linux/include/linux/mtd/sh_flctl.h
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   1/*
   2 * SuperH FLCTL nand controller
   3 *
   4 * Copyright © 2008 Renesas Solutions Corp.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18 */
  19
  20#ifndef __SH_FLCTL_H__
  21#define __SH_FLCTL_H__
  22
  23#include <linux/completion.h>
  24#include <linux/mtd/mtd.h>
  25#include <linux/mtd/nand.h>
  26#include <linux/mtd/partitions.h>
  27#include <linux/pm_qos.h>
  28
  29/* FLCTL registers */
  30#define FLCMNCR(f)              (f->reg + 0x0)
  31#define FLCMDCR(f)              (f->reg + 0x4)
  32#define FLCMCDR(f)              (f->reg + 0x8)
  33#define FLADR(f)                (f->reg + 0xC)
  34#define FLADR2(f)               (f->reg + 0x3C)
  35#define FLDATAR(f)              (f->reg + 0x10)
  36#define FLDTCNTR(f)             (f->reg + 0x14)
  37#define FLINTDMACR(f)           (f->reg + 0x18)
  38#define FLBSYTMR(f)             (f->reg + 0x1C)
  39#define FLBSYCNT(f)             (f->reg + 0x20)
  40#define FLDTFIFO(f)             (f->reg + 0x24)
  41#define FLECFIFO(f)             (f->reg + 0x28)
  42#define FLTRCR(f)               (f->reg + 0x2C)
  43#define FLHOLDCR(f)             (f->reg + 0x38)
  44#define FL4ECCRESULT0(f)        (f->reg + 0x80)
  45#define FL4ECCRESULT1(f)        (f->reg + 0x84)
  46#define FL4ECCRESULT2(f)        (f->reg + 0x88)
  47#define FL4ECCRESULT3(f)        (f->reg + 0x8C)
  48#define FL4ECCCR(f)             (f->reg + 0x90)
  49#define FL4ECCCNT(f)            (f->reg + 0x94)
  50#define FLERRADR(f)             (f->reg + 0x98)
  51
  52/* FLCMNCR control bits */
  53#define _4ECCCNTEN      (0x1 << 24)
  54#define _4ECCEN         (0x1 << 23)
  55#define _4ECCCORRECT    (0x1 << 22)
  56#define SHBUSSEL        (0x1 << 20)
  57#define SEL_16BIT       (0x1 << 19)
  58#define SNAND_E         (0x1 << 18)     /* SNAND (0=512 1=2048)*/
  59#define QTSEL_E         (0x1 << 17)
  60#define ENDIAN          (0x1 << 16)     /* 1 = little endian */
  61#define FCKSEL_E        (0x1 << 15)
  62#define ACM_SACCES_MODE (0x01 << 10)
  63#define NANWF_E         (0x1 << 9)
  64#define SE_D            (0x1 << 8)      /* Spare area disable */
  65#define CE1_ENABLE      (0x1 << 4)      /* Chip Enable 1 */
  66#define CE0_ENABLE      (0x1 << 3)      /* Chip Enable 0 */
  67#define TYPESEL_SET     (0x1 << 0)
  68
  69/*
  70 * Clock settings using the PULSEx registers from FLCMNCR
  71 *
  72 * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E
  73 * to control the clock divider used between the High-Speed Peripheral Clock
  74 * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit
  75 * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16
  76 * bit version the divider is seperate for the pulse width of high and low
  77 * signals.
  78 */
  79#define PULSE3  (0x1 << 27)
  80#define PULSE2  (0x1 << 17)
  81#define PULSE1  (0x1 << 15)
  82#define PULSE0  (0x1 << 9)
  83#define CLK_8B_0_5                      PULSE1
  84#define CLK_8B_1                        0x0
  85#define CLK_8B_1_5                      (PULSE1 | PULSE2)
  86#define CLK_8B_2                        PULSE0
  87#define CLK_8B_3                        (PULSE0 | PULSE1 | PULSE2)
  88#define CLK_8B_4                        (PULSE0 | PULSE2)
  89#define CLK_16B_6L_2H                   PULSE0
  90#define CLK_16B_9L_3H                   (PULSE0 | PULSE1 | PULSE2)
  91#define CLK_16B_12L_4H                  (PULSE0 | PULSE2)
  92
  93/* FLCMDCR control bits */
  94#define ADRCNT2_E       (0x1 << 31)     /* 5byte address enable */
  95#define ADRMD_E         (0x1 << 26)     /* Sector address access */
  96#define CDSRC_E         (0x1 << 25)     /* Data buffer selection */
  97#define DOSR_E          (0x1 << 24)     /* Status read check */
  98#define SELRW           (0x1 << 21)     /*  0:read 1:write */
  99#define DOADR_E         (0x1 << 20)     /* Address stage execute */
 100#define ADRCNT_1        (0x00 << 18)    /* Address data bytes: 1byte */
 101#define ADRCNT_2        (0x01 << 18)    /* Address data bytes: 2byte */
 102#define ADRCNT_3        (0x02 << 18)    /* Address data bytes: 3byte */
 103#define ADRCNT_4        (0x03 << 18)    /* Address data bytes: 4byte */
 104#define DOCMD2_E        (0x1 << 17)     /* 2nd cmd stage execute */
 105#define DOCMD1_E        (0x1 << 16)     /* 1st cmd stage execute */
 106
 107/* FLINTDMACR control bits */
 108#define ESTERINTE       (0x1 << 24)     /* ECC error interrupt enable */
 109#define AC1CLR          (0x1 << 19)     /* ECC FIFO clear */
 110#define AC0CLR          (0x1 << 18)     /* Data FIFO clear */
 111#define DREQ0EN         (0x1 << 16)     /* FLDTFIFODMA Request Enable */
 112#define ECERB           (0x1 << 9)      /* ECC error */
 113#define STERB           (0x1 << 8)      /* Status error */
 114#define STERINTE        (0x1 << 4)      /* Status error enable */
 115
 116/* FLTRCR control bits */
 117#define TRSTRT          (0x1 << 0)      /* translation start */
 118#define TREND           (0x1 << 1)      /* translation end */
 119
 120/*
 121 * FLHOLDCR control bits
 122 *
 123 * HOLDEN: Bus Occupancy Enable (inverted)
 124 * Enable this bit when the external bus might be used in between transfers.
 125 * If not set and the bus gets used by other modules, a deadlock occurs.
 126 */
 127#define HOLDEN          (0x1 << 0)
 128
 129/* FL4ECCCR control bits */
 130#define _4ECCFA         (0x1 << 2)      /* 4 symbols correct fault */
 131#define _4ECCEND        (0x1 << 1)      /* 4 symbols end */
 132#define _4ECCEXST       (0x1 << 0)      /* 4 symbols exist */
 133
 134#define LOOP_TIMEOUT_MAX        0x00010000
 135
 136enum flctl_ecc_res_t {
 137        FL_SUCCESS,
 138        FL_REPAIRABLE,
 139        FL_ERROR,
 140        FL_TIMEOUT
 141};
 142
 143struct dma_chan;
 144
 145struct sh_flctl {
 146        struct mtd_info         mtd;
 147        struct nand_chip        chip;
 148        struct platform_device  *pdev;
 149        struct dev_pm_qos_request pm_qos;
 150        void __iomem            *reg;
 151
 152        uint8_t done_buff[2048 + 64];   /* max size 2048 + 64 */
 153        int     read_bytes;
 154        unsigned int index;
 155        int     seqin_column;           /* column in SEQIN cmd */
 156        int     seqin_page_addr;        /* page_addr in SEQIN cmd */
 157        uint32_t seqin_read_cmd;                /* read cmd in SEQIN cmd */
 158        int     erase1_page_addr;       /* page_addr in ERASE1 cmd */
 159        uint32_t erase_ADRCNT;          /* bits of FLCMDCR in ERASE1 cmd */
 160        uint32_t rw_ADRCNT;     /* bits of FLCMDCR in READ WRITE cmd */
 161        uint32_t flcmncr_base;  /* base value of FLCMNCR */
 162        uint32_t flintdmacr_base;       /* irq enable bits */
 163
 164        unsigned page_size:1;   /* NAND page size (0 = 512, 1 = 2048) */
 165        unsigned hwecc:1;       /* Hardware ECC (0 = disabled, 1 = enabled) */
 166        unsigned holden:1;      /* Hardware has FLHOLDCR and HOLDEN is set */
 167        unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
 168
 169        /* DMA related objects */
 170        struct dma_chan         *chan_fifo0_rx;
 171        struct dma_chan         *chan_fifo0_tx;
 172        struct completion       dma_complete;
 173};
 174
 175struct sh_flctl_platform_data {
 176        struct mtd_partition    *parts;
 177        int                     nr_parts;
 178        unsigned long           flcmncr_val;
 179
 180        unsigned has_hwecc:1;
 181        unsigned use_holden:1;
 182
 183        unsigned int            slave_id_fifo0_tx;
 184        unsigned int            slave_id_fifo0_rx;
 185};
 186
 187static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
 188{
 189        return container_of(mtdinfo, struct sh_flctl, mtd);
 190}
 191
 192#endif  /* __SH_FLCTL_H__ */
 193
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.