1/* 2 * mv643xx.h - MV-643XX Internal registers definition file. 3 * 4 * Copyright 2002 Momentum Computer, Inc. 5 * Author: Matthew Dharm <mdharm@momenco.com> 6 * Copyright 2002 GALILEO TECHNOLOGY, LTD. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13#ifndef __ASM_MV643XX_H 14#define __ASM_MV643XX_H 15 16#include <asm/types.h> 17#include <linux/mv643xx_eth.h> 18#include <linux/mv643xx_i2c.h> 19 20/****************************************/ 21/* Processor Address Space */ 22/****************************************/ 23 24/* DDR SDRAM BAR and size registers */ 25 26#define MV64340_CS_0_BASE_ADDR 0x008 27#define MV64340_CS_0_SIZE 0x010 28#define MV64340_CS_1_BASE_ADDR 0x208 29#define MV64340_CS_1_SIZE 0x210 30#define MV64340_CS_2_BASE_ADDR 0x018 31#define MV64340_CS_2_SIZE 0x020 32#define MV64340_CS_3_BASE_ADDR 0x218 33#define MV64340_CS_3_SIZE 0x220 34 35/* Devices BAR and size registers */ 36 37#define MV64340_DEV_CS0_BASE_ADDR 0x028 38#define MV64340_DEV_CS0_SIZE 0x030 39#define MV64340_DEV_CS1_BASE_ADDR 0x228 40#define MV64340_DEV_CS1_SIZE 0x230 41#define MV64340_DEV_CS2_BASE_ADDR 0x248 42#define MV64340_DEV_CS2_SIZE 0x250 43#define MV64340_DEV_CS3_BASE_ADDR 0x038 44#define MV64340_DEV_CS3_SIZE 0x040 45#define MV64340_BOOTCS_BASE_ADDR 0x238 46#define MV64340_BOOTCS_SIZE 0x240 47 48/* PCI 0 BAR and size registers */ 49 50#define MV64340_PCI_0_IO_BASE_ADDR 0x048 51#define MV64340_PCI_0_IO_SIZE 0x050 52#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058 53#define MV64340_PCI_0_MEMORY0_SIZE 0x060 54#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080 55#define MV64340_PCI_0_MEMORY1_SIZE 0x088 56#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258 57#define MV64340_PCI_0_MEMORY2_SIZE 0x260 58#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280 59#define MV64340_PCI_0_MEMORY3_SIZE 0x288 60 61/* PCI 1 BAR and size registers */ 62#define MV64340_PCI_1_IO_BASE_ADDR 0x090 63#define MV64340_PCI_1_IO_SIZE 0x098 64#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0 65#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8 66#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0 67#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8 68#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0 69#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8 70#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0 71#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8 72 73/* SRAM base address */ 74#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268 75 76/* internal registers space base address */ 77#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068 78 79/* Enables the CS , DEV_CS , PCI 0 and PCI 1 80 windows above */ 81#define MV64340_BASE_ADDR_ENABLE 0x278 82 83/****************************************/ 84/* PCI remap registers */ 85/****************************************/ 86 /* PCI 0 */ 87#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0 88#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 89#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 90#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 91#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 92#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 93#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 94#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 95#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 96 /* PCI 1 */ 97#define MV64340_PCI_1_IO_ADDR_REMAP 0x108 98#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 99#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 100#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 101#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 102#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 103#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 104#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 105#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 106 107#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 108#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 109#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 110#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 111#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 112#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 113#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 114#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 115 116/****************************************/ 117/* CPU Control Registers */ 118/****************************************/ 119 120#define MV64340_CPU_CONFIG 0x000 121#define MV64340_CPU_MODE 0x120 122#define MV64340_CPU_MASTER_CONTROL 0x160 123#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150 124#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158 125#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168 126 127/****************************************/ 128/* SMP RegisterS */ 129/****************************************/ 130 131#define MV64340_SMP_WHO_AM_I 0x200 132#define MV64340_SMP_CPU0_DOORBELL 0x214 133#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C 134#define MV64340_SMP_CPU1_DOORBELL 0x224 135#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C 136#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234 137#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C 138#define MV64340_SMP_SEMAPHOR0 0x244 139#define MV64340_SMP_SEMAPHOR1 0x24c 140#define MV64340_SMP_SEMAPHOR2 0x254 141#define MV64340_SMP_SEMAPHOR3 0x25c 142#define MV64340_SMP_SEMAPHOR4 0x264 143#define MV64340_SMP_SEMAPHOR5 0x26c 144#define MV64340_SMP_SEMAPHOR6 0x274 145#define MV64340_SMP_SEMAPHOR7 0x27c 146 147/****************************************/ 148/* CPU Sync Barrier Register */ 149/****************************************/ 150 151#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 152#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 153#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 154#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 155 156/****************************************/ 157/* CPU Access Protect */ 158/****************************************/ 159 160#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 161#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188 162#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 163#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198 164#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 165#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 166#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 167#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 168 169 170/****************************************/ 171/* CPU Error Report */ 172/****************************************/ 173 174#define MV64340_CPU_ERROR_ADDR_LOW 0x070 175#define MV64340_CPU_ERROR_ADDR_HIGH 0x078 176#define MV64340_CPU_ERROR_DATA_LOW 0x128 177#define MV64340_CPU_ERROR_DATA_HIGH 0x130 178#define MV64340_CPU_ERROR_PARITY 0x138 179#define MV64340_CPU_ERROR_CAUSE 0x140 180#define MV64340_CPU_ERROR_MASK 0x148 181 182/****************************************/ 183/* CPU Interface Debug Registers */ 184/****************************************/ 185 186#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360 187#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368 188#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370 189#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378 190#define MV64340_PUNIT_MMASK 0x3e4 191 192/****************************************/ 193/* Integrated SRAM Registers */ 194/****************************************/ 195 196#define MV64340_SRAM_CONFIG 0x380 197#define MV64340_SRAM_TEST_MODE 0X3F4 198#define MV64340_SRAM_ERROR_CAUSE 0x388 199#define MV64340_SRAM_ERROR_ADDR 0x390 200#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8 201#define MV64340_SRAM_ERROR_DATA_LOW 0x398 202#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0 203#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8 204 205/****************************************/ 206/* SDRAM Configuration */ 207/****************************************/ 208 209#define MV64340_SDRAM_CONFIG 0x1400 210#define MV64340_D_UNIT_CONTROL_LOW 0x1404 211#define MV64340_D_UNIT_CONTROL_HIGH 0x1424 212#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408 213#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c 214#define MV64340_SDRAM_ADDR_CONTROL 0x1410 215#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414 216#define MV64340_SDRAM_OPERATION 0x1418 217#define MV64340_SDRAM_MODE 0x141c 218#define MV64340_EXTENDED_DRAM_MODE 0x1420 219#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 220#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 221#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438 222#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 223#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4 224 225/****************************************/ 226/* SDRAM Error Report */ 227/****************************************/ 228 229#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444 230#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440 231#define MV64340_SDRAM_ERROR_ADDR 0x1450 232#define MV64340_SDRAM_RECEIVED_ECC 0x1448 233#define MV64340_SDRAM_CALCULATED_ECC 0x144c 234#define MV64340_SDRAM_ECC_CONTROL 0x1454 235#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458 236 237/******************************************/ 238/* Controlled Delay Line (CDL) Registers */ 239/******************************************/ 240 241#define MV64340_DFCDL_CONFIG0 0x1480 242#define MV64340_DFCDL_CONFIG1 0x1484 243#define MV64340_DLL_WRITE 0x1488 244#define MV64340_DLL_READ 0x148c 245#define MV64340_SRAM_ADDR 0x1490 246#define MV64340_SRAM_DATA0 0x1494 247#define MV64340_SRAM_DATA1 0x1498 248#define MV64340_SRAM_DATA2 0x149c 249#define MV64340_DFCL_PROBE 0x14a0 250 251/******************************************/ 252/* Debug Registers */ 253/******************************************/ 254 255#define MV64340_DUNIT_DEBUG_LOW 0x1460 256#define MV64340_DUNIT_DEBUG_HIGH 0x1464 257#define MV64340_DUNIT_MMASK 0X1b40 258 259/****************************************/ 260/* Device Parameters */ 261/****************************************/ 262 263#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c 264#define MV64340_DEVICE_BANK1_PARAMETERS 0x460 265#define MV64340_DEVICE_BANK2_PARAMETERS 0x464 266#define MV64340_DEVICE_BANK3_PARAMETERS 0x468 267#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c 268#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0 269#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 270#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc 271#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 272 273/****************************************/ 274/* Device interrupt registers */ 275/****************************************/ 276 277#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0 278#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4 279#define MV64340_DEVICE_ERROR_ADDR 0x4d8 280#define MV64340_DEVICE_ERROR_DATA 0x4dc 281#define MV64340_DEVICE_ERROR_PARITY 0x4e0 282 283/****************************************/ 284/* Device debug registers */ 285/****************************************/ 286 287#define MV64340_DEVICE_DEBUG_LOW 0x4e4 288#define MV64340_DEVICE_DEBUG_HIGH 0x4e8 289#define MV64340_RUNIT_MMASK 0x4f0 290 291/****************************************/ 292/* PCI Slave Address Decoding registers */ 293/****************************************/ 294 295#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08 296#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88 297#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08 298#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88 299#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c 300#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c 301#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c 302#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c 303#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10 304#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90 305#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10 306#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90 307#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18 308#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98 309#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14 310#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94 311#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 312#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 313#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c 314#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c 315#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 316#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 317#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24 318#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4 319#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28 320#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8 321#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 322#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 323#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c 324#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c 325#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c 326#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc 327#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 328#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 329#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 330#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 331#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c 332#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc 333#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c 334#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc 335#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 336#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 337#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 338#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 339#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C 340#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C 341#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 342#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 343#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 344#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 345#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 346#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 347#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 348#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 349#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 350#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 351#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 352#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 353#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c 354#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc 355#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 356#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 357#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 358#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 359#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 360#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 361#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c 362#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec 363#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 364#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 365#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 366#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 367#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 368#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 369#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 370#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 371#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c 372#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc 373#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 374#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 375#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44 376#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4 377#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48 378#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 379 380/***********************************/ 381/* PCI Control Register Map */ 382/***********************************/ 383 384#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 385#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 386#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C 387#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C 388#define MV64340_PCI_0_COMMAND 0xc00 389#define MV64340_PCI_1_COMMAND 0xc80 390#define MV64340_PCI_0_MODE 0xd00 391#define MV64340_PCI_1_MODE 0xd80 392#define MV64340_PCI_0_RETRY 0xc04 393#define MV64340_PCI_1_RETRY 0xc84 394#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 395#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 396#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38 397#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8 398#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00 399#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80 400#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 401#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 402#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c 403#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c 404#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 405#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 406#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 407#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 408#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 409#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 410#define MV64340_PCI_0_P2P_CONFIG 0x1d14 411#define MV64340_PCI_1_P2P_CONFIG 0x1d94 412 413#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 414#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 415#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 416#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 417#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 418#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 419#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 420#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 421#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 422#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 423#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 424#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 425#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 426#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 427#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 428#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 429#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 430#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 431 432#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 433#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 434#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 435#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 436#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 437#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 438#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 439#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 440#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 441#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 442#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 443#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 444#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 445#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 446#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 447#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 448#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 449#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 450 451/****************************************/ 452/* PCI Configuration Access Registers */ 453/****************************************/ 454 455#define MV64340_PCI_0_CONFIG_ADDR 0xcf8 456#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc 457#define MV64340_PCI_1_CONFIG_ADDR 0xc78 458#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c 459#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 460#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 461 462/****************************************/ 463/* PCI Error Report Registers */ 464/****************************************/ 465 466#define MV64340_PCI_0_SERR_MASK 0xc28 467#define MV64340_PCI_1_SERR_MASK 0xca8 468#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40 469#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0 470#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44 471#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4 472#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48 473#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8 474#define MV64340_PCI_0_ERROR_COMMAND 0x1d50 475#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0 476#define MV64340_PCI_0_ERROR_CAUSE 0x1d58 477#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8 478#define MV64340_PCI_0_ERROR_MASK 0x1d5c 479#define MV64340_PCI_1_ERROR_MASK 0x1ddc 480 481/****************************************/ 482/* PCI Debug Registers */ 483/****************************************/ 484 485#define MV64340_PCI_0_MMASK 0X1D24 486#define MV64340_PCI_1_MMASK 0X1DA4 487 488/*********************************************/ 489/* PCI Configuration, Function 0, Registers */ 490/*********************************************/ 491 492#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000 493#define MV64340_PCI_STATUS_AND_COMMAND 0x004 494#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008 495#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C 496 497#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010 498#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014 499#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018 500#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C 501#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 502#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 503#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c 504#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 505#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034 506#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C 507 /* capability list */ 508#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 509#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 510#define MV64340_PCI_VPD_ADDR 0x048 511#define MV64340_PCI_VPD_DATA 0x04c 512#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050 513#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054 514#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 515#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c 516#define MV64340_PCI_X_COMMAND 0x060 517#define MV64340_PCI_X_STATUS 0x064 518#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068 519 520/***********************************************/ 521/* PCI Configuration, Function 1, Registers */ 522/***********************************************/ 523 524#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110 525#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114 526#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118 527#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c 528#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 529#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 530 531/***********************************************/ 532/* PCI Configuration, Function 2, Registers */ 533/***********************************************/ 534 535#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 536#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 537#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 538#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c 539#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 540#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 541 542/***********************************************/ 543/* PCI Configuration, Function 3, Registers */ 544/***********************************************/ 545 546#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 547#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 548#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 549#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c 550#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220 551#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224 552 553/***********************************************/ 554/* PCI Configuration, Function 4, Registers */ 555/***********************************************/ 556 557#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 558#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 559#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 560#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c 561#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420 562#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 563 564/****************************************/ 565/* Messaging Unit Registers (I20) */ 566/****************************************/ 567 568#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 569#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 570#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 571#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C 572#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 573#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 574#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 575#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C 576#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 577#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 578#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 579#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 580#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 581#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 582#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 583#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 584#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 585#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C 586#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 587#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 588#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 589#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC 590 591#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 592#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 593#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 594#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C 595#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 596#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 597#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 598#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC 599#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 600#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 601#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 602#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 603#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 604#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 605#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 606#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 607#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 608#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC 609#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 610#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 611#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 612#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C 613 614#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 615#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 616#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 617#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C 618#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 619#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 620#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 621#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C 622#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 623#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 624#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 625#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 626#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 627#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 628#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 629#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 630#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 631#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C 632#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 633#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 634#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 635#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC 636#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 637#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 638#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 639#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C 640#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 641#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 642#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 643#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC 644#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 645#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 646#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 647#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 648#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 649#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 650#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 651#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 652#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 653#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC 654#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 655#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 656#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 657#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C 658 659/****************************************/ 660/* Ethernet Unit Registers */ 661/****************************************/ 662 663/*******************************************/ 664/* CUNIT Registers */ 665/*******************************************/ 666 667 /* Address Decoding Register Map */ 668 669#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200 670#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208 671#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210 672#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218 673#define MV64340_CUNIT_SIZE0 0xf204 674#define MV64340_CUNIT_SIZE1 0xf20c 675#define MV64340_CUNIT_SIZE2 0xf214 676#define MV64340_CUNIT_SIZE3 0xf21c 677#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 678#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 679#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 680#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254 681#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258 682#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C 683 684 /* Error Report Registers */ 685 686#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310 687#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314 688#define MV64340_CUNIT_ERROR_ADDR 0xf318 689 690 /* Cunit Control Registers */ 691 692#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300 693#define MV64340_CUNIT_CONFIG_REG 0xb40c 694#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 695 696 /* Cunit Debug Registers */ 697 698#define MV64340_CUNIT_DEBUG_LOW 0xf340 699#define MV64340_CUNIT_DEBUG_HIGH 0xf344 700#define MV64340_CUNIT_MMASK 0xf380 701 702 /* MPSCs Clocks Routing Registers */ 703 704#define MV64340_MPSC_ROUTING_REG 0xb400 705#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404 706#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408 707 708 /* MPSCs Interrupts Registers */ 709 710#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) 711#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3)) 712 713#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) 714#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) 715#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) 716#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) 717#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) 718#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) 719#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) 720#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) 721#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) 722#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) 723#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) 724#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) 725#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) 726 727 /* MPSC0 Registers */ 728 729 730/***************************************/ 731/* SDMA Registers */ 732/***************************************/ 733 734#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) 735#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) 736#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) 737#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) 738#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) 739 740#define MV64340_SDMA_CAUSE_REG 0xb800 741#define MV64340_SDMA_MASK_REG 0xb880 742 743/* BRG Interrupts */ 744 745#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) 746#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) 747#define MV64340_BRG_CAUSE_REG 0xb834 748#define MV64340_BRG_MASK_REG 0xb8b4 749 750/****************************************/ 751/* DMA Channel Control */ 752/****************************************/ 753 754#define MV64340_DMA_CHANNEL0_CONTROL 0x840 755#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880 756#define MV64340_DMA_CHANNEL1_CONTROL 0x844 757#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884 758#define MV64340_DMA_CHANNEL2_CONTROL 0x848 759#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888 760#define MV64340_DMA_CHANNEL3_CONTROL 0x84C 761#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C 762 763 764/****************************************/ 765/* IDMA Registers */ 766/****************************************/ 767 768#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800 769#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804 770#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808 771#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C 772#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810 773#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814 774#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818 775#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c 776#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820 777#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824 778#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828 779#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C 780#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 781#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 782#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 783#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C 784#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 785#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 786#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 787#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C 788 789 /* IDMA Address Decoding Base Address Registers */ 790 791#define MV64340_DMA_BASE_ADDR_REG0 0xa00 792#define MV64340_DMA_BASE_ADDR_REG1 0xa08 793#define MV64340_DMA_BASE_ADDR_REG2 0xa10 794#define MV64340_DMA_BASE_ADDR_REG3 0xa18 795#define MV64340_DMA_BASE_ADDR_REG4 0xa20 796#define MV64340_DMA_BASE_ADDR_REG5 0xa28 797#define MV64340_DMA_BASE_ADDR_REG6 0xa30 798#define MV64340_DMA_BASE_ADDR_REG7 0xa38 799 800 /* IDMA Address Decoding Size Address Register */ 801 802#define MV64340_DMA_SIZE_REG0 0xa04 803#define MV64340_DMA_SIZE_REG1 0xa0c 804#define MV64340_DMA_SIZE_REG2 0xa14 805#define MV64340_DMA_SIZE_REG3 0xa1c 806#define MV64340_DMA_SIZE_REG4 0xa24 807#define MV64340_DMA_SIZE_REG5 0xa2c 808#define MV64340_DMA_SIZE_REG6 0xa34 809#define MV64340_DMA_SIZE_REG7 0xa3C 810 811 /* IDMA Address Decoding High Address Remap and Access 812 Protection Registers */ 813 814#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60 815#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64 816#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68 817#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C 818#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80 819#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 820#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 821#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 822#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c 823#define MV64340_DMA_ARBITER_CONTROL 0x860 824#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0 825 826 /* IDMA Headers Retarget Registers */ 827 828#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84 829#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88 830 831 /* IDMA Interrupt Register */ 832 833#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0 834#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4 835#define MV64340_DMA_ERROR_ADDR 0x8c8 836#define MV64340_DMA_ERROR_SELECT 0x8cc 837 838 /* IDMA Debug Register ( for internal use ) */ 839 840#define MV64340_DMA_DEBUG_LOW 0x8e0 841#define MV64340_DMA_DEBUG_HIGH 0x8e4 842#define MV64340_DMA_SPARE 0xA8C 843 844/****************************************/ 845/* Timer_Counter */ 846/****************************************/ 847 848#define MV64340_TIMER_COUNTER0 0x850 849#define MV64340_TIMER_COUNTER1 0x854 850#define MV64340_TIMER_COUNTER2 0x858 851#define MV64340_TIMER_COUNTER3 0x85C 852#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864 853#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 854#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c 855 856/****************************************/ 857/* Watchdog registers */ 858/****************************************/ 859 860#define MV64340_WATCHDOG_CONFIG_REG 0xb410 861#define MV64340_WATCHDOG_VALUE_REG 0xb414 862 863/****************************************/ 864/* I2C Registers */ 865/****************************************/ 866 867#define MV64XXX_I2C_OFFSET 0xc000 868#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 869 870/****************************************/ 871/* GPP Interface Registers */ 872/****************************************/ 873 874#define MV64340_GPP_IO_CONTROL 0xf100 875#define MV64340_GPP_LEVEL_CONTROL 0xf110 876#define MV64340_GPP_VALUE 0xf104 877#define MV64340_GPP_INTERRUPT_CAUSE 0xf108 878#define MV64340_GPP_INTERRUPT_MASK0 0xf10c 879#define MV64340_GPP_INTERRUPT_MASK1 0xf114 880#define MV64340_GPP_VALUE_SET 0xf118 881#define MV64340_GPP_VALUE_CLEAR 0xf11c 882 883/****************************************/ 884/* Interrupt Controller Registers */ 885/****************************************/ 886 887/****************************************/ 888/* Interrupts */ 889/****************************************/ 890 891#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004 892#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c 893#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014 894#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c 895#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024 896#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034 897#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c 898#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044 899#define MV64340_INTERRUPT0_MASK_0_LOW 0x054 900#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c 901#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064 902#define MV64340_INTERRUPT1_MASK_0_LOW 0x074 903#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c 904#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084 905 906/****************************************/ 907/* MPP Interface Registers */ 908/****************************************/ 909 910#define MV64340_MPP_CONTROL0 0xf000 911#define MV64340_MPP_CONTROL1 0xf004 912#define MV64340_MPP_CONTROL2 0xf008 913#define MV64340_MPP_CONTROL3 0xf00c 914 915/****************************************/ 916/* Serial Initialization registers */ 917/****************************************/ 918 919#define MV64340_SERIAL_INIT_LAST_DATA 0xf324 920#define MV64340_SERIAL_INIT_CONTROL 0xf328 921#define MV64340_SERIAL_INIT_STATUS 0xf32c 922 923extern void mv64340_irq_init(unsigned int base); 924 925/* MPSC Platform Device, Driver Data (Shared register regions) */ 926#define MPSC_SHARED_NAME "mpsc_shared" 927 928#define MPSC_ROUTING_BASE_ORDER 0 929#define MPSC_SDMA_INTR_BASE_ORDER 1 930 931#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c 932#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084 933 934struct mpsc_shared_pdata { 935 u32 mrr_val; 936 u32 rcrr_val; 937 u32 tcrr_val; 938 u32 intr_cause_val; 939 u32 intr_mask_val; 940}; 941 942/* MPSC Platform Device, Driver Data */ 943#define MPSC_CTLR_NAME "mpsc" 944 945#define MPSC_BASE_ORDER 0 946#define MPSC_SDMA_BASE_ORDER 1 947#define MPSC_BRG_BASE_ORDER 2 948 949#define MPSC_REG_BLOCK_SIZE 0x0038 950#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18 951#define MPSC_BRG_REG_BLOCK_SIZE 0x0008 952 953struct mpsc_pdata { 954 u8 mirror_regs; 955 u8 cache_mgmt; 956 u8 max_idle; 957 int default_baud; 958 int default_bits; 959 int default_parity; 960 int default_flow; 961 u32 chr_1_val; 962 u32 chr_2_val; 963 u32 chr_10_val; 964 u32 mpcr_val; 965 u32 bcr_val; 966 u8 brg_can_tune; 967 u8 brg_clk_src; 968 u32 brg_clk_freq; 969}; 970 971/* Watchdog Platform Device, Driver Data */ 972#define MV64x60_WDT_NAME "mv64x60_wdt" 973 974struct mv64x60_wdt_pdata { 975 int timeout; /* watchdog expiry in seconds, default 10 */ 976 int bus_clk; /* bus clock in MHz, default 133 */ 977}; 978 979#endif /* __ASM_MV643XX_H */ 980