1/* linux/include/asm-arm/arch-msm/hsusb.h 2 * 3 * Copyright (C) 2008 Google, Inc. 4 * Author: Brian Swetland <swetland@google.com> 5 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18#ifndef __ASM_ARCH_MSM_HSUSB_H 19#define __ASM_ARCH_MSM_HSUSB_H 20 21#include <linux/types.h> 22#include <linux/usb/otg.h> 23 24/** 25 * Supported USB modes 26 * 27 * USB_PERIPHERAL Only peripheral mode is supported. 28 * USB_HOST Only host mode is supported. 29 * USB_OTG OTG mode is supported. 30 * 31 */ 32enum usb_mode_type { 33 USB_NONE = 0, 34 USB_PERIPHERAL, 35 USB_HOST, 36 USB_OTG, 37}; 38 39/** 40 * OTG control 41 * 42 * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host 43 * only configuration. 44 * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY. 45 * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware. 46 * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs. 47 * 48 */ 49enum otg_control_type { 50 OTG_NO_CONTROL = 0, 51 OTG_PHY_CONTROL, 52 OTG_PMIC_CONTROL, 53 OTG_USER_CONTROL, 54}; 55 56/** 57 * PHY used in 58 * 59 * INVALID_PHY Unsupported PHY 60 * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY 61 * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY 62 * 63 */ 64enum msm_usb_phy_type { 65 INVALID_PHY = 0, 66 CI_45NM_INTEGRATED_PHY, 67 SNPS_28NM_INTEGRATED_PHY, 68}; 69 70#define IDEV_CHG_MAX 1500 71#define IUNIT 100 72 73/** 74 * Different states involved in USB charger detection. 75 * 76 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection 77 * process is not yet started. 78 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact. 79 * USB_CHG_STATE_DCD_DONE Data pin contact is detected. 80 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects 81 * between SDP and DCP/CDP). 82 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects 83 * between DCP and CDP). 84 * USB_CHG_STATE_DETECTED USB charger type is determined. 85 * 86 */ 87enum usb_chg_state { 88 USB_CHG_STATE_UNDEFINED = 0, 89 USB_CHG_STATE_WAIT_FOR_DCD, 90 USB_CHG_STATE_DCD_DONE, 91 USB_CHG_STATE_PRIMARY_DONE, 92 USB_CHG_STATE_SECONDARY_DONE, 93 USB_CHG_STATE_DETECTED, 94}; 95 96/** 97 * USB charger types 98 * 99 * USB_INVALID_CHARGER Invalid USB charger. 100 * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port 101 * on USB2.0 compliant host/hub. 102 * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger). 103 * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and 104 * IDEV_CHG_MAX can be drawn irrespective of USB state. 105 * 106 */ 107enum usb_chg_type { 108 USB_INVALID_CHARGER = 0, 109 USB_SDP_CHARGER, 110 USB_DCP_CHARGER, 111 USB_CDP_CHARGER, 112}; 113 114/** 115 * struct msm_otg_platform_data - platform device data 116 * for msm_otg driver. 117 * @phy_init_seq: PHY configuration sequence. val, reg pairs 118 * terminated by -1. 119 * @vbus_power: VBUS power on/off routine. 120 * @power_budget: VBUS power budget in mA (0 will be treated as 500mA). 121 * @mode: Supported mode (OTG/peripheral/host). 122 * @otg_control: OTG switch controlled by user/Id pin 123 * @default_mode: Default operational mode. Applicable only if 124 * OTG switch is controller by user. 125 * @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k 126 * dfab_usb_hs_clk in case of 8660 and 8960. 127 */ 128struct msm_otg_platform_data { 129 int *phy_init_seq; 130 void (*vbus_power)(bool on); 131 unsigned power_budget; 132 enum usb_mode_type mode; 133 enum otg_control_type otg_control; 134 enum usb_mode_type default_mode; 135 enum msm_usb_phy_type phy_type; 136 void (*setup_gpio)(enum usb_otg_state state); 137 char *pclk_src_name; 138}; 139 140/** 141 * struct msm_otg: OTG driver data. Shared by HCD and DCD. 142 * @otg: USB OTG Transceiver structure. 143 * @pdata: otg device platform data. 144 * @irq: IRQ number assigned for HSUSB controller. 145 * @clk: clock struct of usb_hs_clk. 146 * @pclk: clock struct of usb_hs_pclk. 147 * @pclk_src: pclk source for voting. 148 * @phy_reset_clk: clock struct of usb_phy_clk. 149 * @core_clk: clock struct of usb_hs_core_clk. 150 * @regs: ioremapped register base address. 151 * @inputs: OTG state machine inputs(Id, SessValid etc). 152 * @sm_work: OTG state machine work. 153 * @in_lpm: indicates low power mode (LPM) state. 154 * @async_int: Async interrupt arrived. 155 * @cur_power: The amount of mA available from downstream port. 156 * @chg_work: Charger detection work. 157 * @chg_state: The state of charger detection process. 158 * @chg_type: The type of charger attached. 159 * @dcd_retires: The retry count used to track Data contact 160 * detection process. 161 */ 162struct msm_otg { 163 struct usb_phy phy; 164 struct msm_otg_platform_data *pdata; 165 int irq; 166 struct clk *clk; 167 struct clk *pclk; 168 struct clk *pclk_src; 169 struct clk *phy_reset_clk; 170 struct clk *core_clk; 171 void __iomem *regs; 172#define ID 0 173#define B_SESS_VLD 1 174 unsigned long inputs; 175 struct work_struct sm_work; 176 atomic_t in_lpm; 177 int async_int; 178 unsigned cur_power; 179 struct delayed_work chg_work; 180 enum usb_chg_state chg_state; 181 enum usb_chg_type chg_type; 182 u8 dcd_retries; 183}; 184 185#endif 186