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21#ifndef _CX25840_H_
22#define _CX25840_H_
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35
36enum cx25840_video_input {
37
38 CX25840_COMPOSITE1 = 1,
39 CX25840_COMPOSITE2,
40 CX25840_COMPOSITE3,
41 CX25840_COMPOSITE4,
42 CX25840_COMPOSITE5,
43 CX25840_COMPOSITE6,
44 CX25840_COMPOSITE7,
45 CX25840_COMPOSITE8,
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48
49 CX25840_SVIDEO_LUMA1 = 0x10,
50 CX25840_SVIDEO_LUMA2 = 0x20,
51 CX25840_SVIDEO_LUMA3 = 0x30,
52 CX25840_SVIDEO_LUMA4 = 0x40,
53 CX25840_SVIDEO_LUMA5 = 0x50,
54 CX25840_SVIDEO_LUMA6 = 0x60,
55 CX25840_SVIDEO_LUMA7 = 0x70,
56 CX25840_SVIDEO_LUMA8 = 0x80,
57 CX25840_SVIDEO_CHROMA4 = 0x400,
58 CX25840_SVIDEO_CHROMA5 = 0x500,
59 CX25840_SVIDEO_CHROMA6 = 0x600,
60 CX25840_SVIDEO_CHROMA7 = 0x700,
61 CX25840_SVIDEO_CHROMA8 = 0x800,
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63
64 CX25840_SVIDEO1 = 0x510,
65 CX25840_SVIDEO2 = 0x620,
66 CX25840_SVIDEO3 = 0x730,
67 CX25840_SVIDEO4 = 0x840,
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70 CX25840_VIN1_CH1 = 0x80000000,
71 CX25840_VIN2_CH1 = 0x80000001,
72 CX25840_VIN3_CH1 = 0x80000002,
73 CX25840_VIN4_CH1 = 0x80000003,
74 CX25840_VIN5_CH1 = 0x80000004,
75 CX25840_VIN6_CH1 = 0x80000005,
76 CX25840_VIN7_CH1 = 0x80000006,
77 CX25840_VIN8_CH1 = 0x80000007,
78 CX25840_VIN4_CH2 = 0x80000000,
79 CX25840_VIN5_CH2 = 0x80000010,
80 CX25840_VIN6_CH2 = 0x80000020,
81 CX25840_NONE_CH2 = 0x80000030,
82 CX25840_VIN7_CH3 = 0x80000000,
83 CX25840_VIN8_CH3 = 0x80000040,
84 CX25840_NONE0_CH3 = 0x80000080,
85 CX25840_NONE1_CH3 = 0x800000c0,
86 CX25840_SVIDEO_ON = 0x80000100,
87 CX25840_COMPONENT_ON = 0x80000200,
88 CX25840_DIF_ON = 0x80000400,
89};
90
91enum cx25840_audio_input {
92
93 CX25840_AUDIO_SERIAL,
94 CX25840_AUDIO4 = 4,
95 CX25840_AUDIO5,
96 CX25840_AUDIO6,
97 CX25840_AUDIO7,
98 CX25840_AUDIO8,
99};
100
101enum cx25840_io_pin {
102 CX25840_PIN_DVALID_PRGM0 = 0,
103 CX25840_PIN_FIELD_PRGM1,
104 CX25840_PIN_HRESET_PRGM2,
105 CX25840_PIN_VRESET_HCTL_PRGM3,
106 CX25840_PIN_IRQ_N_PRGM4,
107 CX25840_PIN_IR_TX_PRGM6,
108 CX25840_PIN_IR_RX_PRGM5,
109 CX25840_PIN_GPIO0_PRGM8,
110 CX25840_PIN_GPIO1_PRGM9,
111 CX25840_PIN_SA_SDIN,
112 CX25840_PIN_SA_SDOUT,
113 CX25840_PIN_PLL_CLK_PRGM7,
114 CX25840_PIN_CHIP_SEL_VIPCLK,
115};
116
117enum cx25840_io_pad {
118
119 CX25840_PAD_DEFAULT = 0,
120 CX25840_PAD_ACTIVE,
121 CX25840_PAD_VACTIVE,
122 CX25840_PAD_CBFLAG,
123 CX25840_PAD_VID_DATA_EXT0,
124 CX25840_PAD_VID_DATA_EXT1,
125 CX25840_PAD_GPO0,
126 CX25840_PAD_GPO1,
127 CX25840_PAD_GPO2,
128 CX25840_PAD_GPO3,
129 CX25840_PAD_IRQ_N,
130 CX25840_PAD_AC_SYNC,
131 CX25840_PAD_AC_SDOUT,
132 CX25840_PAD_PLL_CLK,
133 CX25840_PAD_VRESET,
134 CX25840_PAD_RESERVED,
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136 CX25840_PAD_XTI_X5_DLL,
137 CX25840_PAD_AUX_PLL,
138 CX25840_PAD_VID_PLL,
139 CX25840_PAD_XTI,
140
141 CX25840_PAD_GPI0,
142 CX25840_PAD_GPI1,
143 CX25840_PAD_GPI2,
144 CX25840_PAD_GPI3,
145};
146
147enum cx25840_io_pin_strength {
148 CX25840_PIN_DRIVE_MEDIUM = 0,
149 CX25840_PIN_DRIVE_SLOW,
150 CX25840_PIN_DRIVE_FAST,
151};
152
153enum cx23885_io_pin {
154 CX23885_PIN_IR_RX_GPIO19,
155 CX23885_PIN_IR_TX_GPIO20,
156 CX23885_PIN_I2S_SDAT_GPIO21,
157 CX23885_PIN_I2S_WCLK_GPIO22,
158 CX23885_PIN_I2S_BCLK_GPIO23,
159 CX23885_PIN_IRQ_N_GPIO16,
160};
161
162enum cx23885_io_pad {
163 CX23885_PAD_IR_RX,
164 CX23885_PAD_GPIO19,
165 CX23885_PAD_IR_TX,
166 CX23885_PAD_GPIO20,
167 CX23885_PAD_I2S_SDAT,
168 CX23885_PAD_GPIO21,
169 CX23885_PAD_I2S_WCLK,
170 CX23885_PAD_GPIO22,
171 CX23885_PAD_I2S_BCLK,
172 CX23885_PAD_GPIO23,
173 CX23885_PAD_IRQ_N,
174 CX23885_PAD_GPIO16,
175};
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183
184struct cx25840_platform_data {
185 int pvr150_workaround;
186};
187
188#endif
189