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33#include <linux/init.h>
34#include <linux/io.h>
35#include <linux/module.h>
36#include <linux/interrupt.h>
37#include <linux/clk.h>
38#include <linux/device.h>
39#include <linux/delay.h>
40#include <linux/slab.h>
41#include <linux/of_address.h>
42#include <linux/of_irq.h>
43#include <linux/of_platform.h>
44
45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/initval.h>
49#include <sound/soc.h>
50#include <sound/dmaengine_pcm.h>
51
52#include "fsl_ssi.h"
53#include "imx-pcm.h"
54
55#ifdef PPC
56#define read_ssi(addr) in_be32(addr)
57#define write_ssi(val, addr) out_be32(addr, val)
58#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
59#else
60#define read_ssi(addr) readl(addr)
61#define write_ssi(val, addr) writel(val, addr)
62
63
64
65
66static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
67{
68 u32 val = readl(addr);
69 val = (val & ~clear) | set;
70 writel(val, addr);
71}
72#endif
73
74
75
76
77
78
79
80
81
82#define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
83 SNDRV_PCM_RATE_CONTINUOUS)
84
85
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96
97
98
99#ifdef __BIG_ENDIAN
100#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
103#else
104#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
107#endif
108
109
110#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
111 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
112 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
113 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
114 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
115
116
117
118
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120
121
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126
127
128
129
130
131struct fsl_ssi_private {
132 struct ccsr_ssi __iomem *ssi;
133 dma_addr_t ssi_phys;
134 unsigned int irq;
135 struct snd_pcm_substream *first_stream;
136 struct snd_pcm_substream *second_stream;
137 unsigned int fifo_depth;
138 struct snd_soc_dai_driver cpu_dai_drv;
139 struct device_attribute dev_attr;
140 struct platform_device *pdev;
141
142 bool new_binding;
143 bool ssi_on_imx;
144 bool imx_ac97;
145 bool use_dma;
146 struct clk *clk;
147 struct snd_dmaengine_dai_dma_data dma_params_tx;
148 struct snd_dmaengine_dai_dma_data dma_params_rx;
149 struct imx_dma_data filter_data_tx;
150 struct imx_dma_data filter_data_rx;
151 struct imx_pcm_fiq_params fiq_params;
152
153 struct {
154 unsigned int rfrc;
155 unsigned int tfrc;
156 unsigned int cmdau;
157 unsigned int cmddu;
158 unsigned int rxt;
159 unsigned int rdr1;
160 unsigned int rdr0;
161 unsigned int tde1;
162 unsigned int tde0;
163 unsigned int roe1;
164 unsigned int roe0;
165 unsigned int tue1;
166 unsigned int tue0;
167 unsigned int tfs;
168 unsigned int rfs;
169 unsigned int tls;
170 unsigned int rls;
171 unsigned int rff1;
172 unsigned int rff0;
173 unsigned int tfe1;
174 unsigned int tfe0;
175 } stats;
176
177 char name[1];
178};
179
180
181
182
183
184
185
186
187
188
189
190
191
192static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
193{
194 struct fsl_ssi_private *ssi_private = dev_id;
195 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
196 irqreturn_t ret = IRQ_NONE;
197 __be32 sisr;
198 __be32 sisr2 = 0;
199
200
201
202
203
204 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
205
206 if (sisr & CCSR_SSI_SISR_RFRC) {
207 ssi_private->stats.rfrc++;
208 sisr2 |= CCSR_SSI_SISR_RFRC;
209 ret = IRQ_HANDLED;
210 }
211
212 if (sisr & CCSR_SSI_SISR_TFRC) {
213 ssi_private->stats.tfrc++;
214 sisr2 |= CCSR_SSI_SISR_TFRC;
215 ret = IRQ_HANDLED;
216 }
217
218 if (sisr & CCSR_SSI_SISR_CMDAU) {
219 ssi_private->stats.cmdau++;
220 ret = IRQ_HANDLED;
221 }
222
223 if (sisr & CCSR_SSI_SISR_CMDDU) {
224 ssi_private->stats.cmddu++;
225 ret = IRQ_HANDLED;
226 }
227
228 if (sisr & CCSR_SSI_SISR_RXT) {
229 ssi_private->stats.rxt++;
230 ret = IRQ_HANDLED;
231 }
232
233 if (sisr & CCSR_SSI_SISR_RDR1) {
234 ssi_private->stats.rdr1++;
235 ret = IRQ_HANDLED;
236 }
237
238 if (sisr & CCSR_SSI_SISR_RDR0) {
239 ssi_private->stats.rdr0++;
240 ret = IRQ_HANDLED;
241 }
242
243 if (sisr & CCSR_SSI_SISR_TDE1) {
244 ssi_private->stats.tde1++;
245 ret = IRQ_HANDLED;
246 }
247
248 if (sisr & CCSR_SSI_SISR_TDE0) {
249 ssi_private->stats.tde0++;
250 ret = IRQ_HANDLED;
251 }
252
253 if (sisr & CCSR_SSI_SISR_ROE1) {
254 ssi_private->stats.roe1++;
255 sisr2 |= CCSR_SSI_SISR_ROE1;
256 ret = IRQ_HANDLED;
257 }
258
259 if (sisr & CCSR_SSI_SISR_ROE0) {
260 ssi_private->stats.roe0++;
261 sisr2 |= CCSR_SSI_SISR_ROE0;
262 ret = IRQ_HANDLED;
263 }
264
265 if (sisr & CCSR_SSI_SISR_TUE1) {
266 ssi_private->stats.tue1++;
267 sisr2 |= CCSR_SSI_SISR_TUE1;
268 ret = IRQ_HANDLED;
269 }
270
271 if (sisr & CCSR_SSI_SISR_TUE0) {
272 ssi_private->stats.tue0++;
273 sisr2 |= CCSR_SSI_SISR_TUE0;
274 ret = IRQ_HANDLED;
275 }
276
277 if (sisr & CCSR_SSI_SISR_TFS) {
278 ssi_private->stats.tfs++;
279 ret = IRQ_HANDLED;
280 }
281
282 if (sisr & CCSR_SSI_SISR_RFS) {
283 ssi_private->stats.rfs++;
284 ret = IRQ_HANDLED;
285 }
286
287 if (sisr & CCSR_SSI_SISR_TLS) {
288 ssi_private->stats.tls++;
289 ret = IRQ_HANDLED;
290 }
291
292 if (sisr & CCSR_SSI_SISR_RLS) {
293 ssi_private->stats.rls++;
294 ret = IRQ_HANDLED;
295 }
296
297 if (sisr & CCSR_SSI_SISR_RFF1) {
298 ssi_private->stats.rff1++;
299 ret = IRQ_HANDLED;
300 }
301
302 if (sisr & CCSR_SSI_SISR_RFF0) {
303 ssi_private->stats.rff0++;
304 ret = IRQ_HANDLED;
305 }
306
307 if (sisr & CCSR_SSI_SISR_TFE1) {
308 ssi_private->stats.tfe1++;
309 ret = IRQ_HANDLED;
310 }
311
312 if (sisr & CCSR_SSI_SISR_TFE0) {
313 ssi_private->stats.tfe0++;
314 ret = IRQ_HANDLED;
315 }
316
317
318 if (sisr2)
319 write_ssi(sisr2, &ssi->sisr);
320
321 return ret;
322}
323
324static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
325{
326 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
327 u8 i2s_mode;
328 u8 wm;
329 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
330
331 if (ssi_private->imx_ac97)
332 i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
333 else
334 i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
335
336
337
338
339
340 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
341
342
343
344
345
346
347
348 write_ssi_mask(&ssi->scr,
349 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
350 CCSR_SSI_SCR_TFR_CLK_DIS |
351 i2s_mode |
352 (synchronous ? CCSR_SSI_SCR_SYN : 0));
353
354 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
355 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
356 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
357
358 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
359 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
360 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376 if (ssi_private->use_dma)
377 wm = ssi_private->fifo_depth - 2;
378 else
379 wm = ssi_private->fifo_depth;
380
381 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
382 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
383 &ssi->sfcsr);
384
385
386
387
388
389
390 if (ssi_private->imx_ac97) {
391
392
393
394 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
395 &ssi->stccr);
396 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
397 &ssi->srccr);
398
399
400
401
402 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
403 &ssi->sacnt);
404 write_ssi(0xff, &ssi->saccdis);
405 write_ssi(0x300, &ssi->saccen);
406
407
408
409
410 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
411 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
412
413 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
414 }
415
416 return 0;
417}
418
419
420
421
422
423
424
425
426
427
428static int fsl_ssi_startup(struct snd_pcm_substream *substream,
429 struct snd_soc_dai *dai)
430{
431 struct snd_soc_pcm_runtime *rtd = substream->private_data;
432 struct fsl_ssi_private *ssi_private =
433 snd_soc_dai_get_drvdata(rtd->cpu_dai);
434 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
435
436
437
438
439
440 if (!ssi_private->first_stream) {
441 ssi_private->first_stream = substream;
442
443
444
445
446
447 if (!ssi_private->imx_ac97)
448 fsl_ssi_setup(ssi_private);
449 } else {
450 if (synchronous) {
451 struct snd_pcm_runtime *first_runtime =
452 ssi_private->first_stream->runtime;
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472 if (!first_runtime->sample_bits) {
473 dev_err(substream->pcm->card->dev,
474 "set sample size in %s stream first\n",
475 substream->stream ==
476 SNDRV_PCM_STREAM_PLAYBACK
477 ? "capture" : "playback");
478 return -EAGAIN;
479 }
480
481 snd_pcm_hw_constraint_minmax(substream->runtime,
482 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
483 first_runtime->sample_bits,
484 first_runtime->sample_bits);
485 }
486
487 ssi_private->second_stream = substream;
488 }
489
490 return 0;
491}
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
507 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
508{
509 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
510 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
511 unsigned int sample_size =
512 snd_pcm_format_width(params_format(hw_params));
513 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
514 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
515
516
517
518
519
520 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
521 return 0;
522
523
524
525
526
527
528
529
530
531
532
533
534 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
535 ssi_private->cpu_dai_drv.symmetric_rates)
536 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
537 else
538 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
539
540 return 0;
541}
542
543
544
545
546
547
548
549
550
551
552static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
553 struct snd_soc_dai *dai)
554{
555 struct snd_soc_pcm_runtime *rtd = substream->private_data;
556 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
557 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
558 unsigned int sier_bits;
559
560
561
562
563
564
565
566
567
568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
569 if (ssi_private->use_dma)
570 sier_bits = SIER_FLAGS;
571 else
572 sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
573 } else {
574 if (ssi_private->use_dma)
575 sier_bits = SIER_FLAGS;
576 else
577 sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
578 }
579
580 switch (cmd) {
581 case SNDRV_PCM_TRIGGER_START:
582 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
584 write_ssi_mask(&ssi->scr, 0,
585 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
586 else
587 write_ssi_mask(&ssi->scr, 0,
588 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
589 break;
590
591 case SNDRV_PCM_TRIGGER_STOP:
592 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
593 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
594 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
595 else
596 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
597
598 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
599 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
600 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
601 break;
602
603 default:
604 return -EINVAL;
605 }
606
607 write_ssi(sier_bits, &ssi->sier);
608
609 return 0;
610}
611
612
613
614
615
616
617static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
618 struct snd_soc_dai *dai)
619{
620 struct snd_soc_pcm_runtime *rtd = substream->private_data;
621 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
622
623 if (ssi_private->first_stream == substream)
624 ssi_private->first_stream = ssi_private->second_stream;
625
626 ssi_private->second_stream = NULL;
627}
628
629static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
630{
631 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
632
633 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
634 dai->playback_dma_data = &ssi_private->dma_params_tx;
635 dai->capture_dma_data = &ssi_private->dma_params_rx;
636 }
637
638 return 0;
639}
640
641static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
642 .startup = fsl_ssi_startup,
643 .hw_params = fsl_ssi_hw_params,
644 .shutdown = fsl_ssi_shutdown,
645 .trigger = fsl_ssi_trigger,
646};
647
648
649static struct snd_soc_dai_driver fsl_ssi_dai_template = {
650 .probe = fsl_ssi_dai_probe,
651 .playback = {
652
653 .channels_min = 2,
654 .channels_max = 2,
655 .rates = FSLSSI_I2S_RATES,
656 .formats = FSLSSI_I2S_FORMATS,
657 },
658 .capture = {
659 .channels_min = 2,
660 .channels_max = 2,
661 .rates = FSLSSI_I2S_RATES,
662 .formats = FSLSSI_I2S_FORMATS,
663 },
664 .ops = &fsl_ssi_dai_ops,
665};
666
667static const struct snd_soc_component_driver fsl_ssi_component = {
668 .name = "fsl-ssi",
669};
670
671
672
673
674
675
676
677static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
678 struct snd_soc_dai *dai)
679{
680 struct snd_soc_pcm_runtime *rtd = substream->private_data;
681 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
682 rtd->cpu_dai);
683 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
684
685 switch (cmd) {
686 case SNDRV_PCM_TRIGGER_START:
687 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
688 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
689 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
690 CCSR_SSI_SIER_TFE0_EN);
691 else
692 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
693 CCSR_SSI_SIER_RFF0_EN);
694 break;
695
696 case SNDRV_PCM_TRIGGER_STOP:
697 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
698 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
699 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
700 CCSR_SSI_SIER_TFE0_EN, 0);
701 else
702 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
703 CCSR_SSI_SIER_RFF0_EN, 0);
704 break;
705
706 default:
707 return -EINVAL;
708 }
709
710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
711 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
712 else
713 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
714
715 return 0;
716}
717
718static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
719 .startup = fsl_ssi_startup,
720 .shutdown = fsl_ssi_shutdown,
721 .trigger = fsl_ssi_ac97_trigger,
722};
723
724static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
725 .ac97_control = 1,
726 .playback = {
727 .stream_name = "AC97 Playback",
728 .channels_min = 2,
729 .channels_max = 2,
730 .rates = SNDRV_PCM_RATE_8000_48000,
731 .formats = SNDRV_PCM_FMTBIT_S16_LE,
732 },
733 .capture = {
734 .stream_name = "AC97 Capture",
735 .channels_min = 2,
736 .channels_max = 2,
737 .rates = SNDRV_PCM_RATE_48000,
738 .formats = SNDRV_PCM_FMTBIT_S16_LE,
739 },
740 .ops = &fsl_ssi_ac97_dai_ops,
741};
742
743
744static struct fsl_ssi_private *fsl_ac97_data;
745
746static void fsl_ssi_ac97_init(void)
747{
748 fsl_ssi_setup(fsl_ac97_data);
749}
750
751void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
752 unsigned short val)
753{
754 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
755 unsigned int lreg;
756 unsigned int lval;
757
758 if (reg > 0x7f)
759 return;
760
761
762 lreg = reg << 12;
763 write_ssi(lreg, &ssi->sacadd);
764
765 lval = val << 4;
766 write_ssi(lval , &ssi->sacdat);
767
768 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
769 CCSR_SSI_SACNT_WR);
770 udelay(100);
771}
772
773unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
774 unsigned short reg)
775{
776 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
777
778 unsigned short val = -1;
779 unsigned int lreg;
780
781 lreg = (reg & 0x7f) << 12;
782 write_ssi(lreg, &ssi->sacadd);
783 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
784 CCSR_SSI_SACNT_RD);
785
786 udelay(100);
787
788 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
789
790 return val;
791}
792
793static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
794 .read = fsl_ssi_ac97_read,
795 .write = fsl_ssi_ac97_write,
796};
797
798
799
800
801
802#define SIER_SHOW(flag, name) \
803 do { \
804 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
805 length += sprintf(buf + length, #name "=%u\n", \
806 ssi_private->stats.name); \
807 } while (0)
808
809
810
811
812
813
814
815
816static ssize_t fsl_sysfs_ssi_show(struct device *dev,
817 struct device_attribute *attr, char *buf)
818{
819 struct fsl_ssi_private *ssi_private =
820 container_of(attr, struct fsl_ssi_private, dev_attr);
821 ssize_t length = 0;
822
823 SIER_SHOW(RFRC_EN, rfrc);
824 SIER_SHOW(TFRC_EN, tfrc);
825 SIER_SHOW(CMDAU_EN, cmdau);
826 SIER_SHOW(CMDDU_EN, cmddu);
827 SIER_SHOW(RXT_EN, rxt);
828 SIER_SHOW(RDR1_EN, rdr1);
829 SIER_SHOW(RDR0_EN, rdr0);
830 SIER_SHOW(TDE1_EN, tde1);
831 SIER_SHOW(TDE0_EN, tde0);
832 SIER_SHOW(ROE1_EN, roe1);
833 SIER_SHOW(ROE0_EN, roe0);
834 SIER_SHOW(TUE1_EN, tue1);
835 SIER_SHOW(TUE0_EN, tue0);
836 SIER_SHOW(TFS_EN, tfs);
837 SIER_SHOW(RFS_EN, rfs);
838 SIER_SHOW(TLS_EN, tls);
839 SIER_SHOW(RLS_EN, rls);
840 SIER_SHOW(RFF1_EN, rff1);
841 SIER_SHOW(RFF0_EN, rff0);
842 SIER_SHOW(TFE1_EN, tfe1);
843 SIER_SHOW(TFE0_EN, tfe0);
844
845 return length;
846}
847
848
849
850
851static void make_lowercase(char *s)
852{
853 char *p = s;
854 char c;
855
856 while ((c = *p)) {
857 if ((c >= 'A') && (c <= 'Z'))
858 *p = c + ('a' - 'A');
859 p++;
860 }
861}
862
863static int fsl_ssi_probe(struct platform_device *pdev)
864{
865 struct fsl_ssi_private *ssi_private;
866 int ret = 0;
867 struct device_attribute *dev_attr = NULL;
868 struct device_node *np = pdev->dev.of_node;
869 const char *p, *sprop;
870 const uint32_t *iprop;
871 struct resource res;
872 char name[64];
873 bool shared;
874 bool ac97 = false;
875
876
877
878
879
880 if (!of_device_is_available(np))
881 return -ENODEV;
882
883
884 sprop = of_get_property(np, "fsl,mode", NULL);
885 if (!sprop) {
886 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
887 return -EINVAL;
888 }
889 if (!strcmp(sprop, "ac97-slave")) {
890 ac97 = true;
891 } else if (strcmp(sprop, "i2s-slave")) {
892 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
893 return -ENODEV;
894 }
895
896
897 p = strrchr(np->full_name, '/') + 1;
898 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
899 GFP_KERNEL);
900 if (!ssi_private) {
901 dev_err(&pdev->dev, "could not allocate DAI object\n");
902 return -ENOMEM;
903 }
904
905 strcpy(ssi_private->name, p);
906
907 ssi_private->use_dma = !of_property_read_bool(np,
908 "fsl,fiq-stream-filter");
909
910 if (ac97) {
911 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
912 sizeof(fsl_ssi_ac97_dai));
913
914 fsl_ac97_data = ssi_private;
915 ssi_private->imx_ac97 = true;
916
917 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
918 } else {
919
920 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
921 sizeof(fsl_ssi_dai_template));
922 }
923 ssi_private->cpu_dai_drv.name = ssi_private->name;
924
925
926 ret = of_address_to_resource(np, 0, &res);
927 if (ret) {
928 dev_err(&pdev->dev, "could not determine device resources\n");
929 return ret;
930 }
931 ssi_private->ssi = of_iomap(np, 0);
932 if (!ssi_private->ssi) {
933 dev_err(&pdev->dev, "could not map device resources\n");
934 return -ENOMEM;
935 }
936 ssi_private->ssi_phys = res.start;
937
938 ssi_private->irq = irq_of_parse_and_map(np, 0);
939 if (ssi_private->irq == 0) {
940 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
941 return -ENXIO;
942 }
943
944
945 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
946 ssi_private->cpu_dai_drv.symmetric_rates = 1;
947
948
949 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
950 if (iprop)
951 ssi_private->fifo_depth = be32_to_cpup(iprop);
952 else
953
954 ssi_private->fifo_depth = 8;
955
956 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
957 u32 dma_events[2];
958 ssi_private->ssi_on_imx = true;
959
960 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
961 if (IS_ERR(ssi_private->clk)) {
962 ret = PTR_ERR(ssi_private->clk);
963 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
964 goto error_irqmap;
965 }
966 ret = clk_prepare_enable(ssi_private->clk);
967 if (ret) {
968 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
969 ret);
970 goto error_irqmap;
971 }
972
973
974
975
976
977 ssi_private->dma_params_tx.maxburst =
978 ssi_private->fifo_depth - 2;
979 ssi_private->dma_params_rx.maxburst =
980 ssi_private->fifo_depth - 2;
981 ssi_private->dma_params_tx.addr =
982 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
983 ssi_private->dma_params_rx.addr =
984 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
985 ssi_private->dma_params_tx.filter_data =
986 &ssi_private->filter_data_tx;
987 ssi_private->dma_params_rx.filter_data =
988 &ssi_private->filter_data_rx;
989 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
990 ssi_private->use_dma) {
991
992
993
994
995
996 ret = of_property_read_u32_array(pdev->dev.of_node,
997 "fsl,ssi-dma-events", dma_events, 2);
998 if (ret && ssi_private->use_dma) {
999 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1000 goto error_clk;
1001 }
1002 }
1003
1004 shared = of_device_is_compatible(of_get_parent(np),
1005 "fsl,spba-bus");
1006
1007 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1008 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1009 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1010 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1011 } else if (ssi_private->use_dma) {
1012
1013 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1014 fsl_ssi_isr, 0, ssi_private->name,
1015 ssi_private);
1016 if (ret < 0) {
1017 dev_err(&pdev->dev, "could not claim irq %u\n",
1018 ssi_private->irq);
1019 goto error_irqmap;
1020 }
1021 }
1022
1023
1024 dev_attr = &ssi_private->dev_attr;
1025 sysfs_attr_init(&dev_attr->attr);
1026 dev_attr->attr.name = "statistics";
1027 dev_attr->attr.mode = S_IRUGO;
1028 dev_attr->show = fsl_sysfs_ssi_show;
1029
1030 ret = device_create_file(&pdev->dev, dev_attr);
1031 if (ret) {
1032 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1033 ssi_private->dev_attr.attr.name);
1034 goto error_clk;
1035 }
1036
1037
1038 dev_set_drvdata(&pdev->dev, ssi_private);
1039
1040 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1041 &ssi_private->cpu_dai_drv, 1);
1042 if (ret) {
1043 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1044 goto error_dev;
1045 }
1046
1047 if (ssi_private->ssi_on_imx) {
1048 if (!ssi_private->use_dma) {
1049
1050
1051
1052
1053
1054
1055
1056
1057 ssi_private->fiq_params.irq = ssi_private->irq;
1058 ssi_private->fiq_params.base = ssi_private->ssi;
1059 ssi_private->fiq_params.dma_params_rx =
1060 &ssi_private->dma_params_rx;
1061 ssi_private->fiq_params.dma_params_tx =
1062 &ssi_private->dma_params_tx;
1063
1064 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1065 if (ret)
1066 goto error_dev;
1067 } else {
1068 ret = imx_pcm_dma_init(pdev);
1069 if (ret)
1070 goto error_dev;
1071 }
1072 }
1073
1074
1075
1076
1077
1078
1079 if (!of_get_property(np, "codec-handle", NULL)) {
1080 ssi_private->new_binding = true;
1081 goto done;
1082 }
1083
1084
1085
1086
1087
1088
1089 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1090
1091 p = strrchr(sprop, ',');
1092 if (p)
1093 sprop = p + 1;
1094 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1095 make_lowercase(name);
1096
1097 ssi_private->pdev =
1098 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1099 if (IS_ERR(ssi_private->pdev)) {
1100 ret = PTR_ERR(ssi_private->pdev);
1101 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1102 goto error_dai;
1103 }
1104
1105done:
1106 if (ssi_private->imx_ac97)
1107 fsl_ssi_ac97_init();
1108
1109 return 0;
1110
1111error_dai:
1112 if (ssi_private->ssi_on_imx)
1113 imx_pcm_dma_exit(pdev);
1114 snd_soc_unregister_component(&pdev->dev);
1115
1116error_dev:
1117 device_remove_file(&pdev->dev, dev_attr);
1118
1119error_clk:
1120 if (ssi_private->ssi_on_imx)
1121 clk_disable_unprepare(ssi_private->clk);
1122
1123error_irqmap:
1124 irq_dispose_mapping(ssi_private->irq);
1125
1126 return ret;
1127}
1128
1129static int fsl_ssi_remove(struct platform_device *pdev)
1130{
1131 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1132
1133 if (!ssi_private->new_binding)
1134 platform_device_unregister(ssi_private->pdev);
1135 if (ssi_private->ssi_on_imx)
1136 imx_pcm_dma_exit(pdev);
1137 snd_soc_unregister_component(&pdev->dev);
1138 dev_set_drvdata(&pdev->dev, NULL);
1139 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1140 if (ssi_private->ssi_on_imx)
1141 clk_disable_unprepare(ssi_private->clk);
1142 irq_dispose_mapping(ssi_private->irq);
1143
1144 return 0;
1145}
1146
1147static const struct of_device_id fsl_ssi_ids[] = {
1148 { .compatible = "fsl,mpc8610-ssi", },
1149 { .compatible = "fsl,imx21-ssi", },
1150 {}
1151};
1152MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1153
1154static struct platform_driver fsl_ssi_driver = {
1155 .driver = {
1156 .name = "fsl-ssi-dai",
1157 .owner = THIS_MODULE,
1158 .of_match_table = fsl_ssi_ids,
1159 },
1160 .probe = fsl_ssi_probe,
1161 .remove = fsl_ssi_remove,
1162};
1163
1164module_platform_driver(fsl_ssi_driver);
1165
1166MODULE_ALIAS("platform:fsl-ssi-dai");
1167MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1168MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1169MODULE_LICENSE("GPL v2");
1170