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15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/clk.h>
18#include <linux/module.h>
19
20#include <sound/soc.h>
21
22#include <mach/dma.h>
23#include "regs-ac97.h"
24#include <linux/platform_data/asoc-s3c.h>
25
26#include "dma.h"
27
28#define AC_CMD_ADDR(x) (x << 16)
29#define AC_CMD_DATA(x) (x & 0xffff)
30
31#define S3C_AC97_DAI_PCM 0
32#define S3C_AC97_DAI_MIC 1
33
34struct s3c_ac97_info {
35 struct clk *ac97_clk;
36 void __iomem *regs;
37 struct mutex lock;
38 struct completion done;
39};
40static struct s3c_ac97_info s3c_ac97;
41
42static struct s3c2410_dma_client s3c_dma_client_out = {
43 .name = "AC97 PCMOut"
44};
45
46static struct s3c2410_dma_client s3c_dma_client_in = {
47 .name = "AC97 PCMIn"
48};
49
50static struct s3c2410_dma_client s3c_dma_client_micin = {
51 .name = "AC97 MicIn"
52};
53
54static struct s3c_dma_params s3c_ac97_pcm_out = {
55 .client = &s3c_dma_client_out,
56 .dma_size = 4,
57};
58
59static struct s3c_dma_params s3c_ac97_pcm_in = {
60 .client = &s3c_dma_client_in,
61 .dma_size = 4,
62};
63
64static struct s3c_dma_params s3c_ac97_mic_in = {
65 .client = &s3c_dma_client_micin,
66 .dma_size = 4,
67};
68
69static void s3c_ac97_activate(struct snd_ac97 *ac97)
70{
71 u32 ac_glbctrl, stat;
72
73 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
74 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
75 return;
76
77 INIT_COMPLETION(s3c_ac97.done);
78
79 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
80 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
81 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
82 msleep(1);
83
84 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
85 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
86 msleep(1);
87
88 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
89 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
90 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
91
92 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
93 pr_err("AC97: Unable to activate!");
94}
95
96static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
97 unsigned short reg)
98{
99 u32 ac_glbctrl, ac_codec_cmd;
100 u32 stat, addr, data;
101
102 mutex_lock(&s3c_ac97.lock);
103
104 s3c_ac97_activate(ac97);
105
106 INIT_COMPLETION(s3c_ac97.done);
107
108 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
109 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
110 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
111
112 udelay(50);
113
114 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
115 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
116 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
117
118 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
119 pr_err("AC97: Unable to read!");
120
121 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
122 addr = (stat >> 16) & 0x7f;
123 data = (stat & 0xffff);
124
125 if (addr != reg)
126 pr_err("ac97: req addr = %02x, rep addr = %02x\n",
127 reg, addr);
128
129 mutex_unlock(&s3c_ac97.lock);
130
131 return (unsigned short)data;
132}
133
134static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
135 unsigned short val)
136{
137 u32 ac_glbctrl, ac_codec_cmd;
138
139 mutex_lock(&s3c_ac97.lock);
140
141 s3c_ac97_activate(ac97);
142
143 INIT_COMPLETION(s3c_ac97.done);
144
145 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
146 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
147 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
148
149 udelay(50);
150
151 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
152 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
153 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
154
155 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
156 pr_err("AC97: Unable to write!");
157
158 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
159 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
160 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
161
162 mutex_unlock(&s3c_ac97.lock);
163}
164
165static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
166{
167 pr_debug("AC97: Cold reset\n");
168 writel(S3C_AC97_GLBCTRL_COLDRESET,
169 s3c_ac97.regs + S3C_AC97_GLBCTRL);
170 msleep(1);
171
172 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
173 msleep(1);
174}
175
176static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
177{
178 u32 stat;
179
180 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
181 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
182 return;
183
184 pr_debug("AC97: Warm reset\n");
185
186 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
187 msleep(1);
188
189 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
190 msleep(1);
191
192 s3c_ac97_activate(ac97);
193}
194
195static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
196{
197 u32 ac_glbctrl, ac_glbstat;
198
199 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
200
201 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
202
203 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
204 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
205 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
206
207 complete(&s3c_ac97.done);
208 }
209
210 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
211 ac_glbctrl |= (1<<30);
212 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
213
214 return IRQ_HANDLED;
215}
216
217static struct snd_ac97_bus_ops s3c_ac97_ops = {
218 .read = s3c_ac97_read,
219 .write = s3c_ac97_write,
220 .warm_reset = s3c_ac97_warm_reset,
221 .reset = s3c_ac97_cold_reset,
222};
223
224static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *dai)
227{
228 struct snd_soc_pcm_runtime *rtd = substream->private_data;
229 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
230 struct s3c_dma_params *dma_data;
231
232 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
233 dma_data = &s3c_ac97_pcm_out;
234 else
235 dma_data = &s3c_ac97_pcm_in;
236
237 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
238
239 return 0;
240}
241
242static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
243 struct snd_soc_dai *dai)
244{
245 u32 ac_glbctrl;
246 struct snd_soc_pcm_runtime *rtd = substream->private_data;
247 struct s3c_dma_params *dma_data =
248 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
249
250 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
251 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
252 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
253 else
254 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
255
256 switch (cmd) {
257 case SNDRV_PCM_TRIGGER_START:
258 case SNDRV_PCM_TRIGGER_RESUME:
259 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
260 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
261 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
262 else
263 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
264 break;
265
266 case SNDRV_PCM_TRIGGER_STOP:
267 case SNDRV_PCM_TRIGGER_SUSPEND:
268 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
269 break;
270 }
271
272 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
273
274 if (!dma_data->ops)
275 dma_data->ops = samsung_dma_get_ops();
276
277 dma_data->ops->started(dma_data->channel);
278
279 return 0;
280}
281
282static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
283 struct snd_pcm_hw_params *params,
284 struct snd_soc_dai *dai)
285{
286 struct snd_soc_pcm_runtime *rtd = substream->private_data;
287 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
288
289 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
290 return -ENODEV;
291 else
292 snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
293
294 return 0;
295}
296
297static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
298 int cmd, struct snd_soc_dai *dai)
299{
300 u32 ac_glbctrl;
301 struct snd_soc_pcm_runtime *rtd = substream->private_data;
302 struct s3c_dma_params *dma_data =
303 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
304
305 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
306 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
307
308 switch (cmd) {
309 case SNDRV_PCM_TRIGGER_START:
310 case SNDRV_PCM_TRIGGER_RESUME:
311 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
312 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
313 break;
314
315 case SNDRV_PCM_TRIGGER_STOP:
316 case SNDRV_PCM_TRIGGER_SUSPEND:
317 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
318 break;
319 }
320
321 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
322
323 if (!dma_data->ops)
324 dma_data->ops = samsung_dma_get_ops();
325
326 dma_data->ops->started(dma_data->channel);
327
328 return 0;
329}
330
331static const struct snd_soc_dai_ops s3c_ac97_dai_ops = {
332 .hw_params = s3c_ac97_hw_params,
333 .trigger = s3c_ac97_trigger,
334};
335
336static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
337 .hw_params = s3c_ac97_hw_mic_params,
338 .trigger = s3c_ac97_mic_trigger,
339};
340
341static struct snd_soc_dai_driver s3c_ac97_dai[] = {
342 [S3C_AC97_DAI_PCM] = {
343 .name = "samsung-ac97",
344 .ac97_control = 1,
345 .playback = {
346 .stream_name = "AC97 Playback",
347 .channels_min = 2,
348 .channels_max = 2,
349 .rates = SNDRV_PCM_RATE_8000_48000,
350 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
351 .capture = {
352 .stream_name = "AC97 Capture",
353 .channels_min = 2,
354 .channels_max = 2,
355 .rates = SNDRV_PCM_RATE_8000_48000,
356 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
357 .ops = &s3c_ac97_dai_ops,
358 },
359 [S3C_AC97_DAI_MIC] = {
360 .name = "samsung-ac97-mic",
361 .ac97_control = 1,
362 .capture = {
363 .stream_name = "AC97 Mic Capture",
364 .channels_min = 1,
365 .channels_max = 1,
366 .rates = SNDRV_PCM_RATE_8000_48000,
367 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
368 .ops = &s3c_ac97_mic_dai_ops,
369 },
370};
371
372static const struct snd_soc_component_driver s3c_ac97_component = {
373 .name = "s3c-ac97",
374};
375
376static int s3c_ac97_probe(struct platform_device *pdev)
377{
378 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
379 struct s3c_audio_pdata *ac97_pdata;
380 int ret;
381
382 ac97_pdata = pdev->dev.platform_data;
383 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
384 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
385 return -EINVAL;
386 }
387
388
389 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
390 if (!dmatx_res) {
391 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
392 return -ENXIO;
393 }
394
395 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
396 if (!dmarx_res) {
397 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
398 return -ENXIO;
399 }
400
401 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
402 if (!dmamic_res) {
403 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
404 return -ENXIO;
405 }
406
407 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
408 if (!irq_res) {
409 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
410 return -ENXIO;
411 }
412
413 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
414 s3c_ac97.regs = devm_ioremap_resource(&pdev->dev, mem_res);
415 if (IS_ERR(s3c_ac97.regs))
416 return PTR_ERR(s3c_ac97.regs);
417
418 s3c_ac97_pcm_out.channel = dmatx_res->start;
419 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
420 s3c_ac97_pcm_in.channel = dmarx_res->start;
421 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
422 s3c_ac97_mic_in.channel = dmamic_res->start;
423 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
424
425 init_completion(&s3c_ac97.done);
426 mutex_init(&s3c_ac97.lock);
427
428 s3c_ac97.ac97_clk = devm_clk_get(&pdev->dev, "ac97");
429 if (IS_ERR(s3c_ac97.ac97_clk)) {
430 dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
431 ret = -ENODEV;
432 goto err2;
433 }
434 clk_prepare_enable(s3c_ac97.ac97_clk);
435
436 if (ac97_pdata->cfg_gpio(pdev)) {
437 dev_err(&pdev->dev, "Unable to configure gpio\n");
438 ret = -EINVAL;
439 goto err3;
440 }
441
442 ret = request_irq(irq_res->start, s3c_ac97_irq,
443 0, "AC97", NULL);
444 if (ret < 0) {
445 dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
446 goto err4;
447 }
448
449 ret = snd_soc_set_ac97_ops(&s3c_ac97_ops);
450 if (ret != 0) {
451 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
452 goto err4;
453 }
454
455 ret = snd_soc_register_component(&pdev->dev, &s3c_ac97_component,
456 s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
457 if (ret)
458 goto err5;
459
460 ret = samsung_asoc_dma_platform_register(&pdev->dev);
461 if (ret) {
462 dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
463 goto err6;
464 }
465
466 return 0;
467err6:
468 snd_soc_unregister_component(&pdev->dev);
469err5:
470 free_irq(irq_res->start, NULL);
471err4:
472err3:
473 clk_disable_unprepare(s3c_ac97.ac97_clk);
474err2:
475 snd_soc_set_ac97_ops(NULL);
476 return ret;
477}
478
479static int s3c_ac97_remove(struct platform_device *pdev)
480{
481 struct resource *irq_res;
482
483 samsung_asoc_dma_platform_unregister(&pdev->dev);
484 snd_soc_unregister_component(&pdev->dev);
485
486 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
487 if (irq_res)
488 free_irq(irq_res->start, NULL);
489
490 clk_disable_unprepare(s3c_ac97.ac97_clk);
491 snd_soc_set_ac97_ops(NULL);
492
493 return 0;
494}
495
496static struct platform_driver s3c_ac97_driver = {
497 .probe = s3c_ac97_probe,
498 .remove = s3c_ac97_remove,
499 .driver = {
500 .name = "samsung-ac97",
501 .owner = THIS_MODULE,
502 },
503};
504
505module_platform_driver(s3c_ac97_driver);
506
507MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
508MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
509MODULE_LICENSE("GPL");
510MODULE_ALIAS("platform:samsung-ac97");
511
