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17#include <linux/clocksource.h>
18#include <linux/clockchips.h>
19#include <linux/cpu.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/sched_clock.h>
28
29#include <asm/mach/time.h>
30
31#include "common.h"
32
33#define TIMER_MATCH_VAL 0x0000
34#define TIMER_COUNT_VAL 0x0004
35#define TIMER_ENABLE 0x0008
36#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37#define TIMER_ENABLE_EN BIT(0)
38#define TIMER_CLEAR 0x000C
39#define DGT_CLK_CTL 0x10
40#define DGT_CLK_CTL_DIV_4 0x3
41#define TIMER_STS_GPT0_CLR_PEND BIT(10)
42
43#define GPT_HZ 32768
44
45#define MSM_DGT_SHIFT 5
46
47static void __iomem *event_base;
48static void __iomem *sts_base;
49
50static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
51{
52 struct clock_event_device *evt = dev_id;
53
54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
56 ctrl &= ~TIMER_ENABLE_EN;
57 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
58 }
59 evt->event_handler(evt);
60 return IRQ_HANDLED;
61}
62
63static int msm_timer_set_next_event(unsigned long cycles,
64 struct clock_event_device *evt)
65{
66 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
67
68 ctrl &= ~TIMER_ENABLE_EN;
69 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
70
71 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
72 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
73
74 if (sts_base)
75 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
76 cpu_relax();
77
78 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
79 return 0;
80}
81
82static void msm_timer_set_mode(enum clock_event_mode mode,
83 struct clock_event_device *evt)
84{
85 u32 ctrl;
86
87 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
88 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
89
90 switch (mode) {
91 case CLOCK_EVT_MODE_RESUME:
92 case CLOCK_EVT_MODE_PERIODIC:
93 break;
94 case CLOCK_EVT_MODE_ONESHOT:
95
96 break;
97 case CLOCK_EVT_MODE_UNUSED:
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 break;
100 }
101 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
102}
103
104static struct clock_event_device __percpu *msm_evt;
105
106static void __iomem *source_base;
107
108static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
109{
110 return readl_relaxed(source_base + TIMER_COUNT_VAL);
111}
112
113static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
114{
115
116
117
118
119 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
120}
121
122static struct clocksource msm_clocksource = {
123 .name = "dg_timer",
124 .rating = 300,
125 .read = msm_read_timer_count,
126 .mask = CLOCKSOURCE_MASK(32),
127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
128};
129
130static int msm_timer_irq;
131static int msm_timer_has_ppi;
132
133static int msm_local_timer_setup(struct clock_event_device *evt)
134{
135 int cpu = smp_processor_id();
136 int err;
137
138 evt->irq = msm_timer_irq;
139 evt->name = "msm_timer";
140 evt->features = CLOCK_EVT_FEAT_ONESHOT;
141 evt->rating = 200;
142 evt->set_mode = msm_timer_set_mode;
143 evt->set_next_event = msm_timer_set_next_event;
144 evt->cpumask = cpumask_of(cpu);
145
146 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
147
148 if (msm_timer_has_ppi) {
149 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
150 } else {
151 err = request_irq(evt->irq, msm_timer_interrupt,
152 IRQF_TIMER | IRQF_NOBALANCING |
153 IRQF_TRIGGER_RISING, "gp_timer", evt);
154 if (err)
155 pr_err("request_irq failed\n");
156 }
157
158 return 0;
159}
160
161static void msm_local_timer_stop(struct clock_event_device *evt)
162{
163 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
164 disable_percpu_irq(evt->irq);
165}
166
167static int msm_timer_cpu_notify(struct notifier_block *self,
168 unsigned long action, void *hcpu)
169{
170
171
172
173
174 switch (action & ~CPU_TASKS_FROZEN) {
175 case CPU_STARTING:
176 msm_local_timer_setup(this_cpu_ptr(msm_evt));
177 break;
178 case CPU_DYING:
179 msm_local_timer_stop(this_cpu_ptr(msm_evt));
180 break;
181 }
182
183 return NOTIFY_OK;
184}
185
186static struct notifier_block msm_timer_cpu_nb = {
187 .notifier_call = msm_timer_cpu_notify,
188};
189
190static notrace u32 msm_sched_clock_read(void)
191{
192 return msm_clocksource.read(&msm_clocksource);
193}
194
195static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
196 bool percpu)
197{
198 struct clocksource *cs = &msm_clocksource;
199 int res = 0;
200
201 msm_timer_irq = irq;
202 msm_timer_has_ppi = percpu;
203
204 msm_evt = alloc_percpu(struct clock_event_device);
205 if (!msm_evt) {
206 pr_err("memory allocation failed for clockevents\n");
207 goto err;
208 }
209
210 if (percpu)
211 res = request_percpu_irq(irq, msm_timer_interrupt,
212 "gp_timer", msm_evt);
213
214 if (res) {
215 pr_err("request_percpu_irq failed\n");
216 } else {
217 res = register_cpu_notifier(&msm_timer_cpu_nb);
218 if (res) {
219 free_percpu_irq(irq, msm_evt);
220 goto err;
221 }
222
223
224 msm_local_timer_setup(__this_cpu_ptr(msm_evt));
225 }
226
227err:
228 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
229 res = clocksource_register_hz(cs, dgt_hz);
230 if (res)
231 pr_err("clocksource_register failed\n");
232 setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
233}
234
235#ifdef CONFIG_OF
236static void __init msm_dt_timer_init(struct device_node *np)
237{
238 u32 freq;
239 int irq;
240 struct resource res;
241 u32 percpu_offset;
242 void __iomem *base;
243 void __iomem *cpu0_base;
244
245 base = of_iomap(np, 0);
246 if (!base) {
247 pr_err("Failed to map event base\n");
248 return;
249 }
250
251
252 irq = irq_of_parse_and_map(np, 1);
253 if (irq <= 0) {
254 pr_err("Can't get irq\n");
255 return;
256 }
257
258
259 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
260 percpu_offset = 0;
261
262 if (of_address_to_resource(np, 0, &res)) {
263 pr_err("Failed to parse DGT resource\n");
264 return;
265 }
266
267 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
268 if (!cpu0_base) {
269 pr_err("Failed to map source base\n");
270 return;
271 }
272
273 if (of_property_read_u32(np, "clock-frequency", &freq)) {
274 pr_err("Unknown frequency\n");
275 return;
276 }
277
278 event_base = base + 0x4;
279 sts_base = base + 0x88;
280 source_base = cpu0_base + 0x24;
281 freq /= 4;
282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
283
284 msm_timer_init(freq, 32, irq, !!percpu_offset);
285}
286CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
287CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
288#endif
289
290static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
291 u32 sts)
292{
293 void __iomem *base;
294
295 base = ioremap(addr, SZ_256);
296 if (!base) {
297 pr_err("Failed to map timer base\n");
298 return -ENOMEM;
299 }
300 event_base = base + event;
301 source_base = base + source;
302 if (sts)
303 sts_base = base + sts;
304
305 return 0;
306}
307
308void __init msm7x01_timer_init(void)
309{
310 struct clocksource *cs = &msm_clocksource;
311
312 if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
313 return;
314 cs->read = msm_read_timer_count_shift;
315 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
316
317 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
318 false);
319}
320
321void __init msm7x30_timer_init(void)
322{
323 if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
324 return;
325 msm_timer_init(24576000 / 4, 32, 1, false);
326}
327
328void __init qsd8x50_timer_init(void)
329{
330 if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
331 return;
332 msm_timer_init(19200000 / 4, 32, 7, false);
333}
334
