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18#include <linux/kernel.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/tegra-powergate.h>
24
25#include "flowctrl.h"
26#include "fuse.h"
27#include "pm.h"
28#include "pmc.h"
29#include "sleep.h"
30
31#define TEGRA_POWER_SYSCLK_POLARITY (1 << 10)
32#define TEGRA_POWER_SYSCLK_OE (1 << 11)
33#define TEGRA_POWER_EFFECT_LP0 (1 << 14)
34#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)
35#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16)
36
37#define PMC_CTRL 0x0
38#define PMC_CTRL_INTR_LOW (1 << 17)
39#define PMC_PWRGATE_TOGGLE 0x30
40#define PMC_PWRGATE_TOGGLE_START (1 << 8)
41#define PMC_REMOVE_CLAMPING 0x34
42#define PMC_PWRGATE_STATUS 0x38
43
44#define PMC_CPUPWRGOOD_TIMER 0xc8
45#define PMC_CPUPWROFF_TIMER 0xcc
46
47static u8 tegra_cpu_domains[] = {
48 0xFF,
49 TEGRA_POWERGATE_CPU1,
50 TEGRA_POWERGATE_CPU2,
51 TEGRA_POWERGATE_CPU3,
52};
53static DEFINE_SPINLOCK(tegra_powergate_lock);
54
55static void __iomem *tegra_pmc_base;
56static bool tegra_pmc_invert_interrupt;
57static struct clk *tegra_pclk;
58
59struct pmc_pm_data {
60 u32 cpu_good_time;
61 u32 cpu_off_time;
62 u32 core_osc_time;
63 u32 core_pmu_time;
64 u32 core_off_time;
65 bool corereq_high;
66 bool sysclkreq_high;
67 bool combined_req;
68 bool cpu_pwr_good_en;
69 u32 lp0_vec_phy_addr;
70 u32 lp0_vec_size;
71 enum tegra_suspend_mode suspend_mode;
72};
73static struct pmc_pm_data pmc_pm_data;
74
75static inline u32 tegra_pmc_readl(u32 reg)
76{
77 return readl(tegra_pmc_base + reg);
78}
79
80static inline void tegra_pmc_writel(u32 val, u32 reg)
81{
82 writel(val, tegra_pmc_base + reg);
83}
84
85static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
86{
87 if (cpuid <= 0 || cpuid >= num_possible_cpus())
88 return -EINVAL;
89 return tegra_cpu_domains[cpuid];
90}
91
92static bool tegra_pmc_powergate_is_powered(int id)
93{
94 return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
95}
96
97static int tegra_pmc_powergate_set(int id, bool new_state)
98{
99 bool old_state;
100 unsigned long flags;
101
102 spin_lock_irqsave(&tegra_powergate_lock, flags);
103
104 old_state = tegra_pmc_powergate_is_powered(id);
105 WARN_ON(old_state == new_state);
106
107 tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
108
109 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
110
111 return 0;
112}
113
114static int tegra_pmc_powergate_remove_clamping(int id)
115{
116 u32 mask;
117
118
119
120
121
122 if (id == TEGRA_POWERGATE_VDEC)
123 mask = (1 << TEGRA_POWERGATE_PCIE);
124 else if (id == TEGRA_POWERGATE_PCIE)
125 mask = (1 << TEGRA_POWERGATE_VDEC);
126 else
127 mask = (1 << id);
128
129 tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
130
131 return 0;
132}
133
134bool tegra_pmc_cpu_is_powered(int cpuid)
135{
136 int id;
137
138 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
139 if (id < 0)
140 return false;
141 return tegra_pmc_powergate_is_powered(id);
142}
143
144int tegra_pmc_cpu_power_on(int cpuid)
145{
146 int id;
147
148 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
149 if (id < 0)
150 return id;
151 return tegra_pmc_powergate_set(id, true);
152}
153
154int tegra_pmc_cpu_remove_clamping(int cpuid)
155{
156 int id;
157
158 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
159 if (id < 0)
160 return id;
161 return tegra_pmc_powergate_remove_clamping(id);
162}
163
164void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
165{
166 u32 val;
167
168 val = tegra_pmc_readl(0);
169 val |= 0x10;
170 tegra_pmc_writel(val, 0);
171}
172
173#ifdef CONFIG_PM_SLEEP
174static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
175{
176 unsigned long long ticks;
177 unsigned long long pclk;
178 static unsigned long tegra_last_pclk;
179
180 if (WARN_ON_ONCE(rate <= 0))
181 pclk = 100000000;
182 else
183 pclk = rate;
184
185 if ((rate != tegra_last_pclk)) {
186 ticks = (us_on * pclk) + 999999ull;
187 do_div(ticks, 1000000);
188 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
189
190 ticks = (us_off * pclk) + 999999ull;
191 do_div(ticks, 1000000);
192 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
193 wmb();
194 }
195 tegra_last_pclk = pclk;
196}
197
198enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
199{
200 return pmc_pm_data.suspend_mode;
201}
202
203void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
204{
205 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
206 return;
207
208 pmc_pm_data.suspend_mode = mode;
209}
210
211void tegra_pmc_suspend(void)
212{
213 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
214}
215
216void tegra_pmc_resume(void)
217{
218 tegra_pmc_writel(0x0, PMC_SCRATCH41);
219}
220
221void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
222{
223 u32 reg, csr_reg;
224 unsigned long rate = 0;
225
226 reg = tegra_pmc_readl(PMC_CTRL);
227 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
228 reg &= ~TEGRA_POWER_EFFECT_LP0;
229
230 switch (tegra_chip_id) {
231 case TEGRA20:
232 case TEGRA30:
233 break;
234 default:
235
236 csr_reg = flowctrl_read_cpu_csr(0);
237 csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
238 csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
239 flowctrl_write_cpu_csr(0, csr_reg);
240 break;
241 }
242
243 switch (mode) {
244 case TEGRA_SUSPEND_LP1:
245 rate = 32768;
246 break;
247 case TEGRA_SUSPEND_LP2:
248 rate = clk_get_rate(tegra_pclk);
249 break;
250 default:
251 break;
252 }
253
254 set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
255 rate);
256
257 tegra_pmc_writel(reg, PMC_CTRL);
258}
259
260void tegra_pmc_suspend_init(void)
261{
262 u32 reg;
263
264
265 reg = tegra_pmc_readl(PMC_CTRL);
266 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
267 tegra_pmc_writel(reg, PMC_CTRL);
268
269 reg = tegra_pmc_readl(PMC_CTRL);
270
271 if (!pmc_pm_data.sysclkreq_high)
272 reg |= TEGRA_POWER_SYSCLK_POLARITY;
273 else
274 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
275
276
277 tegra_pmc_writel(reg, PMC_CTRL);
278
279
280 reg |= TEGRA_POWER_SYSCLK_OE;
281 tegra_pmc_writel(reg, PMC_CTRL);
282}
283#endif
284
285static const struct of_device_id matches[] __initconst = {
286 { .compatible = "nvidia,tegra124-pmc" },
287 { .compatible = "nvidia,tegra114-pmc" },
288 { .compatible = "nvidia,tegra30-pmc" },
289 { .compatible = "nvidia,tegra20-pmc" },
290 { }
291};
292
293void __init tegra_pmc_init_irq(void)
294{
295 struct device_node *np;
296 u32 val;
297
298 np = of_find_matching_node(NULL, matches);
299 BUG_ON(!np);
300
301 tegra_pmc_base = of_iomap(np, 0);
302
303 tegra_pmc_invert_interrupt = of_property_read_bool(np,
304 "nvidia,invert-interrupt");
305
306 val = tegra_pmc_readl(PMC_CTRL);
307 if (tegra_pmc_invert_interrupt)
308 val |= PMC_CTRL_INTR_LOW;
309 else
310 val &= ~PMC_CTRL_INTR_LOW;
311 tegra_pmc_writel(val, PMC_CTRL);
312}
313
314void __init tegra_pmc_init(void)
315{
316 struct device_node *np;
317 u32 prop;
318 enum tegra_suspend_mode suspend_mode;
319 u32 core_good_time[2] = {0, 0};
320 u32 lp0_vec[2] = {0, 0};
321
322 np = of_find_matching_node(NULL, matches);
323 BUG_ON(!np);
324
325 tegra_pclk = of_clk_get_by_name(np, "pclk");
326 WARN_ON(IS_ERR(tegra_pclk));
327
328
329 if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
330 suspend_mode = TEGRA_SUSPEND_NONE;
331 } else {
332 switch (prop) {
333 case 0:
334 suspend_mode = TEGRA_SUSPEND_LP0;
335 break;
336 case 1:
337 suspend_mode = TEGRA_SUSPEND_LP1;
338 break;
339 case 2:
340 suspend_mode = TEGRA_SUSPEND_LP2;
341 break;
342 default:
343 suspend_mode = TEGRA_SUSPEND_NONE;
344 break;
345 }
346 }
347 suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
348
349 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
350 suspend_mode = TEGRA_SUSPEND_NONE;
351 pmc_pm_data.cpu_good_time = prop;
352
353 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
354 suspend_mode = TEGRA_SUSPEND_NONE;
355 pmc_pm_data.cpu_off_time = prop;
356
357 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
358 core_good_time, ARRAY_SIZE(core_good_time)))
359 suspend_mode = TEGRA_SUSPEND_NONE;
360 pmc_pm_data.core_osc_time = core_good_time[0];
361 pmc_pm_data.core_pmu_time = core_good_time[1];
362
363 if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
364 &prop))
365 suspend_mode = TEGRA_SUSPEND_NONE;
366 pmc_pm_data.core_off_time = prop;
367
368 pmc_pm_data.corereq_high = of_property_read_bool(np,
369 "nvidia,core-power-req-active-high");
370
371 pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
372 "nvidia,sys-clock-req-active-high");
373
374 pmc_pm_data.combined_req = of_property_read_bool(np,
375 "nvidia,combined-power-req");
376
377 pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
378 "nvidia,cpu-pwr-good-en");
379
380 if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
381 ARRAY_SIZE(lp0_vec)))
382 if (suspend_mode == TEGRA_SUSPEND_LP0)
383 suspend_mode = TEGRA_SUSPEND_LP1;
384
385 pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
386 pmc_pm_data.lp0_vec_size = lp0_vec[1];
387
388 pmc_pm_data.suspend_mode = suspend_mode;
389}
390
