linux/arch/blackfin/mach-bf527/include/mach/defBF522.h
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   1/*
   2 * Copyright 2007-2010 Analog Devices Inc.
   3 *
   4 * Licensed under the Clear BSD license or the GPL-2 (or later)
   5 */
   6
   7#ifndef _DEF_BF522_H
   8#define _DEF_BF522_H
   9
  10/* ************************************************************** */
  11/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
  12/* ************************************************************** */
  13
  14/* ==== begin from defBF534.h ==== */
  15
  16/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
  17#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
  18#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
  19#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
  20#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
  21#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
  22#define CHIPID        0xFFC00014  /* Device ID Register */
  23
  24
  25/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
  26#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
  27#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
  28#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
  29
  30#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
  31#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
  32#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
  33#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
  34#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
  35#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
  36#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
  37
  38/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
  39#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
  40#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
  41#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
  42#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
  43#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
  44#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
  45#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
  46
  47
  48/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
  49#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
  50#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
  51#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
  52
  53
  54/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
  55#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
  56#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
  57#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
  58#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
  59#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
  60#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
  61#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
  62
  63
  64/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
  65#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
  66#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
  67#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
  68#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
  69#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
  70#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
  71#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
  72#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
  73#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
  74#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
  75#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
  76#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
  77
  78
  79/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
  80#define SPI0_REGBASE                    0xFFC00500
  81#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
  82#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
  83#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
  84#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
  85#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
  86#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
  87#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
  88
  89
  90/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
  91#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
  92#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
  93#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
  94#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
  95
  96#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
  97#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
  98#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
  99#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
 100
 101#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
 102#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
 103#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
 104#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
 105
 106#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
 107#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
 108#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
 109#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
 110
 111#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
 112#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
 113#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
 114#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
 115
 116#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
 117#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
 118#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
 119#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
 120
 121#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
 122#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
 123#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
 124#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
 125
 126#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
 127#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
 128#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
 129#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
 130
 131#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
 132#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
 133#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
 134
 135
 136/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
 137#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
 138#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
 139#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
 140#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
 141#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
 142#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
 143#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
 144#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
 145#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
 146#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
 147#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
 148#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
 149#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
 150#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
 151#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
 152#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
 153#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
 154
 155
 156/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
 157#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
 158#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
 159#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
 160#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
 161#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
 162#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
 163#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
 164#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
 165#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
 166#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
 167#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
 168#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
 169#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
 170#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
 171#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
 172#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
 173#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
 174#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
 175#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
 176#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
 177#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
 178#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
 179
 180
 181/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
 182#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
 183#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
 184#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
 185#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
 186#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
 187#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
 188#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
 189#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
 190#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
 191#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
 192#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
 193#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
 194#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
 195#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
 196#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
 197#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
 198#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
 199#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
 200#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
 201#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
 202#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
 203#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
 204
 205
 206/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
 207#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
 208#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
 209#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
 210#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
 211#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
 212#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
 213#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
 214
 215
 216/* DMA Traffic Control Registers                                                                                                        */
 217#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
 218#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
 219
 220/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
 221#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
 222#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
 223#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
 224#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
 225#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
 226#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
 227#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
 228#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
 229#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
 230#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
 231#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
 232#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
 233#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
 234
 235#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
 236#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
 237#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
 238#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
 239#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
 240#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
 241#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
 242#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
 243#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
 244#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
 245#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
 246#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
 247#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
 248
 249#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
 250#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
 251#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
 252#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
 253#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
 254#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
 255#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
 256#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
 257#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
 258#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
 259#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
 260#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
 261#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
 262
 263#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
 264#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
 265#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
 266#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
 267#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
 268#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
 269#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
 270#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
 271#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
 272#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
 273#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
 274#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
 275#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
 276
 277#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
 278#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
 279#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
 280#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
 281#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
 282#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
 283#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
 284#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
 285#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
 286#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
 287#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
 288#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
 289#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
 290
 291#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
 292#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
 293#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
 294#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
 295#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
 296#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
 297#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
 298#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
 299#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
 300#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
 301#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
 302#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
 303#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
 304
 305#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
 306#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
 307#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
 308#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
 309#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
 310#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
 311#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
 312#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
 313#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
 314#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
 315#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
 316#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
 317#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
 318
 319#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
 320#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
 321#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
 322#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
 323#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
 324#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
 325#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
 326#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
 327#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
 328#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
 329#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
 330#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
 331#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
 332
 333#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
 334#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
 335#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
 336#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
 337#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
 338#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
 339#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
 340#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
 341#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
 342#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
 343#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
 344#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
 345#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
 346
 347#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
 348#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
 349#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
 350#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
 351#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
 352#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
 353#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
 354#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
 355#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
 356#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
 357#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
 358#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
 359#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
 360
 361#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
 362#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
 363#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
 364#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
 365#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
 366#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
 367#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
 368#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
 369#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
 370#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
 371#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
 372#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
 373#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
 374
 375#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
 376#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
 377#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
 378#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
 379#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
 380#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
 381#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
 382#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
 383#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
 384#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
 385#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
 386#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
 387#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
 388
 389#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
 390#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
 391#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
 392#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
 393#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
 394#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
 395#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
 396#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
 397#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
 398#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
 399#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
 400#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
 401#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
 402
 403#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
 404#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
 405#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
 406#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
 407#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
 408#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
 409#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
 410#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
 411#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
 412#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
 413#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
 414#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
 415#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
 416
 417#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
 418#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
 419#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
 420#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
 421#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
 422#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
 423#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
 424#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
 425#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
 426#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
 427#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
 428#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
 429#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
 430
 431#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
 432#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
 433#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
 434#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
 435#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
 436#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
 437#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
 438#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
 439#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
 440#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
 441#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
 442#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
 443#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
 444
 445
 446/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
 447#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
 448#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
 449#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
 450#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
 451#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
 452
 453
 454/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
 455#define TWI0_REGBASE                    0xFFC01400
 456#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
 457#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
 458#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
 459#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
 460#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
 461#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
 462#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
 463#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
 464#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
 465#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
 466#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
 467#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
 468#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
 469#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
 470#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
 471#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
 472
 473
 474/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
 475#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
 476#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
 477#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
 478#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
 479#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
 480#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
 481#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
 482#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
 483#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
 484#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
 485#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
 486#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
 487#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
 488#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
 489#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
 490#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
 491#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
 492
 493
 494/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
 495#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
 496#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
 497#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
 498#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
 499#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
 500#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
 501#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
 502#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
 503#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
 504#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
 505#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
 506#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
 507#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
 508#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
 509#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
 510#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
 511#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
 512
 513
 514/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
 515#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
 516#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
 517#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
 518#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
 519#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
 520#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
 521#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
 522#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
 523#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
 524#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
 525#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
 526#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
 527
 528
 529/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
 530
 531/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
 532#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
 533#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
 534#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
 535#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
 536
 537
 538/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
 539#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
 540#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
 541#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
 542#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
 543#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
 544#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
 545#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
 546
 547#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
 548#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
 549#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
 550#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
 551#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
 552#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
 553#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
 554
 555/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
 556#define PORTF_MUX               0xFFC03210      /* Port F mux control */
 557#define PORTG_MUX               0xFFC03214      /* Port G mux control */
 558#define PORTH_MUX               0xFFC03218      /* Port H mux control */
 559#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
 560#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
 561#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
 562#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
 563#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
 564#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
 565#define PORTF_HYSTERESIS        0xFFC03240      /* Port F Schmitt trigger control */
 566#define PORTG_HYSTERESIS        0xFFC03244      /* Port G Schmitt trigger control */
 567#define PORTH_HYSTERESIS        0xFFC03248      /* Port H Schmitt trigger control */
 568#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
 569#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
 570#define MISCPORT_HYSTERESIS     0xFFC03288      /* Misc Port Schmitt trigger control */
 571
 572
 573/***********************************************************************************
 574** System MMR Register Bits And Macros
 575**
 576** Disclaimer:  All macros are intended to make C and Assembly code more readable.
 577**                              Use these macros carefully, as any that do left shifts for field
 578**                              depositing will result in the lower order bits being destroyed.  Any
 579**                              macro that shifts left to properly position the bit-field should be
 580**                              used as part of an OR to initialize a register and NOT as a dynamic
 581**                              modifier UNLESS the lower order bits are saved and ORed back in when
 582**                              the macro is used.
 583*************************************************************************************/
 584
 585/* CHIPID Masks */
 586#define CHIPID_VERSION         0xF0000000
 587#define CHIPID_FAMILY          0x0FFFF000
 588#define CHIPID_MANUFACTURE     0x00000FFE
 589
 590/* SWRST Masks                                                                                                                                          */
 591#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
 592#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
 593#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
 594#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
 595#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
 596
 597/* SYSCR Masks                                                                                                                                                          */
 598#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
 599#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
 600
 601
 602/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
 603/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
 604
 605#if 0
 606#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
 607
 608#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
 609#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
 610#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
 611#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
 612#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
 613#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
 614#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
 615
 616#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
 617#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
 618#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
 619#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
 620#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
 621#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
 622#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
 623#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
 624
 625#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
 626#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
 627#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
 628#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
 629#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
 630#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
 631#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
 632#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
 633#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
 634#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
 635
 636#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
 637#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
 638#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
 639#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
 640#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
 641#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
 642#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
 643#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
 644#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
 645#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
 646#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
 647#endif
 648
 649/* SIC_IAR0 Macros                                                                                                                      */
 650#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
 651#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
 652#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
 653#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
 654#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
 655#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
 656#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
 657#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
 658
 659/* SIC_IAR1 Macros                                                                                                                      */
 660#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
 661#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
 662#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
 663#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
 664#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
 665#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
 666#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
 667#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
 668
 669/* SIC_IAR2 Macros                                                                                                                      */
 670#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
 671#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
 672#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
 673#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
 674#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
 675#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
 676#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
 677#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
 678
 679/* SIC_IAR3 Macros                                                                                                                      */
 680#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
 681#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
 682#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
 683#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
 684#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
 685#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
 686#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
 687#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
 688
 689
 690/* SIC_IMASK Masks                                                                                                                                              */
 691#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
 692#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
 693#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
 694#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
 695
 696/* SIC_IWR Masks                                                                                                                                                */
 697#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
 698#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
 699#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
 700#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
 701
 702/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
 703/* TIMER_ENABLE Masks                                                                                                   */
 704#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
 705#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
 706#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
 707#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
 708#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
 709#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
 710#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
 711#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
 712
 713/* TIMER_DISABLE Masks                                                                                                  */
 714#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
 715#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
 716#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
 717#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
 718#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
 719#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
 720#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
 721#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
 722
 723/* TIMER_STATUS Masks                                                                                                   */
 724#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
 725#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
 726#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
 727#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
 728#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
 729#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
 730#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
 731#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
 732#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
 733#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
 734#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
 735#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
 736#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
 737#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
 738#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
 739#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
 740#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
 741#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
 742#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
 743#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
 744#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
 745#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
 746#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
 747#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
 748
 749/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
 750#define TOVL_ERR0 TOVF_ERR0
 751#define TOVL_ERR1 TOVF_ERR1
 752#define TOVL_ERR2 TOVF_ERR2
 753#define TOVL_ERR3 TOVF_ERR3
 754#define TOVL_ERR4 TOVF_ERR4
 755#define TOVL_ERR5 TOVF_ERR5
 756#define TOVL_ERR6 TOVF_ERR6
 757#define TOVL_ERR7 TOVF_ERR7
 758
 759/* TIMERx_CONFIG Masks                                                                                                  */
 760#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
 761#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
 762#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
 763#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
 764#define PERIOD_CNT              0x0008  /* Period Count                                                 */
 765#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
 766#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
 767#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
 768#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
 769#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
 770#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
 771#define ERR_TYP                 0xC000  /* Error Type                                                   */
 772
 773/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 774/* EBIU_AMGCTL Masks                                                                                                                                    */
 775#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
 776#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
 777#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
 778#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
 779#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
 780#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
 781
 782/* EBIU_AMBCTL0 Masks                                                                                                                                   */
 783#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
 784#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
 785#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
 786#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
 787#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
 788#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
 789#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
 790#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
 791#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
 792#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
 793#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
 794#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
 795#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
 796#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
 797#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
 798#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
 799#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
 800#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
 801#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
 802#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
 803#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
 804#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
 805#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
 806#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
 807#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
 808#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
 809#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
 810#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
 811#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
 812#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
 813#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
 814#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
 815#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
 816#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
 817#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
 818#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
 819#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
 820#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
 821#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
 822#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
 823#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
 824#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
 825#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
 826#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
 827
 828#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
 829#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
 830#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
 831#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
 832#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
 833#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
 834#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
 835#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
 836#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
 837#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
 838#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
 839#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
 840#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
 841#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
 842#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
 843#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
 844#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
 845#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
 846#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
 847#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
 848#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
 849#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
 850#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
 851#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
 852#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
 853#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
 854#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
 855#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
 856#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
 857#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
 858#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
 859#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
 860#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
 861#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
 862#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
 863#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
 864#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
 865#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
 866#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
 867#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
 868#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
 869#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
 870#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
 871#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
 872
 873/* EBIU_AMBCTL1 Masks                                                                                                                                   */
 874#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
 875#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
 876#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
 877#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
 878#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
 879#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
 880#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
 881#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
 882#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
 883#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
 884#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
 885#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
 886#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
 887#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
 888#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
 889#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
 890#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
 891#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
 892#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
 893#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
 894#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
 895#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
 896#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
 897#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
 898#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
 899#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
 900#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
 901#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
 902#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
 903#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
 904#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
 905#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
 906#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
 907#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
 908#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
 909#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
 910#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
 911#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
 912#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
 913#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
 914#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
 915#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
 916#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
 917#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
 918
 919#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
 920#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
 921#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
 922#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
 923#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
 924#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
 925#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
 926#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
 927#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
 928#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
 929#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
 930#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
 931#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
 932#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
 933#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
 934#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
 935#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
 936#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
 937#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
 938#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
 939#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
 940#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
 941#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
 942#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
 943#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
 944#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
 945#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
 946#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
 947#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
 948#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
 949#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
 950#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
 951#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
 952#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
 953#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
 954#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
 955#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
 956#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
 957#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
 958#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
 959#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
 960#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
 961#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
 962#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
 963
 964
 965/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
 966/* EBIU_SDGCTL Masks                                                                                                                                                    */
 967#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
 968#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
 969#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
 970#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
 971#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
 972#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
 973#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
 974#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
 975#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
 976#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
 977#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
 978#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
 979#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
 980#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
 981#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
 982#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
 983#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
 984#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
 985#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
 986#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
 987#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
 988#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
 989#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
 990#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
 991#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
 992#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
 993#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
 994#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
 995#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
 996#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
 997#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
 998#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
 999#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
1000#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
1001#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
1002#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
1003#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
1004#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
1005#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
1006#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
1007#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
1008#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
1009#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
1010#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
1011#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
1012#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
1013#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
1014
1015/* EBIU_SDBCTL Masks                                                                                                                                            */
1016#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
1017#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
1018#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
1019#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
1020#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
1021#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
1022#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
1023#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
1024#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
1025#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
1026#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
1027
1028/* EBIU_SDSTAT Masks                                                                                                            */
1029#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
1030#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
1031#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
1032#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
1033#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
1034#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
1035
1036
1037/* **************************  DMA CONTROLLER MASKS  ********************************/
1038
1039/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
1040#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
1041#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
1042#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
1043#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
1044#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
1045#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
1046#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
1047#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
1048#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
1049#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
1050#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
1051#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
1052#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
1053#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
1054
1055/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1056/*  PPI_CONTROL Masks                                                                                                   */
1057#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
1058#define PORT_DIR                0x0002          /* PPI Port Direction                           */
1059#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
1060#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
1061#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
1062#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
1063#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
1064#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
1065#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
1066#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
1067#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
1068#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
1069#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
1070#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
1071#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
1072#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
1073#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
1074#define DLENGTH                 0x3800          /* PPI Data Length  */
1075#define POLC                    0x4000          /* PPI Clock Polarity                           */
1076#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
1077
1078/* PPI_STATUS Masks                                                                                                             */
1079#define FLD                             0x0400          /* Field Indicator                                      */
1080#define FT_ERR                  0x0800          /* Frame Track Error                            */
1081#define OVR                             0x1000          /* FIFO Overflow Error                          */
1082#define UNDR                    0x2000          /* FIFO Underrun Error                          */
1083#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
1084#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
1085
1086
1087/* Omit CAN masks from defBF534.h */
1088
1089/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
1090/* PORT_MUX Masks                                                                                                                       */
1091#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
1092#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
1093#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
1094
1095#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
1096#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
1097#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
1098#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
1099
1100#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
1101#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
1102#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
1103
1104#define PFTE                    0x0010                  /* Port F Timer Enable                          */
1105#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
1106#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
1107
1108#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
1109#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
1110#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
1111
1112#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
1113#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
1114#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
1115
1116#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
1117#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
1118#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
1119
1120#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
1121#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
1122#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
1123
1124#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
1125#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
1126#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
1127
1128#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
1129#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
1130#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
1131
1132#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
1133#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
1134#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
1135
1136/* entry addresses of the user-callable Boot ROM functions */
1137
1138#define _BOOTROM_RESET 0xEF000000
1139#define _BOOTROM_FINAL_INIT 0xEF000002
1140#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1141#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1142#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1143#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1144#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1145#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1146#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1147
1148/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1149#define PGDE_UART   PFDE_UART
1150#define PGDE_DMA    PFDE_DMA
1151#define CKELOW          SCKELOW
1152
1153/* ==== end from defBF534.h ==== */
1154
1155/* HOST Port Registers */
1156
1157#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
1158#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
1159#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
1160
1161/* Counter Registers */
1162
1163#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
1164#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
1165#define                       CNT_STATUS  0xffc03508   /* Status Register */
1166#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
1167#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
1168#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
1169#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
1170#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
1171
1172/* OTP/FUSE Registers */
1173
1174#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
1175#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
1176#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
1177#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
1178
1179/* Security Registers */
1180
1181#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
1182#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
1183#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
1184
1185/* OTP Read/Write Data Buffer Registers */
1186
1187#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1188#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1189#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1190#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1191
1192/* NFC Registers */
1193
1194#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
1195#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
1196#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
1197#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
1198#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
1199#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
1200#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
1201#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
1202#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
1203#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
1204#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
1205#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
1206#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
1207#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
1208#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
1209#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
1210
1211/* ********************************************************** */
1212/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
1213/*     and MULTI BIT READ MACROS                              */
1214/* ********************************************************** */
1215
1216/* Bit masks for HOST_CONTROL */
1217
1218#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
1219#define                  HOST_CNTR_nHOST_EN  0x0
1220#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
1221#define                 HOST_CNTR_nHOST_END  0x0
1222#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
1223#define                HOST_CNTR_nDATA_SIZE  0x0
1224#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
1225#define                 HOST_CNTR_nHOST_RST  0x0
1226#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
1227#define                 HOST_CNTR_nHRDY_OVR  0x0
1228#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
1229#define                 HOST_CNTR_nINT_MODE  0x0
1230#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
1231#define                   HOST_CNTR_ nBT_EN  0x0
1232#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
1233#define                      HOST_CNTR_nEHW  0x0
1234#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
1235#define                      HOST_CNTR_nEHR  0x0
1236#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
1237#define                      HOST_CNTR_nBDR  0x0
1238
1239/* Bit masks for HOST_STATUS */
1240
1241#define                     HOST_STAT_READY  0x1        /* DMA Ready */
1242#define                    HOST_STAT_nREADY  0x0
1243#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
1244#define                 HOST_STAT_nFIFOFULL  0x0
1245#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
1246#define                HOST_STAT_nFIFOEMPTY  0x0
1247#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
1248#define                 HOST_STAT_nCOMPLETE  0x0
1249#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
1250#define                     HOST_STAT_nHSHK  0x0
1251#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
1252#define                  HOST_STAT_nTIMEOUT  0x0
1253#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
1254#define                     HOST_STAT_nHIRQ  0x0
1255#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
1256#define               HOST_STAT_nALLOW_CNFG  0x0
1257#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
1258#define                  HOST_STAT_nDMA_DIR  0x0
1259#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
1260#define                      HOST_STAT_nBTE  0x0
1261#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
1262#define              HOST_STAT_nHOSTRD_DONE  0x0
1263
1264/* Bit masks for HOST_TIMEOUT */
1265
1266#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
1267
1268/* Bit masks for SECURE_SYSSWT */
1269
1270#define                   EMUDABL  0x1        /* Emulation Disable. */
1271#define                  nEMUDABL  0x0
1272#define                   RSTDABL  0x2        /* Reset Disable */
1273#define                  nRSTDABL  0x0
1274#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
1275#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
1276#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
1277#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
1278#define                  nDMA0OVR  0x0
1279#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
1280#define                  nDMA1OVR  0x0
1281#define                    EMUOVR  0x4000     /* Emulation Override */
1282#define                   nEMUOVR  0x0
1283#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
1284#define                   nOTPSEN  0x0
1285#define                    L2DABL  0x70000    /* L2 Memory Disable. */
1286
1287/* Bit masks for SECURE_CONTROL */
1288
1289#define                   SECURE0  0x1        /* SECURE 0 */
1290#define                  nSECURE0  0x0
1291#define                   SECURE1  0x2        /* SECURE 1 */
1292#define                  nSECURE1  0x0
1293#define                   SECURE2  0x4        /* SECURE 2 */
1294#define                  nSECURE2  0x0
1295#define                   SECURE3  0x8        /* SECURE 3 */
1296#define                  nSECURE3  0x0
1297
1298/* Bit masks for SECURE_STATUS */
1299
1300#define                   SECMODE  0x3        /* Secured Mode Control State */
1301#define                       NMI  0x4        /* Non Maskable Interrupt */
1302#define                      nNMI  0x0
1303#define                   AFVALID  0x8        /* Authentication Firmware Valid */
1304#define                  nAFVALID  0x0
1305#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
1306#define                   nAFEXIT  0x0
1307#define                   SECSTAT  0xe0       /* Secure Status */
1308
1309#endif /* _DEF_BF522_H */
1310