LXR linux/arch/sh/include/asm/processor.h

   1#ifndef __ASM_SH_PROCESSOR_H
   2#define __ASM_SH_PROCESSOR_H
   3
   4#include <asm/cpu-features.h>
   5#include <asm/segment.h>
   6#include <asm/cache.h>
   7
   8#ifndef __ASSEMBLY__
   9/*
  10 *  CPU type and hardware bug flags. Kept separately for each CPU.
  11 *
  12 *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
  13 *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
  14 *  for parsing the subtype in get_cpu_subtype().
  15 */
  16enum cpu_type {
  17        /* SH-2 types */
  18        CPU_SH7619,
  19
  20        /* SH-2A types */
  21        CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
  22        CPU_MXG,
  23
  24        /* SH-3 types */
  25        CPU_SH7705, CPU_SH7706, CPU_SH7707,
  26        CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
  27        CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
  28        CPU_SH7720, CPU_SH7721, CPU_SH7729,
  29
  30        /* SH-4 types */
  31        CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
  32        CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
  33
  34        /* SH-4A types */
  35        CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
  36        CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
  37
  38        /* SH4AL-DSP types */
  39        CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
  40
  41        /* SH-5 types */
  42        CPU_SH5_101, CPU_SH5_103,
  43
  44        /* Unknown subtype */
  45        CPU_SH_NONE
  46};
  47
  48enum cpu_family {
  49        CPU_FAMILY_SH2,
  50        CPU_FAMILY_SH2A,
  51        CPU_FAMILY_SH3,
  52        CPU_FAMILY_SH4,
  53        CPU_FAMILY_SH4A,
  54        CPU_FAMILY_SH4AL_DSP,
  55        CPU_FAMILY_SH5,
  56        CPU_FAMILY_UNKNOWN,
  57};
  58
  59/*
  60 * TLB information structure
  61 *
  62 * Defined for both I and D tlb, per-processor.
  63 */
  64struct tlb_info {
  65        unsigned long long next;
  66        unsigned long long first;
  67        unsigned long long last;
  68
  69        unsigned int entries;
  70        unsigned int step;
  71
  72        unsigned long flags;
  73};
  74
  75struct sh_cpuinfo {
  76        unsigned int type, family;
  77        int cut_major, cut_minor;
  78        unsigned long loops_per_jiffy;
  79        unsigned long asid_cache;
  80
  81        struct cache_info icache;       /* Primary I-cache */
  82        struct cache_info dcache;       /* Primary D-cache */
  83        struct cache_info scache;       /* Secondary cache */
  84
  85        /* TLB info */
  86        struct tlb_info itlb;
  87        struct tlb_info dtlb;
  88
  89        unsigned int phys_bits;
  90        unsigned long flags;
  91} __attribute__ ((aligned(L1_CACHE_BYTES)));
  92
  93extern struct sh_cpuinfo cpu_data[];
  94#define boot_cpu_data cpu_data[0]
  95#define current_cpu_data cpu_data[smp_processor_id()]
  96#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
  97
  98#define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
  99#define cpu_relax()     barrier()
 100
 101void default_idle(void);
 102void stop_this_cpu(void *);
 103
 104/* Forward decl */
 105struct seq_operations;
 106struct task_struct;
 107
 108extern struct pt_regs fake_swapper_regs;
 109
 110extern void cpu_init(void);
 111extern void cpu_probe(void);
 112
 113/* arch/sh/kernel/process.c */
 114extern unsigned int xstate_size;
 115extern void free_thread_xstate(struct task_struct *);
 116extern struct kmem_cache *task_xstate_cachep;
 117
 118/* arch/sh/mm/alignment.c */
 119extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
 120extern int set_unalign_ctl(struct task_struct *, unsigned int val);
 121
 122#define GET_UNALIGN_CTL(tsk, addr)      get_unalign_ctl((tsk), (addr))
 123#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 124
 125/* arch/sh/mm/init.c */
 126extern unsigned int mem_init_done;
 127
 128/* arch/sh/kernel/setup.c */
 129const char *get_cpu_subtype(struct sh_cpuinfo *c);
 130extern const struct seq_operations cpuinfo_op;
 131
 132/* thread_struct flags */
 133#define SH_THREAD_UAC_NOPRINT   (1 << 0)
 134#define SH_THREAD_UAC_SIGBUS    (1 << 1)
 135#define SH_THREAD_UAC_MASK      (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
 136
 137/* processor boot mode configuration */
 138#define MODE_PIN0 (1 << 0)
 139#define MODE_PIN1 (1 << 1)
 140#define MODE_PIN2 (1 << 2)
 141#define MODE_PIN3 (1 << 3)
 142#define MODE_PIN4 (1 << 4)
 143#define MODE_PIN5 (1 << 5)
 144#define MODE_PIN6 (1 << 6)
 145#define MODE_PIN7 (1 << 7)
 146#define MODE_PIN8 (1 << 8)
 147#define MODE_PIN9 (1 << 9)
 148#define MODE_PIN10 (1 << 10)
 149#define MODE_PIN11 (1 << 11)
 150#define MODE_PIN12 (1 << 12)
 151#define MODE_PIN13 (1 << 13)
 152#define MODE_PIN14 (1 << 14)
 153#define MODE_PIN15 (1 << 15)
 154
 155int generic_mode_pins(void);
 156int test_mode_pin(int pin);
 157
 158#ifdef CONFIG_VSYSCALL
 159int vsyscall_init(void);
 160#else
 161#define vsyscall_init() do { } while (0)
 162#endif
 163
 164/*
 165 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
 166 */
 167#ifdef CONFIG_CPU_SH2A
 168extern unsigned int instruction_size(unsigned int insn);
 169#elif defined(CONFIG_SUPERH32)
 170#define instruction_size(insn)  (2)
 171#else
 172#define instruction_size(insn)  (4)
 173#endif
 174
 175#endif /* __ASSEMBLY__ */
 176
 177#ifdef CONFIG_SUPERH32
 178# include <asm/processor_32.h>
 179#else
 180# include <asm/processor_64.h>
 181#endif
 182
 183#endif /* __ASM_SH_PROCESSOR_H */
 184