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35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <linux/dmi.h>
45#include <linux/gfp.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include "ahci.h"
50
51#define DRV_NAME "ahci"
52#define DRV_VERSION "3.0"
53
54enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
58};
59
60enum board_ids {
61
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
65 board_ahci_yes_fbs,
66
67
68 board_ahci_mcp65,
69 board_ahci_mcp77,
70 board_ahci_mcp89,
71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700,
74 board_ahci_vt8251,
75
76
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81};
82
83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88#ifdef CONFIG_PM
89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
91#endif
92
93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100};
101
102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105};
106
107static const struct ata_port_info ahci_port_info[] = {
108
109 [board_ahci] = {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
114 },
115 [board_ahci_ign_iferr] = {
116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
117 .flags = AHCI_FLAG_COMMON,
118 .pio_mask = ATA_PIO4,
119 .udma_mask = ATA_UDMA6,
120 .port_ops = &ahci_ops,
121 },
122 [board_ahci_nosntf] = {
123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
128 },
129 [board_ahci_yes_fbs] = {
130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
136
137 [board_ahci_mcp65] = {
138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_mcp77] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 [board_ahci_mcp89] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_mv] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_sb600] = {
168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_pmp_retry_srst_ops,
175 },
176 [board_ahci_sb700] = {
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_pmp_retry_srst_ops,
182 },
183 [board_ahci_vt8251] = {
184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_vt8251_ops,
189 },
190};
191
192static const struct pci_device_id ahci_pci_tbl[] = {
193
194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci },
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci },
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci },
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci },
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci },
199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr },
200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci },
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci },
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci },
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci },
204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci },
205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf },
206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci },
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci },
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci },
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci },
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci },
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci },
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci },
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci },
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci },
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci },
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci },
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci },
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci },
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci },
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci },
221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci },
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci },
223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci },
224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci },
225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci },
226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci },
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci },
228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci },
229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci },
230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci },
231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci },
232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci },
233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci },
234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci },
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci },
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci },
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci },
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci },
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci },
240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci },
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci },
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci },
243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci },
244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci },
245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci },
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci },
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci },
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci },
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci },
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci },
251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci },
252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci },
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci },
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci },
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci },
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci },
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci },
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci },
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci },
260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci },
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci },
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci },
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci },
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci },
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci },
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci },
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci },
268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci },
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci },
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci },
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci },
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci },
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci },
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci },
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci },
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci },
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci },
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci },
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci },
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci },
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci },
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci },
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci },
284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci },
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci },
286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci },
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci },
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci },
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci },
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci },
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci },
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci },
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci },
294 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci },
295 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci },
296 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci },
297 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci },
298 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci },
299
300
301 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
302 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
303
304 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
305 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
306
307
308 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 },
309 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 },
310 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 },
311 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 },
312 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 },
313 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 },
314 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 },
315
316
317 { PCI_VDEVICE(AMD, 0x7800), board_ahci },
318 { PCI_VDEVICE(AMD, 0x7900), board_ahci },
319
320 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
321 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
322
323
324 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 },
325 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 },
326
327
328 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },
329 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },
330 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },
331 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },
332 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },
333 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },
334 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },
335 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },
336 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },
337 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },
338 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },
339 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },
340 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },
341 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },
342 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },
343 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },
344 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },
345 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },
346 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },
347 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },
348 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },
349 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },
350 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },
351 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },
352 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },
353 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },
354 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },
355 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },
356 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },
357 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },
358 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },
359 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },
360 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },
361 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },
362 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },
363 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },
364 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },
365 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },
366 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },
367 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },
368 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },
369 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },
370 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },
371 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },
372 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },
373 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },
374 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },
375 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },
376 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },
377 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },
378 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },
379 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },
380 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },
381 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },
382 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },
383 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },
384 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },
385 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },
386 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },
387 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },
388 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },
389 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },
390 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },
391 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },
392 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },
393 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },
394 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },
395 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },
396 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },
397 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },
398 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },
399 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },
400 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },
401 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },
402 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },
403 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },
404 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },
405 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },
406 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },
407 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },
408 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },
409 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },
410 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },
411 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },
412
413
414 { PCI_VDEVICE(SI, 0x1184), board_ahci },
415 { PCI_VDEVICE(SI, 0x1185), board_ahci },
416 { PCI_VDEVICE(SI, 0x0186), board_ahci },
417
418
419 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },
420
421
422 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },
423 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },
424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
425 .class = PCI_CLASS_STORAGE_SATA_AHCI,
426 .class_mask = 0xffffff,
427 .driver_data = board_ahci_yes_fbs },
428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
429 .driver_data = board_ahci_yes_fbs },
430 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
431 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
432 .driver_data = board_ahci_yes_fbs },
433 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
434 .driver_data = board_ahci_yes_fbs },
435 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
436 .driver_data = board_ahci_yes_fbs },
437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
438 .driver_data = board_ahci_yes_fbs },
439 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
440 .driver_data = board_ahci_yes_fbs },
441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
442 .driver_data = board_ahci_yes_fbs },
443
444
445 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },
446
447
448 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },
449 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },
450 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },
451 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },
452
453
454 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
455
456
457 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
458 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
459
460 { }
461};
462
463
464static struct pci_driver ahci_pci_driver = {
465 .name = DRV_NAME,
466 .id_table = ahci_pci_tbl,
467 .probe = ahci_init_one,
468 .remove = ata_pci_remove_one,
469#ifdef CONFIG_PM
470 .suspend = ahci_pci_device_suspend,
471 .resume = ahci_pci_device_resume,
472#endif
473};
474
475#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
476static int marvell_enable;
477#else
478static int marvell_enable = 1;
479#endif
480module_param(marvell_enable, int, 0644);
481MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
482
483
484static void ahci_pci_save_initial_config(struct pci_dev *pdev,
485 struct ahci_host_priv *hpriv)
486{
487 unsigned int force_port_map = 0;
488 unsigned int mask_port_map = 0;
489
490 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
491 dev_info(&pdev->dev, "JMB361 has only one port\n");
492 force_port_map = 1;
493 }
494
495
496
497
498
499
500 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
501 if (pdev->device == 0x6121)
502 mask_port_map = 0x3;
503 else
504 mask_port_map = 0xf;
505 dev_info(&pdev->dev,
506 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
507 }
508
509 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
510 mask_port_map);
511}
512
513static int ahci_pci_reset_controller(struct ata_host *host)
514{
515 struct pci_dev *pdev = to_pci_dev(host->dev);
516
517 ahci_reset_controller(host);
518
519 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
520 struct ahci_host_priv *hpriv = host->private_data;
521 u16 tmp16;
522
523
524 pci_read_config_word(pdev, 0x92, &tmp16);
525 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
526 tmp16 |= hpriv->port_map;
527 pci_write_config_word(pdev, 0x92, tmp16);
528 }
529 }
530
531 return 0;
532}
533
534static void ahci_pci_init_controller(struct ata_host *host)
535{
536 struct ahci_host_priv *hpriv = host->private_data;
537 struct pci_dev *pdev = to_pci_dev(host->dev);
538 void __iomem *port_mmio;
539 u32 tmp;
540 int mv;
541
542 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
543 if (pdev->device == 0x6121)
544 mv = 2;
545 else
546 mv = 4;
547 port_mmio = __ahci_port_base(host, mv);
548
549 writel(0, port_mmio + PORT_IRQ_MASK);
550
551
552 tmp = readl(port_mmio + PORT_IRQ_STAT);
553 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
554 if (tmp)
555 writel(tmp, port_mmio + PORT_IRQ_STAT);
556 }
557
558 ahci_init_controller(host);
559}
560
561static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
562 unsigned long deadline)
563{
564 struct ata_port *ap = link->ap;
565 bool online;
566 int rc;
567
568 DPRINTK("ENTER\n");
569
570 ahci_stop_engine(ap);
571
572 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
573 deadline, &online, NULL);
574
575 ahci_start_engine(ap);
576
577 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
578
579
580
581
582 return online ? -EAGAIN : rc;
583}
584
585static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
586 unsigned long deadline)
587{
588 struct ata_port *ap = link->ap;
589 struct ahci_port_priv *pp = ap->private_data;
590 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
591 struct ata_taskfile tf;
592 bool online;
593 int rc;
594
595 ahci_stop_engine(ap);
596
597
598 ata_tf_init(link->device, &tf);
599 tf.command = ATA_BUSY;
600 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
601
602 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
603 deadline, &online, NULL);
604
605 ahci_start_engine(ap);
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620 if (online) {
621 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
622 ahci_check_ready);
623 if (rc)
624 ahci_kick_engine(ap);
625 }
626 return rc;
627}
628
629#ifdef CONFIG_PM
630static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
631{
632 struct ata_host *host = pci_get_drvdata(pdev);
633 struct ahci_host_priv *hpriv = host->private_data;
634 void __iomem *mmio = hpriv->mmio;
635 u32 ctl;
636
637 if (mesg.event & PM_EVENT_SUSPEND &&
638 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
639 dev_err(&pdev->dev,
640 "BIOS update required for suspend/resume\n");
641 return -EIO;
642 }
643
644 if (mesg.event & PM_EVENT_SLEEP) {
645
646
647
648
649 ctl = readl(mmio + HOST_CTL);
650 ctl &= ~HOST_IRQ_EN;
651 writel(ctl, mmio + HOST_CTL);
652 readl(mmio + HOST_CTL);
653 }
654
655 return ata_pci_device_suspend(pdev, mesg);
656}
657
658static int ahci_pci_device_resume(struct pci_dev *pdev)
659{
660 struct ata_host *host = pci_get_drvdata(pdev);
661 int rc;
662
663 rc = ata_pci_device_do_resume(pdev);
664 if (rc)
665 return rc;
666
667 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
668 rc = ahci_pci_reset_controller(host);
669 if (rc)
670 return rc;
671
672 ahci_pci_init_controller(host);
673 }
674
675 ata_host_resume(host);
676
677 return 0;
678}
679#endif
680
681static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
682{
683 int rc;
684
685
686
687
688
689 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
690 return 0;
691
692 if (using_dac &&
693 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
694 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
695 if (rc) {
696 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
697 if (rc) {
698 dev_err(&pdev->dev,
699 "64-bit DMA enable failed\n");
700 return rc;
701 }
702 }
703 } else {
704 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
705 if (rc) {
706 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
707 return rc;
708 }
709 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
710 if (rc) {
711 dev_err(&pdev->dev,
712 "32-bit consistent DMA enable failed\n");
713 return rc;
714 }
715 }
716 return 0;
717}
718
719static void ahci_pci_print_info(struct ata_host *host)
720{
721 struct pci_dev *pdev = to_pci_dev(host->dev);
722 u16 cc;
723 const char *scc_s;
724
725 pci_read_config_word(pdev, 0x0a, &cc);
726 if (cc == PCI_CLASS_STORAGE_IDE)
727 scc_s = "IDE";
728 else if (cc == PCI_CLASS_STORAGE_SATA)
729 scc_s = "SATA";
730 else if (cc == PCI_CLASS_STORAGE_RAID)
731 scc_s = "RAID";
732 else
733 scc_s = "unknown";
734
735 ahci_print_info(host, scc_s);
736}
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756static void ahci_p5wdh_workaround(struct ata_host *host)
757{
758 static struct dmi_system_id sysids[] = {
759 {
760 .ident = "P5W DH Deluxe",
761 .matches = {
762 DMI_MATCH(DMI_SYS_VENDOR,
763 "ASUSTEK COMPUTER INC"),
764 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
765 },
766 },
767 { }
768 };
769 struct pci_dev *pdev = to_pci_dev(host->dev);
770
771 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
772 dmi_check_system(sysids)) {
773 struct ata_port *ap = host->ports[1];
774
775 dev_info(&pdev->dev,
776 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
777
778 ap->ops = &ahci_p5wdh_ops;
779 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
780 }
781}
782
783
784static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
785{
786 static const struct dmi_system_id sysids[] = {
787
788
789
790
791
792
793
794 {
795 .ident = "ASUS M2A-VM",
796 .matches = {
797 DMI_MATCH(DMI_BOARD_VENDOR,
798 "ASUSTeK Computer INC."),
799 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
800 },
801 .driver_data = "20071026",
802 },
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819 {
820 .ident = "MSI K9A2 Platinum",
821 .matches = {
822 DMI_MATCH(DMI_BOARD_VENDOR,
823 "MICRO-STAR INTER"),
824 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
825 },
826 },
827
828
829
830
831
832
833
834
835 {
836 .ident = "MSI K9AGM2",
837 .matches = {
838 DMI_MATCH(DMI_BOARD_VENDOR,
839 "MICRO-STAR INTER"),
840 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
841 },
842 },
843
844
845
846
847 {
848 .ident = "ASUS M3A",
849 .matches = {
850 DMI_MATCH(DMI_BOARD_VENDOR,
851 "ASUSTeK Computer INC."),
852 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
853 },
854 },
855 { }
856 };
857 const struct dmi_system_id *match;
858 int year, month, date;
859 char buf[9];
860
861 match = dmi_first_match(sysids);
862 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
863 !match)
864 return false;
865
866 if (!match->driver_data)
867 goto enable_64bit;
868
869 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
870 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
871
872 if (strcmp(buf, match->driver_data) >= 0)
873 goto enable_64bit;
874 else {
875 dev_warn(&pdev->dev,
876 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
877 match->ident);
878 return false;
879 }
880
881enable_64bit:
882 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
883 return true;
884}
885
886static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
887{
888 static const struct dmi_system_id broken_systems[] = {
889 {
890 .ident = "HP Compaq nx6310",
891 .matches = {
892 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
893 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
894 },
895
896 .driver_data = (void *)0x1FUL,
897 },
898 {
899 .ident = "HP Compaq 6720s",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
902 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
903 },
904
905 .driver_data = (void *)0x1FUL,
906 },
907
908 { }
909 };
910 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
911
912 if (dmi) {
913 unsigned long slot = (unsigned long)dmi->driver_data;
914
915 return slot == PCI_SLOT(pdev->devfn);
916 }
917
918 return false;
919}
920
921static bool ahci_broken_suspend(struct pci_dev *pdev)
922{
923 static const struct dmi_system_id sysids[] = {
924
925
926
927
928
929
930
931
932
933
934
935
936
937 {
938 .ident = "dv4",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
941 DMI_MATCH(DMI_PRODUCT_NAME,
942 "HP Pavilion dv4 Notebook PC"),
943 },
944 .driver_data = "20090105",
945 },
946 {
947 .ident = "dv5",
948 .matches = {
949 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
950 DMI_MATCH(DMI_PRODUCT_NAME,
951 "HP Pavilion dv5 Notebook PC"),
952 },
953 .driver_data = "20090506",
954 },
955 {
956 .ident = "dv6",
957 .matches = {
958 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
959 DMI_MATCH(DMI_PRODUCT_NAME,
960 "HP Pavilion dv6 Notebook PC"),
961 },
962 .driver_data = "20090423",
963 },
964 {
965 .ident = "HDX18",
966 .matches = {
967 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
968 DMI_MATCH(DMI_PRODUCT_NAME,
969 "HP HDX18 Notebook PC"),
970 },
971 .driver_data = "20090430",
972 },
973
974
975
976
977
978
979
980
981
982 {
983 .ident = "G725",
984 .matches = {
985 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
986 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
987 },
988 .driver_data = "20091216",
989 },
990 { }
991 };
992 const struct dmi_system_id *dmi = dmi_first_match(sysids);
993 int year, month, date;
994 char buf[9];
995
996 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
997 return false;
998
999 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1000 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1001
1002 return strcmp(buf, dmi->driver_data) < 0;
1003}
1004
1005static bool ahci_broken_online(struct pci_dev *pdev)
1006{
1007#define ENCODE_BUSDEVFN(bus, slot, func) \
1008 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1009 static const struct dmi_system_id sysids[] = {
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023 {
1024 .ident = "EP45-DQ6",
1025 .matches = {
1026 DMI_MATCH(DMI_BOARD_VENDOR,
1027 "Gigabyte Technology Co., Ltd."),
1028 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1029 },
1030 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1031 },
1032 {
1033 .ident = "EP45-DS5",
1034 .matches = {
1035 DMI_MATCH(DMI_BOARD_VENDOR,
1036 "Gigabyte Technology Co., Ltd."),
1037 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1038 },
1039 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1040 },
1041 { }
1042 };
1043#undef ENCODE_BUSDEVFN
1044 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1045 unsigned int val;
1046
1047 if (!dmi)
1048 return false;
1049
1050 val = (unsigned long)dmi->driver_data;
1051
1052 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1053}
1054
1055#ifdef CONFIG_ATA_ACPI
1056static void ahci_gtf_filter_workaround(struct ata_host *host)
1057{
1058 static const struct dmi_system_id sysids[] = {
1059
1060
1061
1062
1063
1064
1065
1066
1067 {
1068 .ident = "Aspire 3810T",
1069 .matches = {
1070 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1071 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1072 },
1073 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1074 },
1075 { }
1076 };
1077 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1078 unsigned int filter;
1079 int i;
1080
1081 if (!dmi)
1082 return;
1083
1084 filter = (unsigned long)dmi->driver_data;
1085 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1086 filter, dmi->ident);
1087
1088 for (i = 0; i < host->n_ports; i++) {
1089 struct ata_port *ap = host->ports[i];
1090 struct ata_link *link;
1091 struct ata_device *dev;
1092
1093 ata_for_each_link(link, ap, EDGE)
1094 ata_for_each_dev(dev, link, ALL)
1095 dev->gtf_filter |= filter;
1096 }
1097}
1098#else
1099static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1100{}
1101#endif
1102
1103int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1104{
1105 int rc;
1106 unsigned int maxvec;
1107
1108 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1109 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1110 if (rc > 0) {
1111 if ((rc == maxvec) || (rc == 1))
1112 return rc;
1113
1114
1115
1116
1117 pci_disable_msi(pdev);
1118 if (!pci_enable_msi(pdev))
1119 return 1;
1120 }
1121 }
1122
1123 pci_intx(pdev, 1);
1124 return 0;
1125}
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1146{
1147 int i, rc;
1148
1149
1150 if (n_msis < host->n_ports)
1151 return -EINVAL;
1152
1153 rc = ata_host_start(host);
1154 if (rc)
1155 return rc;
1156
1157 for (i = 0; i < host->n_ports; i++) {
1158 const char* desc;
1159 struct ahci_port_priv *pp = host->ports[i]->private_data;
1160
1161
1162 if (pp)
1163 desc = pp->irq_desc;
1164 else
1165 desc = dev_driver_string(host->dev);
1166
1167 rc = devm_request_threaded_irq(host->dev,
1168 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1169 desc, host->ports[i]);
1170 if (rc)
1171 goto out_free_irqs;
1172 }
1173
1174 for (i = 0; i < host->n_ports; i++)
1175 ata_port_desc(host->ports[i], "irq %d", irq + i);
1176
1177 rc = ata_host_register(host, &ahci_sht);
1178 if (rc)
1179 goto out_free_all_irqs;
1180
1181 return 0;
1182
1183out_free_all_irqs:
1184 i = host->n_ports;
1185out_free_irqs:
1186 for (i--; i >= 0; i--)
1187 devm_free_irq(host->dev, irq + i, host->ports[i]);
1188
1189 return rc;
1190}
1191
1192static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1193{
1194 unsigned int board_id = ent->driver_data;
1195 struct ata_port_info pi = ahci_port_info[board_id];
1196 const struct ata_port_info *ppi[] = { &pi, NULL };
1197 struct device *dev = &pdev->dev;
1198 struct ahci_host_priv *hpriv;
1199 struct ata_host *host;
1200 int n_ports, n_msis, i, rc;
1201 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1202
1203 VPRINTK("ENTER\n");
1204
1205 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1206
1207 ata_print_version_once(&pdev->dev, DRV_VERSION);
1208
1209
1210
1211
1212 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1213 return -ENODEV;
1214
1215
1216
1217
1218
1219 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1220 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1221 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1222 pdev->subsystem_device == 0xcb89)
1223 return -ENODEV;
1224
1225
1226
1227
1228
1229 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1230 dev_info(&pdev->dev,
1231 "PDC42819 can only drive SATA devices with this driver\n");
1232
1233
1234 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1235 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1236 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1237 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1238
1239
1240 rc = pcim_enable_device(pdev);
1241 if (rc)
1242 return rc;
1243
1244 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1245 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1246 u8 map;
1247
1248
1249
1250
1251
1252 pci_read_config_byte(pdev, ICH_MAP, &map);
1253 if (map & 0x3) {
1254 dev_info(&pdev->dev,
1255 "controller is in combined mode, can't enable AHCI mode\n");
1256 return -ENODEV;
1257 }
1258 }
1259
1260
1261
1262
1263 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1264 if (rc == -EBUSY)
1265 pcim_pin_device(pdev);
1266 if (rc)
1267 return rc;
1268
1269 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1270 if (!hpriv)
1271 return -ENOMEM;
1272 hpriv->flags |= (unsigned long)pi.private_data;
1273
1274
1275 if (board_id == board_ahci_mcp65 &&
1276 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1277 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1278
1279
1280 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1281 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1282
1283
1284 if (ahci_sb600_enable_64bit(pdev))
1285 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1286
1287 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1288
1289 n_msis = ahci_init_interrupts(pdev, hpriv);
1290 if (n_msis > 1)
1291 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1292
1293
1294 ahci_pci_save_initial_config(pdev, hpriv);
1295
1296
1297 if (hpriv->cap & HOST_CAP_NCQ) {
1298 pi.flags |= ATA_FLAG_NCQ;
1299
1300
1301
1302
1303
1304
1305 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1306 pi.flags |= ATA_FLAG_FPDMA_AA;
1307
1308
1309
1310
1311
1312
1313
1314 pi.flags |= ATA_FLAG_FPDMA_AUX;
1315 }
1316
1317 if (hpriv->cap & HOST_CAP_PMP)
1318 pi.flags |= ATA_FLAG_PMP;
1319
1320 ahci_set_em_messages(hpriv, &pi);
1321
1322 if (ahci_broken_system_poweroff(pdev)) {
1323 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1324 dev_info(&pdev->dev,
1325 "quirky BIOS, skipping spindown on poweroff\n");
1326 }
1327
1328 if (ahci_broken_suspend(pdev)) {
1329 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1330 dev_warn(&pdev->dev,
1331 "BIOS update required for suspend/resume\n");
1332 }
1333
1334 if (ahci_broken_online(pdev)) {
1335 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1336 dev_info(&pdev->dev,
1337 "online status unreliable, applying workaround\n");
1338 }
1339
1340
1341
1342
1343
1344
1345 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1346
1347 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1348 if (!host)
1349 return -ENOMEM;
1350 host->private_data = hpriv;
1351
1352 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1353 host->flags |= ATA_HOST_PARALLEL_SCAN;
1354 else
1355 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1356
1357 if (pi.flags & ATA_FLAG_EM)
1358 ahci_reset_em(host);
1359
1360 for (i = 0; i < host->n_ports; i++) {
1361 struct ata_port *ap = host->ports[i];
1362
1363 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1364 ata_port_pbar_desc(ap, ahci_pci_bar,
1365 0x100 + ap->port_no * 0x80, "port");
1366
1367
1368 if (ap->flags & ATA_FLAG_EM)
1369 ap->em_message_type = hpriv->em_msg_type;
1370
1371
1372
1373 if (!(hpriv->port_map & (1 << i)))
1374 ap->ops = &ata_dummy_port_ops;
1375 }
1376
1377
1378 ahci_p5wdh_workaround(host);
1379
1380
1381 ahci_gtf_filter_workaround(host);
1382
1383
1384 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1385 if (rc)
1386 return rc;
1387
1388 rc = ahci_pci_reset_controller(host);
1389 if (rc)
1390 return rc;
1391
1392 ahci_pci_init_controller(host);
1393 ahci_pci_print_info(host);
1394
1395 pci_set_master(pdev);
1396
1397 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1398 return ahci_host_activate(host, pdev->irq, n_msis);
1399
1400 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1401 &ahci_sht);
1402}
1403
1404module_pci_driver(ahci_pci_driver);
1405
1406MODULE_AUTHOR("Jeff Garzik");
1407MODULE_DESCRIPTION("AHCI SATA low-level driver");
1408MODULE_LICENSE("GPL");
1409MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1410MODULE_VERSION(DRV_VERSION);
1411