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30#include <linux/device.h>
31#include <drm/drmP.h>
32#include <drm/i915_drm.h>
33#include "i915_drv.h"
34#include "i915_trace.h"
35#include "intel_drv.h"
36
37#include <linux/console.h>
38#include <linux/module.h>
39#include <drm/drm_crtc_helper.h>
40
41static int i915_modeset __read_mostly = -1;
42module_param_named(modeset, i915_modeset, int, 0400);
43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47unsigned int i915_fbpercrtc __always_unused = 0;
48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50int i915_panel_ignore_lid __read_mostly = 1;
51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
55
56unsigned int i915_powersave __read_mostly = 1;
57module_param_named(powersave, i915_powersave, int, 0600);
58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61int i915_semaphores __read_mostly = -1;
62module_param_named(semaphores, i915_semaphores, int, 0600);
63MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66int i915_enable_rc6 __read_mostly = -1;
67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75int i915_enable_fbc __read_mostly = -1;
76module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81unsigned int i915_lvds_downclock __read_mostly = 0;
82module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93int i915_panel_use_ssc __read_mostly = -1;
94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99int i915_vbt_sdvo_panel_type __read_mostly = -1;
100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105static bool i915_try_reset __read_mostly = true;
106module_param_named(reset, i915_try_reset, bool, 0600);
107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109bool i915_enable_hangcheck __read_mostly = true;
110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121int i915_enable_psr __read_mostly = 0;
122module_param_named(enable_psr, i915_enable_psr, int, 0600);
123MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
124
125unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
126module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
127MODULE_PARM_DESC(preliminary_hw_support,
128 "Enable preliminary hardware support.");
129
130int i915_disable_power_well __read_mostly = 1;
131module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
132MODULE_PARM_DESC(disable_power_well,
133 "Disable the power well when possible (default: true)");
134
135int i915_enable_ips __read_mostly = 1;
136module_param_named(enable_ips, i915_enable_ips, int, 0600);
137MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
138
139bool i915_fastboot __read_mostly = 0;
140module_param_named(fastboot, i915_fastboot, bool, 0600);
141MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
142 "(default: false)");
143
144int i915_enable_pc8 __read_mostly = 1;
145module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
146MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
147
148int i915_pc8_timeout __read_mostly = 5000;
149module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
150MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
151
152bool i915_prefault_disable __read_mostly;
153module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
154MODULE_PARM_DESC(prefault_disable,
155 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
156
157static struct drm_driver driver;
158extern int intel_agp_enabled;
159
160static const struct intel_device_info intel_i830_info = {
161 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
162 .has_overlay = 1, .overlay_needs_physical = 1,
163 .ring_mask = RENDER_RING,
164};
165
166static const struct intel_device_info intel_845g_info = {
167 .gen = 2, .num_pipes = 1,
168 .has_overlay = 1, .overlay_needs_physical = 1,
169 .ring_mask = RENDER_RING,
170};
171
172static const struct intel_device_info intel_i85x_info = {
173 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
174 .cursor_needs_physical = 1,
175 .has_overlay = 1, .overlay_needs_physical = 1,
176 .ring_mask = RENDER_RING,
177};
178
179static const struct intel_device_info intel_i865g_info = {
180 .gen = 2, .num_pipes = 1,
181 .has_overlay = 1, .overlay_needs_physical = 1,
182 .ring_mask = RENDER_RING,
183};
184
185static const struct intel_device_info intel_i915g_info = {
186 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
187 .has_overlay = 1, .overlay_needs_physical = 1,
188 .ring_mask = RENDER_RING,
189};
190static const struct intel_device_info intel_i915gm_info = {
191 .gen = 3, .is_mobile = 1, .num_pipes = 2,
192 .cursor_needs_physical = 1,
193 .has_overlay = 1, .overlay_needs_physical = 1,
194 .supports_tv = 1,
195 .ring_mask = RENDER_RING,
196};
197static const struct intel_device_info intel_i945g_info = {
198 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
199 .has_overlay = 1, .overlay_needs_physical = 1,
200 .ring_mask = RENDER_RING,
201};
202static const struct intel_device_info intel_i945gm_info = {
203 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
204 .has_hotplug = 1, .cursor_needs_physical = 1,
205 .has_overlay = 1, .overlay_needs_physical = 1,
206 .supports_tv = 1,
207 .ring_mask = RENDER_RING,
208};
209
210static const struct intel_device_info intel_i965g_info = {
211 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
212 .has_hotplug = 1,
213 .has_overlay = 1,
214 .ring_mask = RENDER_RING,
215};
216
217static const struct intel_device_info intel_i965gm_info = {
218 .gen = 4, .is_crestline = 1, .num_pipes = 2,
219 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
220 .has_overlay = 1,
221 .supports_tv = 1,
222 .ring_mask = RENDER_RING,
223};
224
225static const struct intel_device_info intel_g33_info = {
226 .gen = 3, .is_g33 = 1, .num_pipes = 2,
227 .need_gfx_hws = 1, .has_hotplug = 1,
228 .has_overlay = 1,
229 .ring_mask = RENDER_RING,
230};
231
232static const struct intel_device_info intel_g45_info = {
233 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
234 .has_pipe_cxsr = 1, .has_hotplug = 1,
235 .ring_mask = RENDER_RING | BSD_RING,
236};
237
238static const struct intel_device_info intel_gm45_info = {
239 .gen = 4, .is_g4x = 1, .num_pipes = 2,
240 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
241 .has_pipe_cxsr = 1, .has_hotplug = 1,
242 .supports_tv = 1,
243 .ring_mask = RENDER_RING | BSD_RING,
244};
245
246static const struct intel_device_info intel_pineview_info = {
247 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
248 .need_gfx_hws = 1, .has_hotplug = 1,
249 .has_overlay = 1,
250};
251
252static const struct intel_device_info intel_ironlake_d_info = {
253 .gen = 5, .num_pipes = 2,
254 .need_gfx_hws = 1, .has_hotplug = 1,
255 .ring_mask = RENDER_RING | BSD_RING,
256};
257
258static const struct intel_device_info intel_ironlake_m_info = {
259 .gen = 5, .is_mobile = 1, .num_pipes = 2,
260 .need_gfx_hws = 1, .has_hotplug = 1,
261 .has_fbc = 1,
262 .ring_mask = RENDER_RING | BSD_RING,
263};
264
265static const struct intel_device_info intel_sandybridge_d_info = {
266 .gen = 6, .num_pipes = 2,
267 .need_gfx_hws = 1, .has_hotplug = 1,
268 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
269 .has_llc = 1,
270};
271
272static const struct intel_device_info intel_sandybridge_m_info = {
273 .gen = 6, .is_mobile = 1, .num_pipes = 2,
274 .need_gfx_hws = 1, .has_hotplug = 1,
275 .has_fbc = 1,
276 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
277 .has_llc = 1,
278};
279
280#define GEN7_FEATURES \
281 .gen = 7, .num_pipes = 3, \
282 .need_gfx_hws = 1, .has_hotplug = 1, \
283 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
284 .has_llc = 1
285
286static const struct intel_device_info intel_ivybridge_d_info = {
287 GEN7_FEATURES,
288 .is_ivybridge = 1,
289};
290
291static const struct intel_device_info intel_ivybridge_m_info = {
292 GEN7_FEATURES,
293 .is_ivybridge = 1,
294 .is_mobile = 1,
295 .has_fbc = 1,
296};
297
298static const struct intel_device_info intel_ivybridge_q_info = {
299 GEN7_FEATURES,
300 .is_ivybridge = 1,
301 .num_pipes = 0,
302};
303
304static const struct intel_device_info intel_valleyview_m_info = {
305 GEN7_FEATURES,
306 .is_mobile = 1,
307 .num_pipes = 2,
308 .is_valleyview = 1,
309 .display_mmio_offset = VLV_DISPLAY_BASE,
310 .has_llc = 0,
311};
312
313static const struct intel_device_info intel_valleyview_d_info = {
314 GEN7_FEATURES,
315 .num_pipes = 2,
316 .is_valleyview = 1,
317 .display_mmio_offset = VLV_DISPLAY_BASE,
318 .has_llc = 0,
319};
320
321static const struct intel_device_info intel_haswell_d_info = {
322 GEN7_FEATURES,
323 .is_haswell = 1,
324 .has_ddi = 1,
325 .has_fpga_dbg = 1,
326 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
327};
328
329static const struct intel_device_info intel_haswell_m_info = {
330 GEN7_FEATURES,
331 .is_haswell = 1,
332 .is_mobile = 1,
333 .has_ddi = 1,
334 .has_fpga_dbg = 1,
335 .has_fbc = 1,
336 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
337};
338
339static const struct intel_device_info intel_broadwell_d_info = {
340 .is_preliminary = 1,
341 .gen = 8, .num_pipes = 3,
342 .need_gfx_hws = 1, .has_hotplug = 1,
343 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
344 .has_llc = 1,
345 .has_ddi = 1,
346};
347
348static const struct intel_device_info intel_broadwell_m_info = {
349 .is_preliminary = 1,
350 .gen = 8, .is_mobile = 1, .num_pipes = 3,
351 .need_gfx_hws = 1, .has_hotplug = 1,
352 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
353 .has_llc = 1,
354 .has_ddi = 1,
355};
356
357
358
359
360
361
362
363#define INTEL_PCI_IDS \
364 INTEL_I830_IDS(&intel_i830_info), \
365 INTEL_I845G_IDS(&intel_845g_info), \
366 INTEL_I85X_IDS(&intel_i85x_info), \
367 INTEL_I865G_IDS(&intel_i865g_info), \
368 INTEL_I915G_IDS(&intel_i915g_info), \
369 INTEL_I915GM_IDS(&intel_i915gm_info), \
370 INTEL_I945G_IDS(&intel_i945g_info), \
371 INTEL_I945GM_IDS(&intel_i945gm_info), \
372 INTEL_I965G_IDS(&intel_i965g_info), \
373 INTEL_G33_IDS(&intel_g33_info), \
374 INTEL_I965GM_IDS(&intel_i965gm_info), \
375 INTEL_GM45_IDS(&intel_gm45_info), \
376 INTEL_G45_IDS(&intel_g45_info), \
377 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
378 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
379 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
380 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
381 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
382 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), \
383 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
384 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
385 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
386 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
387 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
388 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
389 INTEL_BDW_M_IDS(&intel_broadwell_m_info), \
390 INTEL_BDW_D_IDS(&intel_broadwell_d_info)
391
392static const struct pci_device_id pciidlist[] = {
393 INTEL_PCI_IDS,
394 {0, 0, 0}
395};
396
397#if defined(CONFIG_DRM_I915_KMS)
398MODULE_DEVICE_TABLE(pci, pciidlist);
399#endif
400
401void intel_detect_pch(struct drm_device *dev)
402{
403 struct drm_i915_private *dev_priv = dev->dev_private;
404 struct pci_dev *pch;
405
406
407
408
409 if (INTEL_INFO(dev)->num_pipes == 0) {
410 dev_priv->pch_type = PCH_NOP;
411 return;
412 }
413
414
415
416
417
418
419
420
421
422
423
424
425 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
426 while (pch) {
427 struct pci_dev *curr = pch;
428 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
429 unsigned short id;
430 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
431 dev_priv->pch_id = id;
432
433 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
434 dev_priv->pch_type = PCH_IBX;
435 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
436 WARN_ON(!IS_GEN5(dev));
437 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
438 dev_priv->pch_type = PCH_CPT;
439 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
440 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
441 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
442
443 dev_priv->pch_type = PCH_CPT;
444 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
445 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
446 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
447 dev_priv->pch_type = PCH_LPT;
448 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
449 WARN_ON(!IS_HASWELL(dev));
450 WARN_ON(IS_ULT(dev));
451 } else if (IS_BROADWELL(dev)) {
452 dev_priv->pch_type = PCH_LPT;
453 dev_priv->pch_id =
454 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
455 DRM_DEBUG_KMS("This is Broadwell, assuming "
456 "LynxPoint LP PCH\n");
457 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
458 dev_priv->pch_type = PCH_LPT;
459 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
460 WARN_ON(!IS_HASWELL(dev));
461 WARN_ON(!IS_ULT(dev));
462 } else {
463 goto check_next;
464 }
465 pci_dev_put(pch);
466 break;
467 }
468check_next:
469 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
470 pci_dev_put(curr);
471 }
472 if (!pch)
473 DRM_DEBUG_KMS("No PCH found?\n");
474}
475
476bool i915_semaphore_is_enabled(struct drm_device *dev)
477{
478 if (INTEL_INFO(dev)->gen < 6)
479 return 0;
480
481
482 if (IS_GEN8(dev)) {
483 WARN_ON(!i915_preliminary_hw_support);
484 return 0;
485 }
486
487 if (i915_semaphores >= 0)
488 return i915_semaphores;
489
490#ifdef CONFIG_INTEL_IOMMU
491
492 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
493 return false;
494#endif
495
496 return 1;
497}
498
499static int i915_drm_freeze(struct drm_device *dev)
500{
501 struct drm_i915_private *dev_priv = dev->dev_private;
502 struct drm_crtc *crtc;
503
504
505 mutex_lock(&dev_priv->modeset_restore_lock);
506 dev_priv->modeset_restore = MODESET_SUSPENDED;
507 mutex_unlock(&dev_priv->modeset_restore_lock);
508
509
510
511 hsw_disable_package_c8(dev_priv);
512 intel_display_set_init_power(dev, true);
513
514 drm_kms_helper_poll_disable(dev);
515
516 pci_save_state(dev->pdev);
517
518
519 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
520 int error;
521
522 error = i915_gem_suspend(dev);
523 if (error) {
524 dev_err(&dev->pdev->dev,
525 "GEM idle failed, resume might fail\n");
526 return error;
527 }
528
529 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
530
531 drm_irq_uninstall(dev);
532 dev_priv->enable_hotplug_processing = false;
533
534
535
536
537 mutex_lock(&dev->mode_config.mutex);
538 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
539 dev_priv->display.crtc_disable(crtc);
540 mutex_unlock(&dev->mode_config.mutex);
541
542 intel_modeset_suspend_hw(dev);
543 }
544
545 i915_gem_suspend_gtt_mappings(dev);
546
547 i915_save_state(dev);
548
549 intel_opregion_fini(dev);
550
551 console_lock();
552 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
553 console_unlock();
554
555 return 0;
556}
557
558int i915_suspend(struct drm_device *dev, pm_message_t state)
559{
560 int error;
561
562 if (!dev || !dev->dev_private) {
563 DRM_ERROR("dev: %p\n", dev);
564 DRM_ERROR("DRM not initialized, aborting suspend.\n");
565 return -ENODEV;
566 }
567
568 if (state.event == PM_EVENT_PRETHAW)
569 return 0;
570
571
572 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
573 return 0;
574
575 error = i915_drm_freeze(dev);
576 if (error)
577 return error;
578
579 if (state.event == PM_EVENT_SUSPEND) {
580
581 pci_disable_device(dev->pdev);
582 pci_set_power_state(dev->pdev, PCI_D3hot);
583 }
584
585 return 0;
586}
587
588void intel_console_resume(struct work_struct *work)
589{
590 struct drm_i915_private *dev_priv =
591 container_of(work, struct drm_i915_private,
592 console_resume_work);
593 struct drm_device *dev = dev_priv->dev;
594
595 console_lock();
596 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
597 console_unlock();
598}
599
600static void intel_resume_hotplug(struct drm_device *dev)
601{
602 struct drm_mode_config *mode_config = &dev->mode_config;
603 struct intel_encoder *encoder;
604
605 mutex_lock(&mode_config->mutex);
606 DRM_DEBUG_KMS("running encoder hotplug functions\n");
607
608 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
609 if (encoder->hot_plug)
610 encoder->hot_plug(encoder);
611
612 mutex_unlock(&mode_config->mutex);
613
614
615 drm_helper_hpd_irq_event(dev);
616}
617
618static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
619{
620 struct drm_i915_private *dev_priv = dev->dev_private;
621 int error = 0;
622
623 intel_uncore_early_sanitize(dev);
624
625 intel_uncore_sanitize(dev);
626
627 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
628 restore_gtt_mappings) {
629 mutex_lock(&dev->struct_mutex);
630 i915_gem_restore_gtt_mappings(dev);
631 mutex_unlock(&dev->struct_mutex);
632 }
633
634 intel_power_domains_init_hw(dev);
635
636 i915_restore_state(dev);
637 intel_opregion_setup(dev);
638
639
640 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
641 intel_init_pch_refclk(dev);
642
643 mutex_lock(&dev->struct_mutex);
644
645 error = i915_gem_init_hw(dev);
646 mutex_unlock(&dev->struct_mutex);
647
648
649 drm_irq_install(dev);
650
651 intel_modeset_init_hw(dev);
652
653 drm_modeset_lock_all(dev);
654 drm_mode_config_reset(dev);
655 intel_modeset_setup_hw_state(dev, true);
656 drm_modeset_unlock_all(dev);
657
658
659
660
661
662
663
664 intel_hpd_init(dev);
665 dev_priv->enable_hotplug_processing = true;
666
667 intel_resume_hotplug(dev);
668 }
669
670 intel_opregion_init(dev);
671
672
673
674
675
676
677 if (console_trylock()) {
678 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
679 console_unlock();
680 } else {
681 schedule_work(&dev_priv->console_resume_work);
682 }
683
684
685
686 hsw_enable_package_c8(dev_priv);
687
688 mutex_lock(&dev_priv->modeset_restore_lock);
689 dev_priv->modeset_restore = MODESET_DONE;
690 mutex_unlock(&dev_priv->modeset_restore_lock);
691 return error;
692}
693
694static int i915_drm_thaw(struct drm_device *dev)
695{
696 if (drm_core_check_feature(dev, DRIVER_MODESET))
697 i915_check_and_clear_faults(dev);
698
699 return __i915_drm_thaw(dev, true);
700}
701
702int i915_resume(struct drm_device *dev)
703{
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int ret;
706
707 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
708 return 0;
709
710 if (pci_enable_device(dev->pdev))
711 return -EIO;
712
713 pci_set_master(dev->pdev);
714
715
716
717
718
719
720 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
721 if (ret)
722 return ret;
723
724 drm_kms_helper_poll_enable(dev);
725 return 0;
726}
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743int i915_reset(struct drm_device *dev)
744{
745 drm_i915_private_t *dev_priv = dev->dev_private;
746 bool simulated;
747 int ret;
748
749 if (!i915_try_reset)
750 return 0;
751
752 mutex_lock(&dev->struct_mutex);
753
754 i915_gem_reset(dev);
755
756 simulated = dev_priv->gpu_error.stop_rings != 0;
757
758 ret = intel_gpu_reset(dev);
759
760
761 if (simulated) {
762 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
763 dev_priv->gpu_error.stop_rings = 0;
764 if (ret == -ENODEV) {
765 DRM_ERROR("Reset not implemented, but ignoring "
766 "error for simulated gpu hangs\n");
767 ret = 0;
768 }
769 }
770
771 if (ret) {
772 DRM_ERROR("Failed to reset chip.\n");
773 mutex_unlock(&dev->struct_mutex);
774 return ret;
775 }
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
792 !dev_priv->ums.mm_suspended) {
793 bool hw_contexts_disabled = dev_priv->hw_contexts_disabled;
794 dev_priv->ums.mm_suspended = 0;
795
796 ret = i915_gem_init_hw(dev);
797 if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled)
798 DRM_ERROR("HW contexts didn't survive reset\n");
799 mutex_unlock(&dev->struct_mutex);
800 if (ret) {
801 DRM_ERROR("Failed hw init on reset %d\n", ret);
802 return ret;
803 }
804
805 drm_irq_uninstall(dev);
806 drm_irq_install(dev);
807 intel_hpd_init(dev);
808 } else {
809 mutex_unlock(&dev->struct_mutex);
810 }
811
812 return 0;
813}
814
815static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
816{
817 struct intel_device_info *intel_info =
818 (struct intel_device_info *) ent->driver_data;
819
820 if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
821 DRM_INFO("This hardware requires preliminary hardware support.\n"
822 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
823 return -ENODEV;
824 }
825
826
827
828
829
830
831 if (PCI_FUNC(pdev->devfn))
832 return -ENODEV;
833
834
835
836
837
838 if (intel_info->gen != 3) {
839 driver.driver_features &=
840 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
841 } else if (!intel_agp_enabled) {
842 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
843 return -ENODEV;
844 }
845
846 return drm_get_pci_dev(pdev, ent, &driver);
847}
848
849static void
850i915_pci_remove(struct pci_dev *pdev)
851{
852 struct drm_device *dev = pci_get_drvdata(pdev);
853
854 drm_put_dev(dev);
855}
856
857static int i915_pm_suspend(struct device *dev)
858{
859 struct pci_dev *pdev = to_pci_dev(dev);
860 struct drm_device *drm_dev = pci_get_drvdata(pdev);
861 int error;
862
863 if (!drm_dev || !drm_dev->dev_private) {
864 dev_err(dev, "DRM not initialized, aborting suspend.\n");
865 return -ENODEV;
866 }
867
868 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
869 return 0;
870
871 error = i915_drm_freeze(drm_dev);
872 if (error)
873 return error;
874
875 pci_disable_device(pdev);
876 pci_set_power_state(pdev, PCI_D3hot);
877
878 return 0;
879}
880
881static int i915_pm_resume(struct device *dev)
882{
883 struct pci_dev *pdev = to_pci_dev(dev);
884 struct drm_device *drm_dev = pci_get_drvdata(pdev);
885
886 return i915_resume(drm_dev);
887}
888
889static int i915_pm_freeze(struct device *dev)
890{
891 struct pci_dev *pdev = to_pci_dev(dev);
892 struct drm_device *drm_dev = pci_get_drvdata(pdev);
893
894 if (!drm_dev || !drm_dev->dev_private) {
895 dev_err(dev, "DRM not initialized, aborting suspend.\n");
896 return -ENODEV;
897 }
898
899 return i915_drm_freeze(drm_dev);
900}
901
902static int i915_pm_thaw(struct device *dev)
903{
904 struct pci_dev *pdev = to_pci_dev(dev);
905 struct drm_device *drm_dev = pci_get_drvdata(pdev);
906
907 return i915_drm_thaw(drm_dev);
908}
909
910static int i915_pm_poweroff(struct device *dev)
911{
912 struct pci_dev *pdev = to_pci_dev(dev);
913 struct drm_device *drm_dev = pci_get_drvdata(pdev);
914
915 return i915_drm_freeze(drm_dev);
916}
917
918static const struct dev_pm_ops i915_pm_ops = {
919 .suspend = i915_pm_suspend,
920 .resume = i915_pm_resume,
921 .freeze = i915_pm_freeze,
922 .thaw = i915_pm_thaw,
923 .poweroff = i915_pm_poweroff,
924 .restore = i915_pm_resume,
925};
926
927static const struct vm_operations_struct i915_gem_vm_ops = {
928 .fault = i915_gem_fault,
929 .open = drm_gem_vm_open,
930 .close = drm_gem_vm_close,
931};
932
933static const struct file_operations i915_driver_fops = {
934 .owner = THIS_MODULE,
935 .open = drm_open,
936 .release = drm_release,
937 .unlocked_ioctl = drm_ioctl,
938 .mmap = drm_gem_mmap,
939 .poll = drm_poll,
940 .read = drm_read,
941#ifdef CONFIG_COMPAT
942 .compat_ioctl = i915_compat_ioctl,
943#endif
944 .llseek = noop_llseek,
945};
946
947static struct drm_driver driver = {
948
949
950
951 .driver_features =
952 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
953 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
954 DRIVER_RENDER,
955 .load = i915_driver_load,
956 .unload = i915_driver_unload,
957 .open = i915_driver_open,
958 .lastclose = i915_driver_lastclose,
959 .preclose = i915_driver_preclose,
960 .postclose = i915_driver_postclose,
961
962
963 .suspend = i915_suspend,
964 .resume = i915_resume,
965
966 .device_is_agp = i915_driver_device_is_agp,
967 .master_create = i915_master_create,
968 .master_destroy = i915_master_destroy,
969#if defined(CONFIG_DEBUG_FS)
970 .debugfs_init = i915_debugfs_init,
971 .debugfs_cleanup = i915_debugfs_cleanup,
972#endif
973 .gem_free_object = i915_gem_free_object,
974 .gem_vm_ops = &i915_gem_vm_ops,
975
976 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
977 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
978 .gem_prime_export = i915_gem_prime_export,
979 .gem_prime_import = i915_gem_prime_import,
980
981 .dumb_create = i915_gem_dumb_create,
982 .dumb_map_offset = i915_gem_mmap_gtt,
983 .dumb_destroy = drm_gem_dumb_destroy,
984 .ioctls = i915_ioctls,
985 .fops = &i915_driver_fops,
986 .name = DRIVER_NAME,
987 .desc = DRIVER_DESC,
988 .date = DRIVER_DATE,
989 .major = DRIVER_MAJOR,
990 .minor = DRIVER_MINOR,
991 .patchlevel = DRIVER_PATCHLEVEL,
992};
993
994static struct pci_driver i915_pci_driver = {
995 .name = DRIVER_NAME,
996 .id_table = pciidlist,
997 .probe = i915_pci_probe,
998 .remove = i915_pci_remove,
999 .driver.pm = &i915_pm_ops,
1000};
1001
1002static int __init i915_init(void)
1003{
1004 driver.num_ioctls = i915_max_ioctl;
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015#if defined(CONFIG_DRM_I915_KMS)
1016 if (i915_modeset != 0)
1017 driver.driver_features |= DRIVER_MODESET;
1018#endif
1019 if (i915_modeset == 1)
1020 driver.driver_features |= DRIVER_MODESET;
1021
1022#ifdef CONFIG_VGA_CONSOLE
1023 if (vgacon_text_force() && i915_modeset == -1)
1024 driver.driver_features &= ~DRIVER_MODESET;
1025#endif
1026
1027 if (!(driver.driver_features & DRIVER_MODESET))
1028 driver.get_vblank_timestamp = NULL;
1029
1030 return drm_pci_init(&driver, &i915_pci_driver);
1031}
1032
1033static void __exit i915_exit(void)
1034{
1035 drm_pci_exit(&driver, &i915_pci_driver);
1036}
1037
1038module_init(i915_init);
1039module_exit(i915_exit);
1040
1041MODULE_AUTHOR(DRIVER_AUTHOR);
1042MODULE_DESCRIPTION(DRIVER_DESC);
1043MODULE_LICENSE("GPL and additional rights");
1044