1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
7#include <subdev/bios/conn.h>
8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
10#include <subdev/bios/gpio.h>
11#include <subdev/bios/init.h>
12#include <subdev/devinit.h>
13#include <subdev/i2c.h>
14#include <subdev/vga.h>
15#include <subdev/gpio.h>
16
17#define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
20} while(0)
21#define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
24} while(0)
25#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
28
29
30
31
32
33static inline bool
34init_exec(struct nvbios_init *init)
35{
36 return (init->execute == 1) || ((init->execute & 5) == 5);
37}
38
39static inline void
40init_exec_set(struct nvbios_init *init, bool exec)
41{
42 if (exec) init->execute &= 0xfd;
43 else init->execute |= 0x02;
44}
45
46static inline void
47init_exec_inv(struct nvbios_init *init)
48{
49 init->execute ^= 0x02;
50}
51
52static inline void
53init_exec_force(struct nvbios_init *init, bool exec)
54{
55 if (exec) init->execute |= 0x04;
56 else init->execute &= 0xfb;
57}
58
59
60
61
62
63static inline int
64init_or(struct nvbios_init *init)
65{
66 if (init_exec(init)) {
67 if (init->outp)
68 return ffs(init->outp->or) - 1;
69 error("script needs OR!!\n");
70 }
71 return 0;
72}
73
74static inline int
75init_link(struct nvbios_init *init)
76{
77 if (init_exec(init)) {
78 if (init->outp)
79 return !(init->outp->sorconf.link & 1);
80 error("script needs OR link\n");
81 }
82 return 0;
83}
84
85static inline int
86init_crtc(struct nvbios_init *init)
87{
88 if (init_exec(init)) {
89 if (init->crtc >= 0)
90 return init->crtc;
91 error("script needs crtc\n");
92 }
93 return 0;
94}
95
96static u8
97init_conn(struct nvbios_init *init)
98{
99 struct nouveau_bios *bios = init->bios;
100 u8 ver, len;
101 u16 conn;
102
103 if (init_exec(init)) {
104 if (init->outp) {
105 conn = init->outp->connector;
106 conn = dcb_conn(bios, conn, &ver, &len);
107 if (conn)
108 return nv_ro08(bios, conn);
109 }
110
111 error("script needs connector type\n");
112 }
113
114 return 0xff;
115}
116
117static inline u32
118init_nvreg(struct nvbios_init *init, u32 reg)
119{
120
121
122
123
124
125
126 reg &= ~0x00000003;
127
128
129
130
131 if (nv_device(init->bios)->card_type >= NV_50) {
132 if (reg & 0x80000000) {
133 reg += init_crtc(init) * 0x800;
134 reg &= ~0x80000000;
135 }
136
137 if (reg & 0x40000000) {
138 reg += init_or(init) * 0x800;
139 reg &= ~0x40000000;
140 if (reg & 0x20000000) {
141 reg += init_link(init) * 0x80;
142 reg &= ~0x20000000;
143 }
144 }
145 }
146
147 if (reg & ~0x00fffffc)
148 warn("unknown bits in register 0x%08x\n", reg);
149 return reg;
150}
151
152static u32
153init_rd32(struct nvbios_init *init, u32 reg)
154{
155 reg = init_nvreg(init, reg);
156 if (init_exec(init))
157 return nv_rd32(init->subdev, reg);
158 return 0x00000000;
159}
160
161static void
162init_wr32(struct nvbios_init *init, u32 reg, u32 val)
163{
164 reg = init_nvreg(init, reg);
165 if (init_exec(init))
166 nv_wr32(init->subdev, reg, val);
167}
168
169static u32
170init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
171{
172 reg = init_nvreg(init, reg);
173 if (init_exec(init)) {
174 u32 tmp = nv_rd32(init->subdev, reg);
175 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
176 return tmp;
177 }
178 return 0x00000000;
179}
180
181static u8
182init_rdport(struct nvbios_init *init, u16 port)
183{
184 if (init_exec(init))
185 return nv_rdport(init->subdev, init->crtc, port);
186 return 0x00;
187}
188
189static void
190init_wrport(struct nvbios_init *init, u16 port, u8 value)
191{
192 if (init_exec(init))
193 nv_wrport(init->subdev, init->crtc, port, value);
194}
195
196static u8
197init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
198{
199 struct nouveau_subdev *subdev = init->subdev;
200 if (init_exec(init)) {
201 int head = init->crtc < 0 ? 0 : init->crtc;
202 return nv_rdvgai(subdev, head, port, index);
203 }
204 return 0x00;
205}
206
207static void
208init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
209{
210
211 if (nv_device(init->subdev)->card_type < NV_50) {
212 if (port == 0x03d4 && index == 0x44)
213 init->crtc = 0;
214 }
215
216 if (init_exec(init)) {
217 int head = init->crtc < 0 ? 0 : init->crtc;
218 nv_wrvgai(init->subdev, head, port, index, value);
219 }
220
221
222 if (nv_device(init->subdev)->card_type < NV_50) {
223 if (port == 0x03d4 && index == 0x44 && value == 3)
224 init->crtc = 1;
225 }
226}
227
228static struct nouveau_i2c_port *
229init_i2c(struct nvbios_init *init, int index)
230{
231 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
232
233 if (index == 0xff) {
234 index = NV_I2C_DEFAULT(0);
235 if (init->outp && init->outp->i2c_upper_default)
236 index = NV_I2C_DEFAULT(1);
237 } else
238 if (index < 0) {
239 if (!init->outp) {
240 if (init_exec(init))
241 error("script needs output for i2c\n");
242 return NULL;
243 }
244
245 if (index == -2 && init->outp->location) {
246 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
247 return i2c->find_type(i2c, index);
248 }
249
250 index = init->outp->i2c_index;
251 }
252
253 return i2c->find(i2c, index);
254}
255
256static int
257init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
258{
259 struct nouveau_i2c_port *port = init_i2c(init, index);
260 if (port && init_exec(init))
261 return nv_rdi2cr(port, addr, reg);
262 return -ENODEV;
263}
264
265static int
266init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
267{
268 struct nouveau_i2c_port *port = init_i2c(init, index);
269 if (port && init_exec(init))
270 return nv_wri2cr(port, addr, reg, val);
271 return -ENODEV;
272}
273
274static int
275init_rdauxr(struct nvbios_init *init, u32 addr)
276{
277 struct nouveau_i2c_port *port = init_i2c(init, -2);
278 u8 data;
279
280 if (port && init_exec(init)) {
281 int ret = nv_rdaux(port, addr, &data, 1);
282 if (ret)
283 return ret;
284 return data;
285 }
286
287 return -ENODEV;
288}
289
290static int
291init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
292{
293 struct nouveau_i2c_port *port = init_i2c(init, -2);
294 if (port && init_exec(init))
295 return nv_wraux(port, addr, &data, 1);
296 return -ENODEV;
297}
298
299static void
300init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
301{
302 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
303 if (devinit->pll_set && init_exec(init)) {
304 int ret = devinit->pll_set(devinit, id, freq);
305 if (ret)
306 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
307 }
308}
309
310
311
312
313
314static u16
315init_table(struct nouveau_bios *bios, u16 *len)
316{
317 struct bit_entry bit_I;
318
319 if (!bit_entry(bios, 'I', &bit_I)) {
320 *len = bit_I.length;
321 return bit_I.offset;
322 }
323
324 if (bmp_version(bios) >= 0x0510) {
325 *len = 14;
326 return bios->bmp_offset + 75;
327 }
328
329 return 0x0000;
330}
331
332static u16
333init_table_(struct nvbios_init *init, u16 offset, const char *name)
334{
335 struct nouveau_bios *bios = init->bios;
336 u16 len, data = init_table(bios, &len);
337 if (data) {
338 if (len >= offset + 2) {
339 data = nv_ro16(bios, data + offset);
340 if (data)
341 return data;
342
343 warn("%s pointer invalid\n", name);
344 return 0x0000;
345 }
346
347 warn("init data too short for %s pointer", name);
348 return 0x0000;
349 }
350
351 warn("init data not found\n");
352 return 0x0000;
353}
354
355#define init_script_table(b) init_table_((b), 0x00, "script table")
356#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
357#define init_macro_table(b) init_table_((b), 0x04, "macro table")
358#define init_condition_table(b) init_table_((b), 0x06, "condition table")
359#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
360#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
361#define init_function_table(b) init_table_((b), 0x0c, "function table")
362#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
363
364static u16
365init_script(struct nouveau_bios *bios, int index)
366{
367 struct nvbios_init init = { .bios = bios };
368 u16 bmp_ver = bmp_version(bios), data;
369
370 if (bmp_ver && bmp_ver < 0x0510) {
371 if (index > 1 || bmp_ver < 0x0100)
372 return 0x0000;
373
374 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
375 return nv_ro16(bios, data + (index * 2));
376 }
377
378 data = init_script_table(&init);
379 if (data)
380 return nv_ro16(bios, data + (index * 2));
381
382 return 0x0000;
383}
384
385static u16
386init_unknown_script(struct nouveau_bios *bios)
387{
388 u16 len, data = init_table(bios, &len);
389 if (data && len >= 16)
390 return nv_ro16(bios, data + 14);
391 return 0x0000;
392}
393
394static u16
395init_ram_restrict_table(struct nvbios_init *init)
396{
397 struct nouveau_bios *bios = init->bios;
398 struct bit_entry bit_M;
399 u16 data = 0x0000;
400
401 if (!bit_entry(bios, 'M', &bit_M)) {
402 if (bit_M.version == 1 && bit_M.length >= 5)
403 data = nv_ro16(bios, bit_M.offset + 3);
404 if (bit_M.version == 2 && bit_M.length >= 3)
405 data = nv_ro16(bios, bit_M.offset + 1);
406 }
407
408 if (data == 0x0000)
409 warn("ram restrict table not found\n");
410 return data;
411}
412
413static u8
414init_ram_restrict_group_count(struct nvbios_init *init)
415{
416 struct nouveau_bios *bios = init->bios;
417 struct bit_entry bit_M;
418
419 if (!bit_entry(bios, 'M', &bit_M)) {
420 if (bit_M.version == 1 && bit_M.length >= 5)
421 return nv_ro08(bios, bit_M.offset + 2);
422 if (bit_M.version == 2 && bit_M.length >= 3)
423 return nv_ro08(bios, bit_M.offset + 0);
424 }
425
426 return 0x00;
427}
428
429static u8
430init_ram_restrict_strap(struct nvbios_init *init)
431{
432
433
434
435
436
437
438
439
440 if (!init->ramcfg || init->bios->version.major < 0x70)
441 init->ramcfg = init_rd32(init, 0x101000);
442 return (init->ramcfg & 0x00000003c) >> 2;
443}
444
445static u8
446init_ram_restrict(struct nvbios_init *init)
447{
448 u8 strap = init_ram_restrict_strap(init);
449 u16 table = init_ram_restrict_table(init);
450 if (table)
451 return nv_ro08(init->bios, table + strap);
452 return 0x00;
453}
454
455static u8
456init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
457{
458 struct nouveau_bios *bios = init->bios;
459 u16 table = init_xlat_table(init);
460 if (table) {
461 u16 data = nv_ro16(bios, table + (index * 2));
462 if (data)
463 return nv_ro08(bios, data + offset);
464 warn("xlat table pointer %d invalid\n", index);
465 }
466 return 0x00;
467}
468
469
470
471
472
473static bool
474init_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_condition_table(init);
478 if (table) {
479 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
480 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
481 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
482 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
483 cond, reg, msk, val);
484 return (init_rd32(init, reg) & msk) == val;
485 }
486 return false;
487}
488
489static bool
490init_io_condition_met(struct nvbios_init *init, u8 cond)
491{
492 struct nouveau_bios *bios = init->bios;
493 u16 table = init_io_condition_table(init);
494 if (table) {
495 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
496 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
497 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
498 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
499 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
500 cond, port, index, mask, value);
501 return (init_rdvgai(init, port, index) & mask) == value;
502 }
503 return false;
504}
505
506static bool
507init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
508{
509 struct nouveau_bios *bios = init->bios;
510 u16 table = init_io_flag_condition_table(init);
511 if (table) {
512 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
513 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
514 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
515 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
516 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
517 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
518 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
519 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
520 return (nv_ro08(bios, data + ioval) & dmask) == value;
521 }
522 return false;
523}
524
525static inline u32
526init_shift(u32 data, u8 shift)
527{
528 if (shift < 0x80)
529 return data >> shift;
530 return data << (0x100 - shift);
531}
532
533static u32
534init_tmds_reg(struct nvbios_init *init, u8 tmds)
535{
536
537
538
539
540
541
542
543
544
545 const int pramdac_offset[13] = {
546 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
547 const u32 pramdac_table[4] = {
548 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
549
550 if (tmds >= 0x80) {
551 if (init->outp) {
552 u32 dacoffset = pramdac_offset[init->outp->or];
553 if (tmds == 0x81)
554 dacoffset ^= 8;
555 return 0x6808b0 + dacoffset;
556 }
557
558 if (init_exec(init))
559 error("tmds opcodes need dcb\n");
560 } else {
561 if (tmds < ARRAY_SIZE(pramdac_table))
562 return pramdac_table[tmds];
563
564 error("tmds selector 0x%02x unknown\n", tmds);
565 }
566
567 return 0;
568}
569
570
571
572
573
574
575
576
577
578static void
579init_reserved(struct nvbios_init *init)
580{
581 u8 opcode = nv_ro08(init->bios, init->offset);
582 u8 length, i;
583
584 switch (opcode) {
585 case 0xaa:
586 length = 4;
587 break;
588 default:
589 length = 1;
590 break;
591 }
592
593 trace("RESERVED 0x%02x\t", opcode);
594 for (i = 1; i < length; i++)
595 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
596 cont("\n");
597 init->offset += length;
598}
599
600
601
602
603
604static void
605init_done(struct nvbios_init *init)
606{
607 trace("DONE\n");
608 init->offset = 0x0000;
609}
610
611
612
613
614
615static void
616init_io_restrict_prog(struct nvbios_init *init)
617{
618 struct nouveau_bios *bios = init->bios;
619 u16 port = nv_ro16(bios, init->offset + 1);
620 u8 index = nv_ro08(bios, init->offset + 3);
621 u8 mask = nv_ro08(bios, init->offset + 4);
622 u8 shift = nv_ro08(bios, init->offset + 5);
623 u8 count = nv_ro08(bios, init->offset + 6);
624 u32 reg = nv_ro32(bios, init->offset + 7);
625 u8 conf, i;
626
627 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
628 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
629 reg, port, index, mask, shift);
630 init->offset += 11;
631
632 conf = (init_rdvgai(init, port, index) & mask) >> shift;
633 for (i = 0; i < count; i++) {
634 u32 data = nv_ro32(bios, init->offset);
635
636 if (i == conf) {
637 trace("\t0x%08x *\n", data);
638 init_wr32(init, reg, data);
639 } else {
640 trace("\t0x%08x\n", data);
641 }
642
643 init->offset += 4;
644 }
645 trace("}]\n");
646}
647
648
649
650
651
652static void
653init_repeat(struct nvbios_init *init)
654{
655 struct nouveau_bios *bios = init->bios;
656 u8 count = nv_ro08(bios, init->offset + 1);
657 u16 repeat = init->repeat;
658
659 trace("REPEAT\t0x%02x\n", count);
660 init->offset += 2;
661
662 init->repeat = init->offset;
663 init->repend = init->offset;
664 while (count--) {
665 init->offset = init->repeat;
666 nvbios_exec(init);
667 if (count)
668 trace("REPEAT\t0x%02x\n", count);
669 }
670 init->offset = init->repend;
671 init->repeat = repeat;
672}
673
674
675
676
677
678static void
679init_io_restrict_pll(struct nvbios_init *init)
680{
681 struct nouveau_bios *bios = init->bios;
682 u16 port = nv_ro16(bios, init->offset + 1);
683 u8 index = nv_ro08(bios, init->offset + 3);
684 u8 mask = nv_ro08(bios, init->offset + 4);
685 u8 shift = nv_ro08(bios, init->offset + 5);
686 s8 iofc = nv_ro08(bios, init->offset + 6);
687 u8 count = nv_ro08(bios, init->offset + 7);
688 u32 reg = nv_ro32(bios, init->offset + 8);
689 u8 conf, i;
690
691 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
692 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
693 reg, port, index, mask, shift, iofc);
694 init->offset += 12;
695
696 conf = (init_rdvgai(init, port, index) & mask) >> shift;
697 for (i = 0; i < count; i++) {
698 u32 freq = nv_ro16(bios, init->offset) * 10;
699
700 if (i == conf) {
701 trace("\t%dkHz *\n", freq);
702 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
703 freq *= 2;
704 init_prog_pll(init, reg, freq);
705 } else {
706 trace("\t%dkHz\n", freq);
707 }
708
709 init->offset += 2;
710 }
711 trace("}]\n");
712}
713
714
715
716
717
718static void
719init_end_repeat(struct nvbios_init *init)
720{
721 trace("END_REPEAT\n");
722 init->offset += 1;
723
724 if (init->repeat) {
725 init->repend = init->offset;
726 init->offset = 0;
727 }
728}
729
730
731
732
733
734static void
735init_copy(struct nvbios_init *init)
736{
737 struct nouveau_bios *bios = init->bios;
738 u32 reg = nv_ro32(bios, init->offset + 1);
739 u8 shift = nv_ro08(bios, init->offset + 5);
740 u8 smask = nv_ro08(bios, init->offset + 6);
741 u16 port = nv_ro16(bios, init->offset + 7);
742 u8 index = nv_ro08(bios, init->offset + 9);
743 u8 mask = nv_ro08(bios, init->offset + 10);
744 u8 data;
745
746 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
747 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
748 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
749 (shift & 0x80) ? (0x100 - shift) : shift, smask);
750 init->offset += 11;
751
752 data = init_rdvgai(init, port, index) & mask;
753 data |= init_shift(init_rd32(init, reg), shift) & smask;
754 init_wrvgai(init, port, index, data);
755}
756
757
758
759
760
761static void
762init_not(struct nvbios_init *init)
763{
764 trace("NOT\n");
765 init->offset += 1;
766 init_exec_inv(init);
767}
768
769
770
771
772
773static void
774init_io_flag_condition(struct nvbios_init *init)
775{
776 struct nouveau_bios *bios = init->bios;
777 u8 cond = nv_ro08(bios, init->offset + 1);
778
779 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
780 init->offset += 2;
781
782 if (!init_io_flag_condition_met(init, cond))
783 init_exec_set(init, false);
784}
785
786
787
788
789
790static void
791init_dp_condition(struct nvbios_init *init)
792{
793 struct nouveau_bios *bios = init->bios;
794 struct nvbios_dpout info;
795 u8 cond = nv_ro08(bios, init->offset + 1);
796 u8 unkn = nv_ro08(bios, init->offset + 2);
797 u8 ver, hdr, cnt, len;
798 u16 data;
799
800 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
801 init->offset += 3;
802
803 switch (cond) {
804 case 0:
805 if (init_conn(init) != DCB_CONNECTOR_eDP)
806 init_exec_set(init, false);
807 break;
808 case 1:
809 case 2:
810 if ( init->outp &&
811 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
812 (init->outp->or << 0) |
813 (init->outp->sorconf.link << 6),
814 &ver, &hdr, &cnt, &len, &info)))
815 {
816 if (!(info.flags & cond))
817 init_exec_set(init, false);
818 break;
819 }
820
821 if (init_exec(init))
822 warn("script needs dp output table data\n");
823 break;
824 case 5:
825 if (!(init_rdauxr(init, 0x0d) & 1))
826 init_exec_set(init, false);
827 break;
828 default:
829 warn("unknown dp condition 0x%02x\n", cond);
830 break;
831 }
832}
833
834
835
836
837
838static void
839init_io_mask_or(struct nvbios_init *init)
840{
841 struct nouveau_bios *bios = init->bios;
842 u8 index = nv_ro08(bios, init->offset + 1);
843 u8 or = init_or(init);
844 u8 data;
845
846 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
847 init->offset += 2;
848
849 data = init_rdvgai(init, 0x03d4, index);
850 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
851}
852
853
854
855
856
857static void
858init_io_or(struct nvbios_init *init)
859{
860 struct nouveau_bios *bios = init->bios;
861 u8 index = nv_ro08(bios, init->offset + 1);
862 u8 or = init_or(init);
863 u8 data;
864
865 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
866 init->offset += 2;
867
868 data = init_rdvgai(init, 0x03d4, index);
869 init_wrvgai(init, 0x03d4, index, data | (1 << or));
870}
871
872
873
874
875
876static void
877init_idx_addr_latched(struct nvbios_init *init)
878{
879 struct nouveau_bios *bios = init->bios;
880 u32 creg = nv_ro32(bios, init->offset + 1);
881 u32 dreg = nv_ro32(bios, init->offset + 5);
882 u32 mask = nv_ro32(bios, init->offset + 9);
883 u32 data = nv_ro32(bios, init->offset + 13);
884 u8 count = nv_ro08(bios, init->offset + 17);
885
886 trace("INDEX_ADDRESS_LATCHED\t"
887 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
888 creg, dreg, mask, data);
889 init->offset += 18;
890
891 while (count--) {
892 u8 iaddr = nv_ro08(bios, init->offset + 0);
893 u8 idata = nv_ro08(bios, init->offset + 1);
894
895 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
896 init->offset += 2;
897
898 init_wr32(init, dreg, idata);
899 init_mask(init, creg, ~mask, data | iaddr);
900 }
901}
902
903
904
905
906
907static void
908init_io_restrict_pll2(struct nvbios_init *init)
909{
910 struct nouveau_bios *bios = init->bios;
911 u16 port = nv_ro16(bios, init->offset + 1);
912 u8 index = nv_ro08(bios, init->offset + 3);
913 u8 mask = nv_ro08(bios, init->offset + 4);
914 u8 shift = nv_ro08(bios, init->offset + 5);
915 u8 count = nv_ro08(bios, init->offset + 6);
916 u32 reg = nv_ro32(bios, init->offset + 7);
917 u8 conf, i;
918
919 trace("IO_RESTRICT_PLL2\t"
920 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
921 reg, port, index, mask, shift);
922 init->offset += 11;
923
924 conf = (init_rdvgai(init, port, index) & mask) >> shift;
925 for (i = 0; i < count; i++) {
926 u32 freq = nv_ro32(bios, init->offset);
927 if (i == conf) {
928 trace("\t%dkHz *\n", freq);
929 init_prog_pll(init, reg, freq);
930 } else {
931 trace("\t%dkHz\n", freq);
932 }
933 init->offset += 4;
934 }
935 trace("}]\n");
936}
937
938
939
940
941
942static void
943init_pll2(struct nvbios_init *init)
944{
945 struct nouveau_bios *bios = init->bios;
946 u32 reg = nv_ro32(bios, init->offset + 1);
947 u32 freq = nv_ro32(bios, init->offset + 5);
948
949 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
950 init->offset += 9;
951
952 init_prog_pll(init, reg, freq);
953}
954
955
956
957
958
959static void
960init_i2c_byte(struct nvbios_init *init)
961{
962 struct nouveau_bios *bios = init->bios;
963 u8 index = nv_ro08(bios, init->offset + 1);
964 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
965 u8 count = nv_ro08(bios, init->offset + 3);
966
967 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
968 init->offset += 4;
969
970 while (count--) {
971 u8 reg = nv_ro08(bios, init->offset + 0);
972 u8 mask = nv_ro08(bios, init->offset + 1);
973 u8 data = nv_ro08(bios, init->offset + 2);
974 int val;
975
976 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
977 init->offset += 3;
978
979 val = init_rdi2cr(init, index, addr, reg);
980 if (val < 0)
981 continue;
982 init_wri2cr(init, index, addr, reg, (val & mask) | data);
983 }
984}
985
986
987
988
989
990static void
991init_zm_i2c_byte(struct nvbios_init *init)
992{
993 struct nouveau_bios *bios = init->bios;
994 u8 index = nv_ro08(bios, init->offset + 1);
995 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
996 u8 count = nv_ro08(bios, init->offset + 3);
997
998 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
999 init->offset += 4;
1000
1001 while (count--) {
1002 u8 reg = nv_ro08(bios, init->offset + 0);
1003 u8 data = nv_ro08(bios, init->offset + 1);
1004
1005 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1006 init->offset += 2;
1007
1008 init_wri2cr(init, index, addr, reg, data);
1009 }
1010
1011}
1012
1013
1014
1015
1016
1017static void
1018init_zm_i2c(struct nvbios_init *init)
1019{
1020 struct nouveau_bios *bios = init->bios;
1021 u8 index = nv_ro08(bios, init->offset + 1);
1022 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1023 u8 count = nv_ro08(bios, init->offset + 3);
1024 u8 data[256], i;
1025
1026 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1027 init->offset += 4;
1028
1029 for (i = 0; i < count; i++) {
1030 data[i] = nv_ro08(bios, init->offset);
1031 trace("\t0x%02x\n", data[i]);
1032 init->offset++;
1033 }
1034
1035 if (init_exec(init)) {
1036 struct nouveau_i2c_port *port = init_i2c(init, index);
1037 struct i2c_msg msg = {
1038 .addr = addr, .flags = 0, .len = count, .buf = data,
1039 };
1040 int ret;
1041
1042 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1043 warn("i2c wr failed, %d\n", ret);
1044 }
1045}
1046
1047
1048
1049
1050
1051static void
1052init_tmds(struct nvbios_init *init)
1053{
1054 struct nouveau_bios *bios = init->bios;
1055 u8 tmds = nv_ro08(bios, init->offset + 1);
1056 u8 addr = nv_ro08(bios, init->offset + 2);
1057 u8 mask = nv_ro08(bios, init->offset + 3);
1058 u8 data = nv_ro08(bios, init->offset + 4);
1059 u32 reg = init_tmds_reg(init, tmds);
1060
1061 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1062 tmds, addr, mask, data);
1063 init->offset += 5;
1064
1065 if (reg == 0)
1066 return;
1067
1068 init_wr32(init, reg + 0, addr | 0x00010000);
1069 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1070 init_wr32(init, reg + 0, addr);
1071}
1072
1073
1074
1075
1076
1077static void
1078init_zm_tmds_group(struct nvbios_init *init)
1079{
1080 struct nouveau_bios *bios = init->bios;
1081 u8 tmds = nv_ro08(bios, init->offset + 1);
1082 u8 count = nv_ro08(bios, init->offset + 2);
1083 u32 reg = init_tmds_reg(init, tmds);
1084
1085 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1086 init->offset += 3;
1087
1088 while (count--) {
1089 u8 addr = nv_ro08(bios, init->offset + 0);
1090 u8 data = nv_ro08(bios, init->offset + 1);
1091
1092 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1093 init->offset += 2;
1094
1095 init_wr32(init, reg + 4, data);
1096 init_wr32(init, reg + 0, addr);
1097 }
1098}
1099
1100
1101
1102
1103
1104static void
1105init_cr_idx_adr_latch(struct nvbios_init *init)
1106{
1107 struct nouveau_bios *bios = init->bios;
1108 u8 addr0 = nv_ro08(bios, init->offset + 1);
1109 u8 addr1 = nv_ro08(bios, init->offset + 2);
1110 u8 base = nv_ro08(bios, init->offset + 3);
1111 u8 count = nv_ro08(bios, init->offset + 4);
1112 u8 save0;
1113
1114 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1115 init->offset += 5;
1116
1117 save0 = init_rdvgai(init, 0x03d4, addr0);
1118 while (count--) {
1119 u8 data = nv_ro08(bios, init->offset);
1120
1121 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1122 init->offset += 1;
1123
1124 init_wrvgai(init, 0x03d4, addr0, base++);
1125 init_wrvgai(init, 0x03d4, addr1, data);
1126 }
1127 init_wrvgai(init, 0x03d4, addr0, save0);
1128}
1129
1130
1131
1132
1133
1134static void
1135init_cr(struct nvbios_init *init)
1136{
1137 struct nouveau_bios *bios = init->bios;
1138 u8 addr = nv_ro08(bios, init->offset + 1);
1139 u8 mask = nv_ro08(bios, init->offset + 2);
1140 u8 data = nv_ro08(bios, init->offset + 3);
1141 u8 val;
1142
1143 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1144 init->offset += 4;
1145
1146 val = init_rdvgai(init, 0x03d4, addr) & mask;
1147 init_wrvgai(init, 0x03d4, addr, val | data);
1148}
1149
1150
1151
1152
1153
1154static void
1155init_zm_cr(struct nvbios_init *init)
1156{
1157 struct nouveau_bios *bios = init->bios;
1158 u8 addr = nv_ro08(bios, init->offset + 1);
1159 u8 data = nv_ro08(bios, init->offset + 2);
1160
1161 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1162 init->offset += 3;
1163
1164 init_wrvgai(init, 0x03d4, addr, data);
1165}
1166
1167
1168
1169
1170
1171static void
1172init_zm_cr_group(struct nvbios_init *init)
1173{
1174 struct nouveau_bios *bios = init->bios;
1175 u8 count = nv_ro08(bios, init->offset + 1);
1176
1177 trace("ZM_CR_GROUP\n");
1178 init->offset += 2;
1179
1180 while (count--) {
1181 u8 addr = nv_ro08(bios, init->offset + 0);
1182 u8 data = nv_ro08(bios, init->offset + 1);
1183
1184 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1185 init->offset += 2;
1186
1187 init_wrvgai(init, 0x03d4, addr, data);
1188 }
1189}
1190
1191
1192
1193
1194
1195static void
1196init_condition_time(struct nvbios_init *init)
1197{
1198 struct nouveau_bios *bios = init->bios;
1199 u8 cond = nv_ro08(bios, init->offset + 1);
1200 u8 retry = nv_ro08(bios, init->offset + 2);
1201 u8 wait = min((u16)retry * 50, 100);
1202
1203 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1204 init->offset += 3;
1205
1206 if (!init_exec(init))
1207 return;
1208
1209 while (wait--) {
1210 if (init_condition_met(init, cond))
1211 return;
1212 mdelay(20);
1213 }
1214
1215 init_exec_set(init, false);
1216}
1217
1218
1219
1220
1221
1222static void
1223init_ltime(struct nvbios_init *init)
1224{
1225 struct nouveau_bios *bios = init->bios;
1226 u16 msec = nv_ro16(bios, init->offset + 1);
1227
1228 trace("LTIME\t0x%04x\n", msec);
1229 init->offset += 3;
1230
1231 if (init_exec(init))
1232 mdelay(msec);
1233}
1234
1235
1236
1237
1238
1239static void
1240init_zm_reg_sequence(struct nvbios_init *init)
1241{
1242 struct nouveau_bios *bios = init->bios;
1243 u32 base = nv_ro32(bios, init->offset + 1);
1244 u8 count = nv_ro08(bios, init->offset + 5);
1245
1246 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1247 init->offset += 6;
1248
1249 while (count--) {
1250 u32 data = nv_ro32(bios, init->offset);
1251
1252 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1253 init->offset += 4;
1254
1255 init_wr32(init, base, data);
1256 base += 4;
1257 }
1258}
1259
1260
1261
1262
1263
1264static void
1265init_sub_direct(struct nvbios_init *init)
1266{
1267 struct nouveau_bios *bios = init->bios;
1268 u16 addr = nv_ro16(bios, init->offset + 1);
1269 u16 save;
1270
1271 trace("SUB_DIRECT\t0x%04x\n", addr);
1272
1273 if (init_exec(init)) {
1274 save = init->offset;
1275 init->offset = addr;
1276 if (nvbios_exec(init)) {
1277 error("error parsing sub-table\n");
1278 return;
1279 }
1280 init->offset = save;
1281 }
1282
1283 init->offset += 3;
1284}
1285
1286
1287
1288
1289
1290static void
1291init_jump(struct nvbios_init *init)
1292{
1293 struct nouveau_bios *bios = init->bios;
1294 u16 offset = nv_ro16(bios, init->offset + 1);
1295
1296 trace("JUMP\t0x%04x\n", offset);
1297
1298 if (init_exec(init))
1299 init->offset = offset;
1300 else
1301 init->offset += 3;
1302}
1303
1304
1305
1306
1307
1308static void
1309init_i2c_if(struct nvbios_init *init)
1310{
1311 struct nouveau_bios *bios = init->bios;
1312 u8 index = nv_ro08(bios, init->offset + 1);
1313 u8 addr = nv_ro08(bios, init->offset + 2);
1314 u8 reg = nv_ro08(bios, init->offset + 3);
1315 u8 mask = nv_ro08(bios, init->offset + 4);
1316 u8 data = nv_ro08(bios, init->offset + 5);
1317 u8 value;
1318
1319 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1320 index, addr, reg, mask, data);
1321 init->offset += 6;
1322 init_exec_force(init, true);
1323
1324 value = init_rdi2cr(init, index, addr, reg);
1325 if ((value & mask) != data)
1326 init_exec_set(init, false);
1327
1328 init_exec_force(init, false);
1329}
1330
1331
1332
1333
1334
1335static void
1336init_copy_nv_reg(struct nvbios_init *init)
1337{
1338 struct nouveau_bios *bios = init->bios;
1339 u32 sreg = nv_ro32(bios, init->offset + 1);
1340 u8 shift = nv_ro08(bios, init->offset + 5);
1341 u32 smask = nv_ro32(bios, init->offset + 6);
1342 u32 sxor = nv_ro32(bios, init->offset + 10);
1343 u32 dreg = nv_ro32(bios, init->offset + 14);
1344 u32 dmask = nv_ro32(bios, init->offset + 18);
1345 u32 data;
1346
1347 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1348 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1349 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1350 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1351 init->offset += 22;
1352
1353 data = init_shift(init_rd32(init, sreg), shift);
1354 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1355}
1356
1357
1358
1359
1360
1361static void
1362init_zm_index_io(struct nvbios_init *init)
1363{
1364 struct nouveau_bios *bios = init->bios;
1365 u16 port = nv_ro16(bios, init->offset + 1);
1366 u8 index = nv_ro08(bios, init->offset + 3);
1367 u8 data = nv_ro08(bios, init->offset + 4);
1368
1369 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1370 init->offset += 5;
1371
1372 init_wrvgai(init, port, index, data);
1373}
1374
1375
1376
1377
1378
1379static void
1380init_compute_mem(struct nvbios_init *init)
1381{
1382 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1383
1384 trace("COMPUTE_MEM\n");
1385 init->offset += 1;
1386
1387 init_exec_force(init, true);
1388 if (init_exec(init) && devinit->meminit)
1389 devinit->meminit(devinit);
1390 init_exec_force(init, false);
1391}
1392
1393
1394
1395
1396
1397static void
1398init_reset(struct nvbios_init *init)
1399{
1400 struct nouveau_bios *bios = init->bios;
1401 u32 reg = nv_ro32(bios, init->offset + 1);
1402 u32 data1 = nv_ro32(bios, init->offset + 5);
1403 u32 data2 = nv_ro32(bios, init->offset + 9);
1404 u32 savepci19;
1405
1406 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1407 init->offset += 13;
1408 init_exec_force(init, true);
1409
1410 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1411 init_wr32(init, reg, data1);
1412 udelay(10);
1413 init_wr32(init, reg, data2);
1414 init_wr32(init, 0x00184c, savepci19);
1415 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1416
1417 init_exec_force(init, false);
1418}
1419
1420
1421
1422
1423
1424static u16
1425init_configure_mem_clk(struct nvbios_init *init)
1426{
1427 u16 mdata = bmp_mem_init_table(init->bios);
1428 if (mdata)
1429 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1430 return mdata;
1431}
1432
1433static void
1434init_configure_mem(struct nvbios_init *init)
1435{
1436 struct nouveau_bios *bios = init->bios;
1437 u16 mdata, sdata;
1438 u32 addr, data;
1439
1440 trace("CONFIGURE_MEM\n");
1441 init->offset += 1;
1442
1443 if (bios->version.major > 2) {
1444 init_done(init);
1445 return;
1446 }
1447 init_exec_force(init, true);
1448
1449 mdata = init_configure_mem_clk(init);
1450 sdata = bmp_sdr_seq_table(bios);
1451 if (nv_ro08(bios, mdata) & 0x01)
1452 sdata = bmp_ddr_seq_table(bios);
1453 mdata += 6;
1454
1455 data = init_rdvgai(init, 0x03c4, 0x01);
1456 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1457
1458 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1459 switch (addr) {
1460 case 0x10021c:
1461 case 0x1002d0:
1462 case 0x1002d4:
1463 data = 0x00000001;
1464 break;
1465 default:
1466 data = nv_ro32(bios, mdata);
1467 mdata += 4;
1468 if (data == 0xffffffff)
1469 continue;
1470 break;
1471 }
1472
1473 init_wr32(init, addr, data);
1474 }
1475
1476 init_exec_force(init, false);
1477}
1478
1479
1480
1481
1482
1483static void
1484init_configure_clk(struct nvbios_init *init)
1485{
1486 struct nouveau_bios *bios = init->bios;
1487 u16 mdata, clock;
1488
1489 trace("CONFIGURE_CLK\n");
1490 init->offset += 1;
1491
1492 if (bios->version.major > 2) {
1493 init_done(init);
1494 return;
1495 }
1496 init_exec_force(init, true);
1497
1498 mdata = init_configure_mem_clk(init);
1499
1500
1501 clock = nv_ro16(bios, mdata + 4) * 10;
1502 init_prog_pll(init, 0x680500, clock);
1503
1504
1505 clock = nv_ro16(bios, mdata + 2) * 10;
1506 if (nv_ro08(bios, mdata) & 0x01)
1507 clock *= 2;
1508 init_prog_pll(init, 0x680504, clock);
1509
1510 init_exec_force(init, false);
1511}
1512
1513
1514
1515
1516
1517static void
1518init_configure_preinit(struct nvbios_init *init)
1519{
1520 struct nouveau_bios *bios = init->bios;
1521 u32 strap;
1522
1523 trace("CONFIGURE_PREINIT\n");
1524 init->offset += 1;
1525
1526 if (bios->version.major > 2) {
1527 init_done(init);
1528 return;
1529 }
1530 init_exec_force(init, true);
1531
1532 strap = init_rd32(init, 0x101000);
1533 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1534 init_wrvgai(init, 0x03d4, 0x3c, strap);
1535
1536 init_exec_force(init, false);
1537}
1538
1539
1540
1541
1542
1543static void
1544init_io(struct nvbios_init *init)
1545{
1546 struct nouveau_bios *bios = init->bios;
1547 u16 port = nv_ro16(bios, init->offset + 1);
1548 u8 mask = nv_ro16(bios, init->offset + 3);
1549 u8 data = nv_ro16(bios, init->offset + 4);
1550 u8 value;
1551
1552 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1553 init->offset += 5;
1554
1555
1556
1557
1558
1559 if (nv_device(init->bios)->card_type >= NV_50 &&
1560 port == 0x03c3 && data == 0x01) {
1561 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1562 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1563 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1564 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1565 mdelay(10);
1566 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1567 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1568 init_wr32(init, 0x614100, 0x00800018);
1569 init_wr32(init, 0x614900, 0x00800018);
1570 mdelay(10);
1571 init_wr32(init, 0x614100, 0x10000018);
1572 init_wr32(init, 0x614900, 0x10000018);
1573 }
1574
1575 value = init_rdport(init, port) & mask;
1576 init_wrport(init, port, data | value);
1577}
1578
1579
1580
1581
1582
1583static void
1584init_sub(struct nvbios_init *init)
1585{
1586 struct nouveau_bios *bios = init->bios;
1587 u8 index = nv_ro08(bios, init->offset + 1);
1588 u16 addr, save;
1589
1590 trace("SUB\t0x%02x\n", index);
1591
1592 addr = init_script(bios, index);
1593 if (addr && init_exec(init)) {
1594 save = init->offset;
1595 init->offset = addr;
1596 if (nvbios_exec(init)) {
1597 error("error parsing sub-table\n");
1598 return;
1599 }
1600 init->offset = save;
1601 }
1602
1603 init->offset += 2;
1604}
1605
1606
1607
1608
1609
1610static void
1611init_ram_condition(struct nvbios_init *init)
1612{
1613 struct nouveau_bios *bios = init->bios;
1614 u8 mask = nv_ro08(bios, init->offset + 1);
1615 u8 value = nv_ro08(bios, init->offset + 2);
1616
1617 trace("RAM_CONDITION\t"
1618 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1619 init->offset += 3;
1620
1621 if ((init_rd32(init, 0x100000) & mask) != value)
1622 init_exec_set(init, false);
1623}
1624
1625
1626
1627
1628
1629static void
1630init_nv_reg(struct nvbios_init *init)
1631{
1632 struct nouveau_bios *bios = init->bios;
1633 u32 reg = nv_ro32(bios, init->offset + 1);
1634 u32 mask = nv_ro32(bios, init->offset + 5);
1635 u32 data = nv_ro32(bios, init->offset + 9);
1636
1637 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1638 init->offset += 13;
1639
1640 init_mask(init, reg, ~mask, data);
1641}
1642
1643
1644
1645
1646
1647static void
1648init_macro(struct nvbios_init *init)
1649{
1650 struct nouveau_bios *bios = init->bios;
1651 u8 macro = nv_ro08(bios, init->offset + 1);
1652 u16 table;
1653
1654 trace("MACRO\t0x%02x\n", macro);
1655
1656 table = init_macro_table(init);
1657 if (table) {
1658 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1659 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1660 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1661 init_wr32(init, addr, data);
1662 }
1663
1664 init->offset += 2;
1665}
1666
1667
1668
1669
1670
1671static void
1672init_resume(struct nvbios_init *init)
1673{
1674 trace("RESUME\n");
1675 init->offset += 1;
1676 init_exec_set(init, true);
1677}
1678
1679
1680
1681
1682
1683static void
1684init_time(struct nvbios_init *init)
1685{
1686 struct nouveau_bios *bios = init->bios;
1687 u16 usec = nv_ro16(bios, init->offset + 1);
1688
1689 trace("TIME\t0x%04x\n", usec);
1690 init->offset += 3;
1691
1692 if (init_exec(init)) {
1693 if (usec < 1000)
1694 udelay(usec);
1695 else
1696 mdelay((usec + 900) / 1000);
1697 }
1698}
1699
1700
1701
1702
1703
1704static void
1705init_condition(struct nvbios_init *init)
1706{
1707 struct nouveau_bios *bios = init->bios;
1708 u8 cond = nv_ro08(bios, init->offset + 1);
1709
1710 trace("CONDITION\t0x%02x\n", cond);
1711 init->offset += 2;
1712
1713 if (!init_condition_met(init, cond))
1714 init_exec_set(init, false);
1715}
1716
1717
1718
1719
1720
1721static void
1722init_io_condition(struct nvbios_init *init)
1723{
1724 struct nouveau_bios *bios = init->bios;
1725 u8 cond = nv_ro08(bios, init->offset + 1);
1726
1727 trace("IO_CONDITION\t0x%02x\n", cond);
1728 init->offset += 2;
1729
1730 if (!init_io_condition_met(init, cond))
1731 init_exec_set(init, false);
1732}
1733
1734
1735
1736
1737
1738static void
1739init_index_io(struct nvbios_init *init)
1740{
1741 struct nouveau_bios *bios = init->bios;
1742 u16 port = nv_ro16(bios, init->offset + 1);
1743 u8 index = nv_ro16(bios, init->offset + 3);
1744 u8 mask = nv_ro08(bios, init->offset + 4);
1745 u8 data = nv_ro08(bios, init->offset + 5);
1746 u8 value;
1747
1748 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1749 port, index, mask, data);
1750 init->offset += 6;
1751
1752 value = init_rdvgai(init, port, index) & mask;
1753 init_wrvgai(init, port, index, data | value);
1754}
1755
1756
1757
1758
1759
1760static void
1761init_pll(struct nvbios_init *init)
1762{
1763 struct nouveau_bios *bios = init->bios;
1764 u32 reg = nv_ro32(bios, init->offset + 1);
1765 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1766
1767 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1768 init->offset += 7;
1769
1770 init_prog_pll(init, reg, freq);
1771}
1772
1773
1774
1775
1776
1777static void
1778init_zm_reg(struct nvbios_init *init)
1779{
1780 struct nouveau_bios *bios = init->bios;
1781 u32 addr = nv_ro32(bios, init->offset + 1);
1782 u32 data = nv_ro32(bios, init->offset + 5);
1783
1784 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1785 init->offset += 9;
1786
1787 if (addr == 0x000200)
1788 data |= 0x00000001;
1789
1790 init_wr32(init, addr, data);
1791}
1792
1793
1794
1795
1796
1797static void
1798init_ram_restrict_pll(struct nvbios_init *init)
1799{
1800 struct nouveau_bios *bios = init->bios;
1801 u8 type = nv_ro08(bios, init->offset + 1);
1802 u8 count = init_ram_restrict_group_count(init);
1803 u8 strap = init_ram_restrict(init);
1804 u8 cconf;
1805
1806 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1807 init->offset += 2;
1808
1809 for (cconf = 0; cconf < count; cconf++) {
1810 u32 freq = nv_ro32(bios, init->offset);
1811
1812 if (cconf == strap) {
1813 trace("%dkHz *\n", freq);
1814 init_prog_pll(init, type, freq);
1815 } else {
1816 trace("%dkHz\n", freq);
1817 }
1818
1819 init->offset += 4;
1820 }
1821}
1822
1823
1824
1825
1826
1827static void
1828init_gpio(struct nvbios_init *init)
1829{
1830 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1831
1832 trace("GPIO\n");
1833 init->offset += 1;
1834
1835 if (init_exec(init) && gpio && gpio->reset)
1836 gpio->reset(gpio, DCB_GPIO_UNUSED);
1837}
1838
1839
1840
1841
1842
1843static void
1844init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1845{
1846 struct nouveau_bios *bios = init->bios;
1847 u32 addr = nv_ro32(bios, init->offset + 1);
1848 u8 incr = nv_ro08(bios, init->offset + 5);
1849 u8 num = nv_ro08(bios, init->offset + 6);
1850 u8 count = init_ram_restrict_group_count(init);
1851 u8 index = init_ram_restrict(init);
1852 u8 i, j;
1853
1854 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1855 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1856 init->offset += 7;
1857
1858 for (i = 0; i < num; i++) {
1859 trace("\tR[0x%06x] = {\n", addr);
1860 for (j = 0; j < count; j++) {
1861 u32 data = nv_ro32(bios, init->offset);
1862
1863 if (j == index) {
1864 trace("\t\t0x%08x *\n", data);
1865 init_wr32(init, addr, data);
1866 } else {
1867 trace("\t\t0x%08x\n", data);
1868 }
1869
1870 init->offset += 4;
1871 }
1872 trace("\t}\n");
1873 addr += incr;
1874 }
1875}
1876
1877
1878
1879
1880
1881static void
1882init_copy_zm_reg(struct nvbios_init *init)
1883{
1884 struct nouveau_bios *bios = init->bios;
1885 u32 sreg = nv_ro32(bios, init->offset + 1);
1886 u32 dreg = nv_ro32(bios, init->offset + 5);
1887
1888 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1889 init->offset += 9;
1890
1891 init_wr32(init, dreg, init_rd32(init, sreg));
1892}
1893
1894
1895
1896
1897
1898static void
1899init_zm_reg_group(struct nvbios_init *init)
1900{
1901 struct nouveau_bios *bios = init->bios;
1902 u32 addr = nv_ro32(bios, init->offset + 1);
1903 u8 count = nv_ro08(bios, init->offset + 5);
1904
1905 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1906 init->offset += 6;
1907
1908 while (count--) {
1909 u32 data = nv_ro32(bios, init->offset);
1910 trace("\t0x%08x\n", data);
1911 init_wr32(init, addr, data);
1912 init->offset += 4;
1913 }
1914}
1915
1916
1917
1918
1919
1920static void
1921init_xlat(struct nvbios_init *init)
1922{
1923 struct nouveau_bios *bios = init->bios;
1924 u32 saddr = nv_ro32(bios, init->offset + 1);
1925 u8 sshift = nv_ro08(bios, init->offset + 5);
1926 u8 smask = nv_ro08(bios, init->offset + 6);
1927 u8 index = nv_ro08(bios, init->offset + 7);
1928 u32 daddr = nv_ro32(bios, init->offset + 8);
1929 u32 dmask = nv_ro32(bios, init->offset + 12);
1930 u8 shift = nv_ro08(bios, init->offset + 16);
1931 u32 data;
1932
1933 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1934 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1935 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1936 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1937 init->offset += 17;
1938
1939 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1940 data = init_xlat_(init, index, data) << shift;
1941 init_mask(init, daddr, ~dmask, data);
1942}
1943
1944
1945
1946
1947
1948static void
1949init_zm_mask_add(struct nvbios_init *init)
1950{
1951 struct nouveau_bios *bios = init->bios;
1952 u32 addr = nv_ro32(bios, init->offset + 1);
1953 u32 mask = nv_ro32(bios, init->offset + 5);
1954 u32 add = nv_ro32(bios, init->offset + 9);
1955 u32 data;
1956
1957 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1958 init->offset += 13;
1959
1960 data = init_rd32(init, addr);
1961 data = (data & mask) | ((data + add) & ~mask);
1962 init_wr32(init, addr, data);
1963}
1964
1965
1966
1967
1968
1969static void
1970init_auxch(struct nvbios_init *init)
1971{
1972 struct nouveau_bios *bios = init->bios;
1973 u32 addr = nv_ro32(bios, init->offset + 1);
1974 u8 count = nv_ro08(bios, init->offset + 5);
1975
1976 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1977 init->offset += 6;
1978
1979 while (count--) {
1980 u8 mask = nv_ro08(bios, init->offset + 0);
1981 u8 data = nv_ro08(bios, init->offset + 1);
1982 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1983 mask = init_rdauxr(init, addr) & mask;
1984 init_wrauxr(init, addr, mask | data);
1985 init->offset += 2;
1986 }
1987}
1988
1989
1990
1991
1992
1993static void
1994init_zm_auxch(struct nvbios_init *init)
1995{
1996 struct nouveau_bios *bios = init->bios;
1997 u32 addr = nv_ro32(bios, init->offset + 1);
1998 u8 count = nv_ro08(bios, init->offset + 5);
1999
2000 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2001 init->offset += 6;
2002
2003 while (count--) {
2004 u8 data = nv_ro08(bios, init->offset + 0);
2005 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2006 init_wrauxr(init, addr, data);
2007 init->offset += 1;
2008 }
2009}
2010
2011
2012
2013
2014
2015static void
2016init_i2c_long_if(struct nvbios_init *init)
2017{
2018 struct nouveau_bios *bios = init->bios;
2019 u8 index = nv_ro08(bios, init->offset + 1);
2020 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2021 u8 reglo = nv_ro08(bios, init->offset + 3);
2022 u8 reghi = nv_ro08(bios, init->offset + 4);
2023 u8 mask = nv_ro08(bios, init->offset + 5);
2024 u8 data = nv_ro08(bios, init->offset + 6);
2025 struct nouveau_i2c_port *port;
2026
2027 trace("I2C_LONG_IF\t"
2028 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2029 index, addr, reglo, reghi, mask, data);
2030 init->offset += 7;
2031
2032 port = init_i2c(init, index);
2033 if (port) {
2034 u8 i[2] = { reghi, reglo };
2035 u8 o[1] = {};
2036 struct i2c_msg msg[] = {
2037 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2038 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2039 };
2040 int ret;
2041
2042 ret = i2c_transfer(&port->adapter, msg, 2);
2043 if (ret == 2 && ((o[0] & mask) == data))
2044 return;
2045 }
2046
2047 init_exec_set(init, false);
2048}
2049
2050
2051
2052
2053
2054static void
2055init_gpio_ne(struct nvbios_init *init)
2056{
2057 struct nouveau_bios *bios = init->bios;
2058 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2059 struct dcb_gpio_func func;
2060 u8 count = nv_ro08(bios, init->offset + 1);
2061 u8 idx = 0, ver, len;
2062 u16 data, i;
2063
2064 trace("GPIO_NE\t");
2065 init->offset += 2;
2066
2067 for (i = init->offset; i < init->offset + count; i++)
2068 cont("0x%02x ", nv_ro08(bios, i));
2069 cont("\n");
2070
2071 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2072 if (func.func != DCB_GPIO_UNUSED) {
2073 for (i = init->offset; i < init->offset + count; i++) {
2074 if (func.func == nv_ro08(bios, i))
2075 break;
2076 }
2077
2078 trace("\tFUNC[0x%02x]", func.func);
2079 if (i == (init->offset + count)) {
2080 cont(" *");
2081 if (init_exec(init) && gpio && gpio->reset)
2082 gpio->reset(gpio, func.func);
2083 }
2084 cont("\n");
2085 }
2086 }
2087
2088 init->offset += count;
2089}
2090
2091static struct nvbios_init_opcode {
2092 void (*exec)(struct nvbios_init *);
2093} init_opcode[] = {
2094 [0x32] = { init_io_restrict_prog },
2095 [0x33] = { init_repeat },
2096 [0x34] = { init_io_restrict_pll },
2097 [0x36] = { init_end_repeat },
2098 [0x37] = { init_copy },
2099 [0x38] = { init_not },
2100 [0x39] = { init_io_flag_condition },
2101 [0x3a] = { init_dp_condition },
2102 [0x3b] = { init_io_mask_or },
2103 [0x3c] = { init_io_or },
2104 [0x49] = { init_idx_addr_latched },
2105 [0x4a] = { init_io_restrict_pll2 },
2106 [0x4b] = { init_pll2 },
2107 [0x4c] = { init_i2c_byte },
2108 [0x4d] = { init_zm_i2c_byte },
2109 [0x4e] = { init_zm_i2c },
2110 [0x4f] = { init_tmds },
2111 [0x50] = { init_zm_tmds_group },
2112 [0x51] = { init_cr_idx_adr_latch },
2113 [0x52] = { init_cr },
2114 [0x53] = { init_zm_cr },
2115 [0x54] = { init_zm_cr_group },
2116 [0x56] = { init_condition_time },
2117 [0x57] = { init_ltime },
2118 [0x58] = { init_zm_reg_sequence },
2119 [0x5b] = { init_sub_direct },
2120 [0x5c] = { init_jump },
2121 [0x5e] = { init_i2c_if },
2122 [0x5f] = { init_copy_nv_reg },
2123 [0x62] = { init_zm_index_io },
2124 [0x63] = { init_compute_mem },
2125 [0x65] = { init_reset },
2126 [0x66] = { init_configure_mem },
2127 [0x67] = { init_configure_clk },
2128 [0x68] = { init_configure_preinit },
2129 [0x69] = { init_io },
2130 [0x6b] = { init_sub },
2131 [0x6d] = { init_ram_condition },
2132 [0x6e] = { init_nv_reg },
2133 [0x6f] = { init_macro },
2134 [0x71] = { init_done },
2135 [0x72] = { init_resume },
2136 [0x74] = { init_time },
2137 [0x75] = { init_condition },
2138 [0x76] = { init_io_condition },
2139 [0x78] = { init_index_io },
2140 [0x79] = { init_pll },
2141 [0x7a] = { init_zm_reg },
2142 [0x87] = { init_ram_restrict_pll },
2143 [0x8c] = { init_reserved },
2144 [0x8d] = { init_reserved },
2145 [0x8e] = { init_gpio },
2146 [0x8f] = { init_ram_restrict_zm_reg_group },
2147 [0x90] = { init_copy_zm_reg },
2148 [0x91] = { init_zm_reg_group },
2149 [0x92] = { init_reserved },
2150 [0x96] = { init_xlat },
2151 [0x97] = { init_zm_mask_add },
2152 [0x98] = { init_auxch },
2153 [0x99] = { init_zm_auxch },
2154 [0x9a] = { init_i2c_long_if },
2155 [0xa9] = { init_gpio_ne },
2156 [0xaa] = { init_reserved },
2157};
2158
2159#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2160
2161int
2162nvbios_exec(struct nvbios_init *init)
2163{
2164 init->nested++;
2165 while (init->offset) {
2166 u8 opcode = nv_ro08(init->bios, init->offset);
2167 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2168 error("unknown opcode 0x%02x\n", opcode);
2169 return -EINVAL;
2170 }
2171
2172 init_opcode[opcode].exec(init);
2173 }
2174 init->nested--;
2175 return 0;
2176}
2177
2178int
2179nvbios_init(struct nouveau_subdev *subdev, bool execute)
2180{
2181 struct nouveau_bios *bios = nouveau_bios(subdev);
2182 int ret = 0;
2183 int i = -1;
2184 u16 data;
2185
2186 if (execute)
2187 nv_info(bios, "running init tables\n");
2188 while (!ret && (data = (init_script(bios, ++i)))) {
2189 struct nvbios_init init = {
2190 .subdev = subdev,
2191 .bios = bios,
2192 .offset = data,
2193 .outp = NULL,
2194 .crtc = -1,
2195 .execute = execute ? 1 : 0,
2196 };
2197
2198 ret = nvbios_exec(&init);
2199 }
2200
2201
2202
2203
2204 if (!ret && (data = init_unknown_script(bios))) {
2205 struct nvbios_init init = {
2206 .subdev = subdev,
2207 .bios = bios,
2208 .offset = data,
2209 .outp = NULL,
2210 .crtc = -1,
2211 .execute = execute ? 1 : 0,
2212 };
2213
2214 ret = nvbios_exec(&init);
2215 }
2216
2217 return ret;
2218}
2219
