1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef CIK_H 25#define CIK_H 26 27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 29 30#define CIK_RB_BITMAP_WIDTH_PER_SH 2 31#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 32 33/* DIDT IND registers */ 34#define DIDT_SQ_CTRL0 0x0 35# define DIDT_CTRL_EN (1 << 0) 36#define DIDT_DB_CTRL0 0x20 37#define DIDT_TD_CTRL0 0x40 38#define DIDT_TCP_CTRL0 0x60 39 40/* SMC IND registers */ 41#define DPM_TABLE_475 0x3F768 42# define SamuBootLevel(x) ((x) << 0) 43# define SamuBootLevel_MASK 0x000000ff 44# define SamuBootLevel_SHIFT 0 45# define AcpBootLevel(x) ((x) << 8) 46# define AcpBootLevel_MASK 0x0000ff00 47# define AcpBootLevel_SHIFT 8 48# define VceBootLevel(x) ((x) << 16) 49# define VceBootLevel_MASK 0x00ff0000 50# define VceBootLevel_SHIFT 16 51# define UvdBootLevel(x) ((x) << 24) 52# define UvdBootLevel_MASK 0xff000000 53# define UvdBootLevel_SHIFT 24 54 55#define FIRMWARE_FLAGS 0x3F800 56# define INTERRUPTS_ENABLED (1 << 0) 57 58#define NB_DPM_CONFIG_1 0x3F9E8 59# define Dpm0PgNbPsLo(x) ((x) << 0) 60# define Dpm0PgNbPsLo_MASK 0x000000ff 61# define Dpm0PgNbPsLo_SHIFT 0 62# define Dpm0PgNbPsHi(x) ((x) << 8) 63# define Dpm0PgNbPsHi_MASK 0x0000ff00 64# define Dpm0PgNbPsHi_SHIFT 8 65# define DpmXNbPsLo(x) ((x) << 16) 66# define DpmXNbPsLo_MASK 0x00ff0000 67# define DpmXNbPsLo_SHIFT 16 68# define DpmXNbPsHi(x) ((x) << 24) 69# define DpmXNbPsHi_MASK 0xff000000 70# define DpmXNbPsHi_SHIFT 24 71 72#define SMC_SYSCON_RESET_CNTL 0x80000000 73# define RST_REG (1 << 0) 74#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 75# define CK_DISABLE (1 << 0) 76# define CKEN (1 << 24) 77 78#define SMC_SYSCON_MISC_CNTL 0x80000010 79 80#define SMC_SYSCON_MSG_ARG_0 0x80000068 81 82#define SMC_PC_C 0x80000370 83 84#define SMC_SCRATCH9 0x80000424 85 86#define RCU_UC_EVENTS 0xC0000004 87# define BOOT_SEQ_DONE (1 << 7) 88 89#define GENERAL_PWRMGT 0xC0200000 90# define GLOBAL_PWRMGT_EN (1 << 0) 91# define STATIC_PM_EN (1 << 1) 92# define THERMAL_PROTECTION_DIS (1 << 2) 93# define THERMAL_PROTECTION_TYPE (1 << 3) 94# define SW_SMIO_INDEX(x) ((x) << 6) 95# define SW_SMIO_INDEX_MASK (1 << 6) 96# define SW_SMIO_INDEX_SHIFT 6 97# define VOLT_PWRMGT_EN (1 << 10) 98# define GPU_COUNTER_CLK (1 << 15) 99# define DYN_SPREAD_SPECTRUM_EN (1 << 23) 100 101#define CNB_PWRMGT_CNTL 0xC0200004 102# define GNB_SLOW_MODE(x) ((x) << 0) 103# define GNB_SLOW_MODE_MASK (3 << 0) 104# define GNB_SLOW_MODE_SHIFT 0 105# define GNB_SLOW (1 << 2) 106# define FORCE_NB_PS1 (1 << 3) 107# define DPM_ENABLED (1 << 4) 108 109#define SCLK_PWRMGT_CNTL 0xC0200008 110# define SCLK_PWRMGT_OFF (1 << 0) 111# define RESET_BUSY_CNT (1 << 4) 112# define RESET_SCLK_CNT (1 << 5) 113# define DYNAMIC_PM_EN (1 << 21) 114 115#define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 116# define CURRENT_STATE_MASK (0xf << 4) 117# define CURRENT_STATE_SHIFT 4 118# define CURR_MCLK_INDEX_MASK (0xf << 8) 119# define CURR_MCLK_INDEX_SHIFT 8 120# define CURR_SCLK_INDEX_MASK (0x1f << 16) 121# define CURR_SCLK_INDEX_SHIFT 16 122 123#define CG_SSP 0xC0200044 124# define SST(x) ((x) << 0) 125# define SST_MASK (0xffff << 0) 126# define SSTU(x) ((x) << 16) 127# define SSTU_MASK (0xf << 16) 128 129#define CG_DISPLAY_GAP_CNTL 0xC0200060 130# define DISP_GAP(x) ((x) << 0) 131# define DISP_GAP_MASK (3 << 0) 132# define VBI_TIMER_COUNT(x) ((x) << 4) 133# define VBI_TIMER_COUNT_MASK (0x3fff << 4) 134# define VBI_TIMER_UNIT(x) ((x) << 20) 135# define VBI_TIMER_UNIT_MASK (7 << 20) 136# define DISP_GAP_MCHG(x) ((x) << 24) 137# define DISP_GAP_MCHG_MASK (3 << 24) 138 139#define SMU_VOLTAGE_STATUS 0xC0200094 140# define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 141# define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 142 143#define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 144# define CURR_PCIE_INDEX_MASK (0xf << 24) 145# define CURR_PCIE_INDEX_SHIFT 24 146 147#define CG_ULV_PARAMETER 0xC0200158 148 149#define CG_FTV_0 0xC02001A8 150#define CG_FTV_1 0xC02001AC 151#define CG_FTV_2 0xC02001B0 152#define CG_FTV_3 0xC02001B4 153#define CG_FTV_4 0xC02001B8 154#define CG_FTV_5 0xC02001BC 155#define CG_FTV_6 0xC02001C0 156#define CG_FTV_7 0xC02001C4 157 158#define CG_DISPLAY_GAP_CNTL2 0xC0200230 159 160#define LCAC_SX0_OVR_SEL 0xC0400D04 161#define LCAC_SX0_OVR_VAL 0xC0400D08 162 163#define LCAC_MC0_CNTL 0xC0400D30 164#define LCAC_MC0_OVR_SEL 0xC0400D34 165#define LCAC_MC0_OVR_VAL 0xC0400D38 166#define LCAC_MC1_CNTL 0xC0400D3C 167#define LCAC_MC1_OVR_SEL 0xC0400D40 168#define LCAC_MC1_OVR_VAL 0xC0400D44 169 170#define LCAC_MC2_OVR_SEL 0xC0400D4C 171#define LCAC_MC2_OVR_VAL 0xC0400D50 172 173#define LCAC_MC3_OVR_SEL 0xC0400D58 174#define LCAC_MC3_OVR_VAL 0xC0400D5C 175 176#define LCAC_CPL_CNTL 0xC0400D80 177#define LCAC_CPL_OVR_SEL 0xC0400D84 178#define LCAC_CPL_OVR_VAL 0xC0400D88 179 180/* dGPU */ 181#define CG_THERMAL_CTRL 0xC0300004 182#define DPM_EVENT_SRC(x) ((x) << 0) 183#define DPM_EVENT_SRC_MASK (7 << 0) 184#define DIG_THERM_DPM(x) ((x) << 14) 185#define DIG_THERM_DPM_MASK 0x003FC000 186#define DIG_THERM_DPM_SHIFT 14 187 188#define CG_THERMAL_INT 0xC030000C 189#define CI_DIG_THERM_INTH(x) ((x) << 8) 190#define CI_DIG_THERM_INTH_MASK 0x0000FF00 191#define CI_DIG_THERM_INTH_SHIFT 8 192#define CI_DIG_THERM_INTL(x) ((x) << 16) 193#define CI_DIG_THERM_INTL_MASK 0x00FF0000 194#define CI_DIG_THERM_INTL_SHIFT 16 195#define THERM_INT_MASK_HIGH (1 << 24) 196#define THERM_INT_MASK_LOW (1 << 25) 197 198#define CG_MULT_THERMAL_STATUS 0xC0300014 199#define ASIC_MAX_TEMP(x) ((x) << 0) 200#define ASIC_MAX_TEMP_MASK 0x000001ff 201#define ASIC_MAX_TEMP_SHIFT 0 202#define CTF_TEMP(x) ((x) << 9) 203#define CTF_TEMP_MASK 0x0003fe00 204#define CTF_TEMP_SHIFT 9 205 206#define CG_SPLL_FUNC_CNTL 0xC0500140 207#define SPLL_RESET (1 << 0) 208#define SPLL_PWRON (1 << 1) 209#define SPLL_BYPASS_EN (1 << 3) 210#define SPLL_REF_DIV(x) ((x) << 5) 211#define SPLL_REF_DIV_MASK (0x3f << 5) 212#define SPLL_PDIV_A(x) ((x) << 20) 213#define SPLL_PDIV_A_MASK (0x7f << 20) 214#define SPLL_PDIV_A_SHIFT 20 215#define CG_SPLL_FUNC_CNTL_2 0xC0500144 216#define SCLK_MUX_SEL(x) ((x) << 0) 217#define SCLK_MUX_SEL_MASK (0x1ff << 0) 218#define CG_SPLL_FUNC_CNTL_3 0xC0500148 219#define SPLL_FB_DIV(x) ((x) << 0) 220#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 221#define SPLL_FB_DIV_SHIFT 0 222#define SPLL_DITHEN (1 << 28) 223#define CG_SPLL_FUNC_CNTL_4 0xC050014C 224 225#define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 226#define SSEN (1 << 0) 227#define CLK_S(x) ((x) << 4) 228#define CLK_S_MASK (0xfff << 4) 229#define CLK_S_SHIFT 4 230#define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 231#define CLK_V(x) ((x) << 0) 232#define CLK_V_MASK (0x3ffffff << 0) 233#define CLK_V_SHIFT 0 234 235#define MPLL_BYPASSCLK_SEL 0xC050019C 236# define MPLL_CLKOUT_SEL(x) ((x) << 8) 237# define MPLL_CLKOUT_SEL_MASK 0xFF00 238#define CG_CLKPIN_CNTL 0xC05001A0 239# define XTALIN_DIVIDE (1 << 1) 240# define BCLK_AS_XCLK (1 << 2) 241#define CG_CLKPIN_CNTL_2 0xC05001A4 242# define FORCE_BIF_REFCLK_EN (1 << 3) 243# define MUX_TCLK_TO_XCLK (1 << 8) 244#define THM_CLK_CNTL 0xC05001A8 245# define CMON_CLK_SEL(x) ((x) << 0) 246# define CMON_CLK_SEL_MASK 0xFF 247# define TMON_CLK_SEL(x) ((x) << 8) 248# define TMON_CLK_SEL_MASK 0xFF00 249#define MISC_CLK_CTRL 0xC05001AC 250# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 251# define DEEP_SLEEP_CLK_SEL_MASK 0xFF 252# define ZCLK_SEL(x) ((x) << 8) 253# define ZCLK_SEL_MASK 0xFF00 254 255/* KV/KB */ 256#define CG_THERMAL_INT_CTRL 0xC2100028 257#define DIG_THERM_INTH(x) ((x) << 0) 258#define DIG_THERM_INTH_MASK 0x000000FF 259#define DIG_THERM_INTH_SHIFT 0 260#define DIG_THERM_INTL(x) ((x) << 8) 261#define DIG_THERM_INTL_MASK 0x0000FF00 262#define DIG_THERM_INTL_SHIFT 8 263#define THERM_INTH_MASK (1 << 24) 264#define THERM_INTL_MASK (1 << 25) 265 266/* PCIE registers idx/data 0x38/0x3c */ 267#define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 268# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 269# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 270# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 271# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 272# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 273# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 274# define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 275# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 276# define PLL_RAMP_UP_TIME_0_SHIFT 24 277#define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 278# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 279# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 280# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 281# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 282# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 283# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 284# define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 285# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 286# define PLL_RAMP_UP_TIME_1_SHIFT 24 287 288#define PCIE_CNTL2 0x1001001c /* PCIE */ 289# define SLV_MEM_LS_EN (1 << 16) 290# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 291# define MST_MEM_LS_EN (1 << 18) 292# define REPLAY_MEM_LS_EN (1 << 19) 293 294#define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 295# define LC_REVERSE_RCVR (1 << 0) 296# define LC_REVERSE_XMIT (1 << 1) 297# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 298# define LC_OPERATING_LINK_WIDTH_SHIFT 2 299# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 300# define LC_DETECTED_LINK_WIDTH_SHIFT 5 301 302#define PCIE_P_CNTL 0x1400040 /* PCIE */ 303# define P_IGNORE_EDB_ERR (1 << 6) 304 305#define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 306#define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 307 308#define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 309# define LC_L0S_INACTIVITY(x) ((x) << 8) 310# define LC_L0S_INACTIVITY_MASK (0xf << 8) 311# define LC_L0S_INACTIVITY_SHIFT 8 312# define LC_L1_INACTIVITY(x) ((x) << 12) 313# define LC_L1_INACTIVITY_MASK (0xf << 12) 314# define LC_L1_INACTIVITY_SHIFT 12 315# define LC_PMI_TO_L1_DIS (1 << 16) 316# define LC_ASPM_TO_L1_DIS (1 << 24) 317 318#define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 319# define LC_LINK_WIDTH_SHIFT 0 320# define LC_LINK_WIDTH_MASK 0x7 321# define LC_LINK_WIDTH_X0 0 322# define LC_LINK_WIDTH_X1 1 323# define LC_LINK_WIDTH_X2 2 324# define LC_LINK_WIDTH_X4 3 325# define LC_LINK_WIDTH_X8 4 326# define LC_LINK_WIDTH_X16 6 327# define LC_LINK_WIDTH_RD_SHIFT 4 328# define LC_LINK_WIDTH_RD_MASK 0x70 329# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 330# define LC_RECONFIG_NOW (1 << 8) 331# define LC_RENEGOTIATION_SUPPORT (1 << 9) 332# define LC_RENEGOTIATE_EN (1 << 10) 333# define LC_SHORT_RECONFIG_EN (1 << 11) 334# define LC_UPCONFIGURE_SUPPORT (1 << 12) 335# define LC_UPCONFIGURE_DIS (1 << 13) 336# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 337# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 338# define LC_DYN_LANES_PWR_STATE_SHIFT 21 339#define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 340# define LC_XMIT_N_FTS(x) ((x) << 0) 341# define LC_XMIT_N_FTS_MASK (0xff << 0) 342# define LC_XMIT_N_FTS_SHIFT 0 343# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 344# define LC_N_FTS_MASK (0xff << 24) 345#define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 346# define LC_GEN2_EN_STRAP (1 << 0) 347# define LC_GEN3_EN_STRAP (1 << 1) 348# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 349# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 350# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 351# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 352# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 353# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 354# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 355# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 356# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 357# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 358# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 359# define LC_CURRENT_DATA_RATE_SHIFT 13 360# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 361# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 362# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 363# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 364# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 365 366#define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 367# define LC_ALLOW_PDWN_IN_L1 (1 << 17) 368# define LC_ALLOW_PDWN_IN_L23 (1 << 18) 369 370#define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 371# define LC_GO_TO_RECOVERY (1 << 30) 372#define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 373# define LC_REDO_EQ (1 << 5) 374# define LC_SET_QUIESCE (1 << 13) 375 376/* direct registers */ 377#define PCIE_INDEX 0x38 378#define PCIE_DATA 0x3C 379 380#define SMC_IND_INDEX_0 0x200 381#define SMC_IND_DATA_0 0x204 382 383#define SMC_IND_ACCESS_CNTL 0x240 384#define AUTO_INCREMENT_IND_0 (1 << 0) 385 386#define SMC_MESSAGE_0 0x250 387#define SMC_MSG_MASK 0xffff 388#define SMC_RESP_0 0x254 389#define SMC_RESP_MASK 0xffff 390 391#define SMC_MSG_ARG_0 0x290 392 393#define VGA_HDP_CONTROL 0x328 394#define VGA_MEMORY_DISABLE (1 << 4) 395 396#define DMIF_ADDR_CALC 0xC00 397 398#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 399# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 400# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 401 402#define SRBM_GFX_CNTL 0xE44 403#define PIPEID(x) ((x) << 0) 404#define MEID(x) ((x) << 2) 405#define VMID(x) ((x) << 4) 406#define QUEUEID(x) ((x) << 8) 407 408#define SRBM_STATUS2 0xE4C 409#define SDMA_BUSY (1 << 5) 410#define SDMA1_BUSY (1 << 6) 411#define SRBM_STATUS 0xE50 412#define UVD_RQ_PENDING (1 << 1) 413#define GRBM_RQ_PENDING (1 << 5) 414#define VMC_BUSY (1 << 8) 415#define MCB_BUSY (1 << 9) 416#define MCB_NON_DISPLAY_BUSY (1 << 10) 417#define MCC_BUSY (1 << 11) 418#define MCD_BUSY (1 << 12) 419#define SEM_BUSY (1 << 14) 420#define IH_BUSY (1 << 17) 421#define UVD_BUSY (1 << 19) 422 423#define SRBM_SOFT_RESET 0xE60 424#define SOFT_RESET_BIF (1 << 1) 425#define SOFT_RESET_R0PLL (1 << 4) 426#define SOFT_RESET_DC (1 << 5) 427#define SOFT_RESET_SDMA1 (1 << 6) 428#define SOFT_RESET_GRBM (1 << 8) 429#define SOFT_RESET_HDP (1 << 9) 430#define SOFT_RESET_IH (1 << 10) 431#define SOFT_RESET_MC (1 << 11) 432#define SOFT_RESET_ROM (1 << 14) 433#define SOFT_RESET_SEM (1 << 15) 434#define SOFT_RESET_VMC (1 << 17) 435#define SOFT_RESET_SDMA (1 << 20) 436#define SOFT_RESET_TST (1 << 21) 437#define SOFT_RESET_REGBB (1 << 22) 438#define SOFT_RESET_ORB (1 << 23) 439#define SOFT_RESET_VCE (1 << 24) 440 441#define VM_L2_CNTL 0x1400 442#define ENABLE_L2_CACHE (1 << 0) 443#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 444#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 445#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 446#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 447#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 448#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 449#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 450#define VM_L2_CNTL2 0x1404 451#define INVALIDATE_ALL_L1_TLBS (1 << 0) 452#define INVALIDATE_L2_CACHE (1 << 1) 453#define INVALIDATE_CACHE_MODE(x) ((x) << 26) 454#define INVALIDATE_PTE_AND_PDE_CACHES 0 455#define INVALIDATE_ONLY_PTE_CACHES 1 456#define INVALIDATE_ONLY_PDE_CACHES 2 457#define VM_L2_CNTL3 0x1408 458#define BANK_SELECT(x) ((x) << 0) 459#define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 460#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 461#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 462#define VM_L2_STATUS 0x140C 463#define L2_BUSY (1 << 0) 464#define VM_CONTEXT0_CNTL 0x1410 465#define ENABLE_CONTEXT (1 << 0) 466#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 467#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 468#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 469#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 470#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 471#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 472#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 473#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 474#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 475#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 476#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 477#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 478#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 479#define VM_CONTEXT1_CNTL 0x1414 480#define VM_CONTEXT0_CNTL2 0x1430 481#define VM_CONTEXT1_CNTL2 0x1434 482#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 483#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 484#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 485#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 486#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 487#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 488#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 489#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 490 491#define VM_INVALIDATE_REQUEST 0x1478 492#define VM_INVALIDATE_RESPONSE 0x147c 493 494#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 495#define PROTECTIONS_MASK (0xf << 0) 496#define PROTECTIONS_SHIFT 0 497 /* bit 0: range 498 * bit 1: pde0 499 * bit 2: valid 500 * bit 3: read 501 * bit 4: write 502 */ 503#define MEMORY_CLIENT_ID_MASK (0xff << 12) 504#define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12) 505#define MEMORY_CLIENT_ID_SHIFT 12 506#define MEMORY_CLIENT_RW_MASK (1 << 24) 507#define MEMORY_CLIENT_RW_SHIFT 24 508#define FAULT_VMID_MASK (0xf << 25) 509#define FAULT_VMID_SHIFT 25 510 511#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 512 513#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 514 515#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 516#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 517 518#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 519#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 520#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 521#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 522#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 523#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 524#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 525#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 526#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 527#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 528 529#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 530#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 531 532#define VM_L2_CG 0x15c0 533#define MC_CG_ENABLE (1 << 18) 534#define MC_LS_ENABLE (1 << 19) 535 536#define MC_SHARED_CHMAP 0x2004 537#define NOOFCHAN_SHIFT 12 538#define NOOFCHAN_MASK 0x0000f000 539#define MC_SHARED_CHREMAP 0x2008 540 541#define CHUB_CONTROL 0x1864 542#define BYPASS_VM (1 << 0) 543 544#define MC_VM_FB_LOCATION 0x2024 545#define MC_VM_AGP_TOP 0x2028 546#define MC_VM_AGP_BOT 0x202C 547#define MC_VM_AGP_BASE 0x2030 548#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 549#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 550#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 551 552#define MC_VM_MX_L1_TLB_CNTL 0x2064 553#define ENABLE_L1_TLB (1 << 0) 554#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 555#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 556#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 557#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 558#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 559#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 560#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 561#define MC_VM_FB_OFFSET 0x2068 562 563#define MC_SHARED_BLACKOUT_CNTL 0x20ac 564 565#define MC_HUB_MISC_HUB_CG 0x20b8 566#define MC_HUB_MISC_VM_CG 0x20bc 567 568#define MC_HUB_MISC_SIP_CG 0x20c0 569 570#define MC_XPB_CLK_GAT 0x2478 571 572#define MC_CITF_MISC_RD_CG 0x2648 573#define MC_CITF_MISC_WR_CG 0x264c 574#define MC_CITF_MISC_VM_CG 0x2650 575 576#define MC_ARB_RAMCFG 0x2760 577#define NOOFBANK_SHIFT 0 578#define NOOFBANK_MASK 0x00000003 579#define NOOFRANK_SHIFT 2 580#define NOOFRANK_MASK 0x00000004 581#define NOOFROWS_SHIFT 3 582#define NOOFROWS_MASK 0x00000038 583#define NOOFCOLS_SHIFT 6 584#define NOOFCOLS_MASK 0x000000C0 585#define CHANSIZE_SHIFT 8 586#define CHANSIZE_MASK 0x00000100 587#define NOOFGROUPS_SHIFT 12 588#define NOOFGROUPS_MASK 0x00001000 589 590#define MC_ARB_DRAM_TIMING 0x2774 591#define MC_ARB_DRAM_TIMING2 0x2778 592 593#define MC_ARB_BURST_TIME 0x2808 594#define STATE0(x) ((x) << 0) 595#define STATE0_MASK (0x1f << 0) 596#define STATE0_SHIFT 0 597#define STATE1(x) ((x) << 5) 598#define STATE1_MASK (0x1f << 5) 599#define STATE1_SHIFT 5 600#define STATE2(x) ((x) << 10) 601#define STATE2_MASK (0x1f << 10) 602#define STATE2_SHIFT 10 603#define STATE3(x) ((x) << 15) 604#define STATE3_MASK (0x1f << 15) 605#define STATE3_SHIFT 15 606 607#define MC_SEQ_RAS_TIMING 0x28a0 608#define MC_SEQ_CAS_TIMING 0x28a4 609#define MC_SEQ_MISC_TIMING 0x28a8 610#define MC_SEQ_MISC_TIMING2 0x28ac 611#define MC_SEQ_PMG_TIMING 0x28b0 612#define MC_SEQ_RD_CTL_D0 0x28b4 613#define MC_SEQ_RD_CTL_D1 0x28b8 614#define MC_SEQ_WR_CTL_D0 0x28bc 615#define MC_SEQ_WR_CTL_D1 0x28c0 616 617#define MC_SEQ_SUP_CNTL 0x28c8 618#define RUN_MASK (1 << 0) 619#define MC_SEQ_SUP_PGM 0x28cc 620#define MC_PMG_AUTO_CMD 0x28d0 621 622#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 623#define TRAIN_DONE_D0 (1 << 30) 624#define TRAIN_DONE_D1 (1 << 31) 625 626#define MC_IO_PAD_CNTL_D0 0x29d0 627#define MEM_FALL_OUT_CMD (1 << 8) 628 629#define MC_SEQ_MISC0 0x2a00 630#define MC_SEQ_MISC0_VEN_ID_SHIFT 8 631#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 632#define MC_SEQ_MISC0_VEN_ID_VALUE 3 633#define MC_SEQ_MISC0_REV_ID_SHIFT 12 634#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 635#define MC_SEQ_MISC0_REV_ID_VALUE 1 636#define MC_SEQ_MISC0_GDDR5_SHIFT 28 637#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 638#define MC_SEQ_MISC0_GDDR5_VALUE 5 639#define MC_SEQ_MISC1 0x2a04 640#define MC_SEQ_RESERVE_M 0x2a08 641#define MC_PMG_CMD_EMRS 0x2a0c 642 643#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 644#define MC_SEQ_IO_DEBUG_DATA 0x2a48 645 646#define MC_SEQ_MISC5 0x2a54 647#define MC_SEQ_MISC6 0x2a58 648 649#define MC_SEQ_MISC7 0x2a64 650 651#define MC_SEQ_RAS_TIMING_LP 0x2a6c 652#define MC_SEQ_CAS_TIMING_LP 0x2a70 653#define MC_SEQ_MISC_TIMING_LP 0x2a74 654#define MC_SEQ_MISC_TIMING2_LP 0x2a78 655#define MC_SEQ_WR_CTL_D0_LP 0x2a7c 656#define MC_SEQ_WR_CTL_D1_LP 0x2a80 657#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 658#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 659 660#define MC_PMG_CMD_MRS 0x2aac 661 662#define MC_SEQ_RD_CTL_D0_LP 0x2b1c 663#define MC_SEQ_RD_CTL_D1_LP 0x2b20 664 665#define MC_PMG_CMD_MRS1 0x2b44 666#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 667#define MC_SEQ_PMG_TIMING_LP 0x2b4c 668 669#define MC_SEQ_WR_CTL_2 0x2b54 670#define MC_SEQ_WR_CTL_2_LP 0x2b58 671#define MC_PMG_CMD_MRS2 0x2b5c 672#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 673 674#define MCLK_PWRMGT_CNTL 0x2ba0 675# define DLL_SPEED(x) ((x) << 0) 676# define DLL_SPEED_MASK (0x1f << 0) 677# define DLL_READY (1 << 6) 678# define MC_INT_CNTL (1 << 7) 679# define MRDCK0_PDNB (1 << 8) 680# define MRDCK1_PDNB (1 << 9) 681# define MRDCK0_RESET (1 << 16) 682# define MRDCK1_RESET (1 << 17) 683# define DLL_READY_READ (1 << 24) 684#define DLL_CNTL 0x2ba4 685# define MRDCK0_BYPASS (1 << 24) 686# define MRDCK1_BYPASS (1 << 25) 687 688#define MPLL_FUNC_CNTL 0x2bb4 689#define BWCTRL(x) ((x) << 20) 690#define BWCTRL_MASK (0xff << 20) 691#define MPLL_FUNC_CNTL_1 0x2bb8 692#define VCO_MODE(x) ((x) << 0) 693#define VCO_MODE_MASK (3 << 0) 694#define CLKFRAC(x) ((x) << 4) 695#define CLKFRAC_MASK (0xfff << 4) 696#define CLKF(x) ((x) << 16) 697#define CLKF_MASK (0xfff << 16) 698#define MPLL_FUNC_CNTL_2 0x2bbc 699#define MPLL_AD_FUNC_CNTL 0x2bc0 700#define YCLK_POST_DIV(x) ((x) << 0) 701#define YCLK_POST_DIV_MASK (7 << 0) 702#define MPLL_DQ_FUNC_CNTL 0x2bc4 703#define YCLK_SEL(x) ((x) << 4) 704#define YCLK_SEL_MASK (1 << 4) 705 706#define MPLL_SS1 0x2bcc 707#define CLKV(x) ((x) << 0) 708#define CLKV_MASK (0x3ffffff << 0) 709#define MPLL_SS2 0x2bd0 710#define CLKS(x) ((x) << 0) 711#define CLKS_MASK (0xfff << 0) 712 713#define HDP_HOST_PATH_CNTL 0x2C00 714#define CLOCK_GATING_DIS (1 << 23) 715#define HDP_NONSURFACE_BASE 0x2C04 716#define HDP_NONSURFACE_INFO 0x2C08 717#define HDP_NONSURFACE_SIZE 0x2C0C 718 719#define HDP_ADDR_CONFIG 0x2F48 720#define HDP_MISC_CNTL 0x2F4C 721#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 722#define HDP_MEM_POWER_LS 0x2F50 723#define HDP_LS_ENABLE (1 << 0) 724 725#define ATC_MISC_CG 0x3350 726 727#define MC_SEQ_CNTL_3 0x3600 728# define CAC_EN (1 << 31) 729#define MC_SEQ_G5PDX_CTRL 0x3604 730#define MC_SEQ_G5PDX_CTRL_LP 0x3608 731#define MC_SEQ_G5PDX_CMD0 0x360c 732#define MC_SEQ_G5PDX_CMD0_LP 0x3610 733#define MC_SEQ_G5PDX_CMD1 0x3614 734#define MC_SEQ_G5PDX_CMD1_LP 0x3618 735 736#define MC_SEQ_PMG_DVS_CTL 0x3628 737#define MC_SEQ_PMG_DVS_CTL_LP 0x362c 738#define MC_SEQ_PMG_DVS_CMD 0x3630 739#define MC_SEQ_PMG_DVS_CMD_LP 0x3634 740#define MC_SEQ_DLL_STBY 0x3638 741#define MC_SEQ_DLL_STBY_LP 0x363c 742 743#define IH_RB_CNTL 0x3e00 744# define IH_RB_ENABLE (1 << 0) 745# define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 746# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 747# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 748# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 749# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 750# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 751#define IH_RB_BASE 0x3e04 752#define IH_RB_RPTR 0x3e08 753#define IH_RB_WPTR 0x3e0c 754# define RB_OVERFLOW (1 << 0) 755# define WPTR_OFFSET_MASK 0x3fffc 756#define IH_RB_WPTR_ADDR_HI 0x3e10 757#define IH_RB_WPTR_ADDR_LO 0x3e14 758#define IH_CNTL 0x3e18 759# define ENABLE_INTR (1 << 0) 760# define IH_MC_SWAP(x) ((x) << 1) 761# define IH_MC_SWAP_NONE 0 762# define IH_MC_SWAP_16BIT 1 763# define IH_MC_SWAP_32BIT 2 764# define IH_MC_SWAP_64BIT 3 765# define RPTR_REARM (1 << 4) 766# define MC_WRREQ_CREDIT(x) ((x) << 15) 767# define MC_WR_CLEAN_CNT(x) ((x) << 20) 768# define MC_VMID(x) ((x) << 25) 769 770#define BIF_LNCNT_RESET 0x5220 771# define RESET_LNCNT_EN (1 << 0) 772 773#define CONFIG_MEMSIZE 0x5428 774 775#define INTERRUPT_CNTL 0x5468 776# define IH_DUMMY_RD_OVERRIDE (1 << 0) 777# define IH_DUMMY_RD_EN (1 << 1) 778# define IH_REQ_NONSNOOP_EN (1 << 3) 779# define GEN_IH_INT_EN (1 << 8) 780#define INTERRUPT_CNTL2 0x546c 781 782#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 783 784#define BIF_FB_EN 0x5490 785#define FB_READ_EN (1 << 0) 786#define FB_WRITE_EN (1 << 1) 787 788#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 789 790#define GPU_HDP_FLUSH_REQ 0x54DC 791#define GPU_HDP_FLUSH_DONE 0x54E0 792#define CP0 (1 << 0) 793#define CP1 (1 << 1) 794#define CP2 (1 << 2) 795#define CP3 (1 << 3) 796#define CP4 (1 << 4) 797#define CP5 (1 << 5) 798#define CP6 (1 << 6) 799#define CP7 (1 << 7) 800#define CP8 (1 << 8) 801#define CP9 (1 << 9) 802#define SDMA0 (1 << 10) 803#define SDMA1 (1 << 11) 804 805/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 806#define LB_MEMORY_CTRL 0x6b04 807#define LB_MEMORY_SIZE(x) ((x) << 0) 808#define LB_MEMORY_CONFIG(x) ((x) << 20) 809 810#define DPG_WATERMARK_MASK_CONTROL 0x6cc8 811# define LATENCY_WATERMARK_MASK(x) ((x) << 8) 812#define DPG_PIPE_LATENCY_CONTROL 0x6ccc 813# define LATENCY_LOW_WATERMARK(x) ((x) << 0) 814# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 815 816/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 817#define LB_VLINE_STATUS 0x6b24 818# define VLINE_OCCURRED (1 << 0) 819# define VLINE_ACK (1 << 4) 820# define VLINE_STAT (1 << 12) 821# define VLINE_INTERRUPT (1 << 16) 822# define VLINE_INTERRUPT_TYPE (1 << 17) 823/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 824#define LB_VBLANK_STATUS 0x6b2c 825# define VBLANK_OCCURRED (1 << 0) 826# define VBLANK_ACK (1 << 4) 827# define VBLANK_STAT (1 << 12) 828# define VBLANK_INTERRUPT (1 << 16) 829# define VBLANK_INTERRUPT_TYPE (1 << 17) 830 831/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 832#define LB_INTERRUPT_MASK 0x6b20 833# define VBLANK_INTERRUPT_MASK (1 << 0) 834# define VLINE_INTERRUPT_MASK (1 << 4) 835# define VLINE2_INTERRUPT_MASK (1 << 8) 836 837#define DISP_INTERRUPT_STATUS 0x60f4 838# define LB_D1_VLINE_INTERRUPT (1 << 2) 839# define LB_D1_VBLANK_INTERRUPT (1 << 3) 840# define DC_HPD1_INTERRUPT (1 << 17) 841# define DC_HPD1_RX_INTERRUPT (1 << 18) 842# define DACA_AUTODETECT_INTERRUPT (1 << 22) 843# define DACB_AUTODETECT_INTERRUPT (1 << 23) 844# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 845# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 846#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 847# define LB_D2_VLINE_INTERRUPT (1 << 2) 848# define LB_D2_VBLANK_INTERRUPT (1 << 3) 849# define DC_HPD2_INTERRUPT (1 << 17) 850# define DC_HPD2_RX_INTERRUPT (1 << 18) 851# define DISP_TIMER_INTERRUPT (1 << 24) 852#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 853# define LB_D3_VLINE_INTERRUPT (1 << 2) 854# define LB_D3_VBLANK_INTERRUPT (1 << 3) 855# define DC_HPD3_INTERRUPT (1 << 17) 856# define DC_HPD3_RX_INTERRUPT (1 << 18) 857#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 858# define LB_D4_VLINE_INTERRUPT (1 << 2) 859# define LB_D4_VBLANK_INTERRUPT (1 << 3) 860# define DC_HPD4_INTERRUPT (1 << 17) 861# define DC_HPD4_RX_INTERRUPT (1 << 18) 862#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 863# define LB_D5_VLINE_INTERRUPT (1 << 2) 864# define LB_D5_VBLANK_INTERRUPT (1 << 3) 865# define DC_HPD5_INTERRUPT (1 << 17) 866# define DC_HPD5_RX_INTERRUPT (1 << 18) 867#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 868# define LB_D6_VLINE_INTERRUPT (1 << 2) 869# define LB_D6_VBLANK_INTERRUPT (1 << 3) 870# define DC_HPD6_INTERRUPT (1 << 17) 871# define DC_HPD6_RX_INTERRUPT (1 << 18) 872#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 873 874#define DAC_AUTODETECT_INT_CONTROL 0x67c8 875 876#define DC_HPD1_INT_STATUS 0x601c 877#define DC_HPD2_INT_STATUS 0x6028 878#define DC_HPD3_INT_STATUS 0x6034 879#define DC_HPD4_INT_STATUS 0x6040 880#define DC_HPD5_INT_STATUS 0x604c 881#define DC_HPD6_INT_STATUS 0x6058 882# define DC_HPDx_INT_STATUS (1 << 0) 883# define DC_HPDx_SENSE (1 << 1) 884# define DC_HPDx_SENSE_DELAYED (1 << 4) 885# define DC_HPDx_RX_INT_STATUS (1 << 8) 886 887#define DC_HPD1_INT_CONTROL 0x6020 888#define DC_HPD2_INT_CONTROL 0x602c 889#define DC_HPD3_INT_CONTROL 0x6038 890#define DC_HPD4_INT_CONTROL 0x6044 891#define DC_HPD5_INT_CONTROL 0x6050 892#define DC_HPD6_INT_CONTROL 0x605c 893# define DC_HPDx_INT_ACK (1 << 0) 894# define DC_HPDx_INT_POLARITY (1 << 8) 895# define DC_HPDx_INT_EN (1 << 16) 896# define DC_HPDx_RX_INT_ACK (1 << 20) 897# define DC_HPDx_RX_INT_EN (1 << 24) 898 899#define DC_HPD1_CONTROL 0x6024 900#define DC_HPD2_CONTROL 0x6030 901#define DC_HPD3_CONTROL 0x603c 902#define DC_HPD4_CONTROL 0x6048 903#define DC_HPD5_CONTROL 0x6054 904#define DC_HPD6_CONTROL 0x6060 905# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 906# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 907# define DC_HPDx_EN (1 << 28) 908 909#define DPG_PIPE_STUTTER_CONTROL 0x6cd4 910# define STUTTER_ENABLE (1 << 0) 911 912/* DCE8 FMT blocks */ 913#define FMT_DYNAMIC_EXP_CNTL 0x6fb4 914# define FMT_DYNAMIC_EXP_EN (1 << 0) 915# define FMT_DYNAMIC_EXP_MODE (1 << 4) 916 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 917#define FMT_CONTROL 0x6fb8 918# define FMT_PIXEL_ENCODING (1 << 16) 919 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 920#define FMT_BIT_DEPTH_CONTROL 0x6fc8 921# define FMT_TRUNCATE_EN (1 << 0) 922# define FMT_TRUNCATE_MODE (1 << 1) 923# define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 924# define FMT_SPATIAL_DITHER_EN (1 << 8) 925# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 926# define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 927# define FMT_FRAME_RANDOM_ENABLE (1 << 13) 928# define FMT_RGB_RANDOM_ENABLE (1 << 14) 929# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 930# define FMT_TEMPORAL_DITHER_EN (1 << 16) 931# define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 932# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 933# define FMT_TEMPORAL_LEVEL (1 << 24) 934# define FMT_TEMPORAL_DITHER_RESET (1 << 25) 935# define FMT_25FRC_SEL(x) ((x) << 26) 936# define FMT_50FRC_SEL(x) ((x) << 28) 937# define FMT_75FRC_SEL(x) ((x) << 30) 938#define FMT_CLAMP_CONTROL 0x6fe4 939# define FMT_CLAMP_DATA_EN (1 << 0) 940# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 941# define FMT_CLAMP_6BPC 0 942# define FMT_CLAMP_8BPC 1 943# define FMT_CLAMP_10BPC 2 944 945#define GRBM_CNTL 0x8000 946#define GRBM_READ_TIMEOUT(x) ((x) << 0) 947 948#define GRBM_STATUS2 0x8008 949#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 950#define ME0PIPE1_CF_RQ_PENDING (1 << 4) 951#define ME0PIPE1_PF_RQ_PENDING (1 << 5) 952#define ME1PIPE0_RQ_PENDING (1 << 6) 953#define ME1PIPE1_RQ_PENDING (1 << 7) 954#define ME1PIPE2_RQ_PENDING (1 << 8) 955#define ME1PIPE3_RQ_PENDING (1 << 9) 956#define ME2PIPE0_RQ_PENDING (1 << 10) 957#define ME2PIPE1_RQ_PENDING (1 << 11) 958#define ME2PIPE2_RQ_PENDING (1 << 12) 959#define ME2PIPE3_RQ_PENDING (1 << 13) 960#define RLC_RQ_PENDING (1 << 14) 961#define RLC_BUSY (1 << 24) 962#define TC_BUSY (1 << 25) 963#define CPF_BUSY (1 << 28) 964#define CPC_BUSY (1 << 29) 965#define CPG_BUSY (1 << 30) 966 967#define GRBM_STATUS 0x8010 968#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 969#define SRBM_RQ_PENDING (1 << 5) 970#define ME0PIPE0_CF_RQ_PENDING (1 << 7) 971#define ME0PIPE0_PF_RQ_PENDING (1 << 8) 972#define GDS_DMA_RQ_PENDING (1 << 9) 973#define DB_CLEAN (1 << 12) 974#define CB_CLEAN (1 << 13) 975#define TA_BUSY (1 << 14) 976#define GDS_BUSY (1 << 15) 977#define WD_BUSY_NO_DMA (1 << 16) 978#define VGT_BUSY (1 << 17) 979#define IA_BUSY_NO_DMA (1 << 18) 980#define IA_BUSY (1 << 19) 981#define SX_BUSY (1 << 20) 982#define WD_BUSY (1 << 21) 983#define SPI_BUSY (1 << 22) 984#define BCI_BUSY (1 << 23) 985#define SC_BUSY (1 << 24) 986#define PA_BUSY (1 << 25) 987#define DB_BUSY (1 << 26) 988#define CP_COHERENCY_BUSY (1 << 28) 989#define CP_BUSY (1 << 29) 990#define CB_BUSY (1 << 30) 991#define GUI_ACTIVE (1 << 31) 992#define GRBM_STATUS_SE0 0x8014 993#define GRBM_STATUS_SE1 0x8018 994#define GRBM_STATUS_SE2 0x8038 995#define GRBM_STATUS_SE3 0x803C 996#define SE_DB_CLEAN (1 << 1) 997#define SE_CB_CLEAN (1 << 2) 998#define SE_BCI_BUSY (1 << 22) 999#define SE_VGT_BUSY (1 << 23) 1000#define SE_PA_BUSY (1 << 24)
1001#define SE_TA_BUSY (1 << 25) 1002#define SE_SX_BUSY (1 << 26) 1003#define SE_SPI_BUSY (1 << 27) 1004#define SE_SC_BUSY (1 << 29) 1005#define SE_DB_BUSY (1 << 30) 1006#define SE_CB_BUSY (1 << 31) 1007 1008#define GRBM_SOFT_RESET 0x8020 1009#define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 1010#define SOFT_RESET_RLC (1 << 2) /* RLC */ 1011#define SOFT_RESET_GFX (1 << 16) /* GFX */ 1012#define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 1013#define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 1014#define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 1015 1016#define GRBM_INT_CNTL 0x8060 1017# define RDERR_INT_ENABLE (1 << 0) 1018# define GUI_IDLE_INT_ENABLE (1 << 19) 1019 1020#define CP_CPC_STATUS 0x8210 1021#define CP_CPC_BUSY_STAT 0x8214 1022#define CP_CPC_STALLED_STAT1 0x8218 1023#define CP_CPF_STATUS 0x821c 1024#define CP_CPF_BUSY_STAT 0x8220 1025#define CP_CPF_STALLED_STAT1 0x8224 1026 1027#define CP_MEC_CNTL 0x8234 1028#define MEC_ME2_HALT (1 << 28) 1029#define MEC_ME1_HALT (1 << 30) 1030 1031#define CP_MEC_CNTL 0x8234 1032#define MEC_ME2_HALT (1 << 28) 1033#define MEC_ME1_HALT (1 << 30) 1034 1035#define CP_STALLED_STAT3 0x8670 1036#define CP_STALLED_STAT1 0x8674 1037#define CP_STALLED_STAT2 0x8678 1038 1039#define CP_STAT 0x8680 1040 1041#define CP_ME_CNTL 0x86D8 1042#define CP_CE_HALT (1 << 24) 1043#define CP_PFP_HALT (1 << 26) 1044#define CP_ME_HALT (1 << 28) 1045 1046#define CP_RB0_RPTR 0x8700 1047#define CP_RB_WPTR_DELAY 0x8704 1048#define CP_RB_WPTR_POLL_CNTL 0x8708 1049#define IDLE_POLL_COUNT(x) ((x) << 16) 1050#define IDLE_POLL_COUNT_MASK (0xffff << 16) 1051 1052#define CP_MEQ_THRESHOLDS 0x8764 1053#define MEQ1_START(x) ((x) << 0) 1054#define MEQ2_START(x) ((x) << 8) 1055 1056#define VGT_VTX_VECT_EJECT_REG 0x88B0 1057 1058#define VGT_CACHE_INVALIDATION 0x88C4 1059#define CACHE_INVALIDATION(x) ((x) << 0) 1060#define VC_ONLY 0 1061#define TC_ONLY 1 1062#define VC_AND_TC 2 1063#define AUTO_INVLD_EN(x) ((x) << 6) 1064#define NO_AUTO 0 1065#define ES_AUTO 1 1066#define GS_AUTO 2 1067#define ES_AND_GS_AUTO 3 1068 1069#define VGT_GS_VERTEX_REUSE 0x88D4 1070 1071#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 1072#define INACTIVE_CUS_MASK 0xFFFF0000 1073#define INACTIVE_CUS_SHIFT 16 1074#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 1075 1076#define PA_CL_ENHANCE 0x8A14 1077#define CLIP_VTX_REORDER_ENA (1 << 0) 1078#define NUM_CLIP_SEQ(x) ((x) << 1) 1079 1080#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 1081#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1082#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1083 1084#define PA_SC_FIFO_SIZE 0x8BCC 1085#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 1086#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1087#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1088#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1089 1090#define PA_SC_ENHANCE 0x8BF0 1091#define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 1092#define DISABLE_PA_SC_GUIDANCE (1 << 13) 1093 1094#define SQ_CONFIG 0x8C00 1095 1096#define SH_MEM_BASES 0x8C28 1097/* if PTR32, these are the bases for scratch and lds */ 1098#define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 1099#define SHARED_BASE(x) ((x) << 16) /* LDS */ 1100#define SH_MEM_APE1_BASE 0x8C2C 1101/* if PTR32, this is the base location of GPUVM */ 1102#define SH_MEM_APE1_LIMIT 0x8C30 1103/* if PTR32, this is the upper limit of GPUVM */ 1104#define SH_MEM_CONFIG 0x8C34 1105#define PTR32 (1 << 0) 1106#define ALIGNMENT_MODE(x) ((x) << 2) 1107#define SH_MEM_ALIGNMENT_MODE_DWORD 0 1108#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 1109#define SH_MEM_ALIGNMENT_MODE_STRICT 2 1110#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 1111#define DEFAULT_MTYPE(x) ((x) << 4) 1112#define APE1_MTYPE(x) ((x) << 7) 1113 1114#define SX_DEBUG_1 0x9060 1115 1116#define SPI_CONFIG_CNTL 0x9100 1117 1118#define SPI_CONFIG_CNTL_1 0x913C 1119#define VTX_DONE_DELAY(x) ((x) << 0) 1120#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1121 1122#define TA_CNTL_AUX 0x9508 1123 1124#define DB_DEBUG 0x9830 1125#define DB_DEBUG2 0x9834 1126#define DB_DEBUG3 0x9838 1127 1128#define CC_RB_BACKEND_DISABLE 0x98F4 1129#define BACKEND_DISABLE(x) ((x) << 16) 1130#define GB_ADDR_CONFIG 0x98F8 1131#define NUM_PIPES(x) ((x) << 0) 1132#define NUM_PIPES_MASK 0x00000007 1133#define NUM_PIPES_SHIFT 0 1134#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1135#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1136#define PIPE_INTERLEAVE_SIZE_SHIFT 4 1137#define NUM_SHADER_ENGINES(x) ((x) << 12) 1138#define NUM_SHADER_ENGINES_MASK 0x00003000 1139#define NUM_SHADER_ENGINES_SHIFT 12 1140#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1141#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1142#define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1143#define ROW_SIZE(x) ((x) << 28) 1144#define ROW_SIZE_MASK 0x30000000 1145#define ROW_SIZE_SHIFT 28 1146 1147#define GB_TILE_MODE0 0x9910 1148# define ARRAY_MODE(x) ((x) << 2) 1149# define ARRAY_LINEAR_GENERAL 0 1150# define ARRAY_LINEAR_ALIGNED 1 1151# define ARRAY_1D_TILED_THIN1 2 1152# define ARRAY_2D_TILED_THIN1 4 1153# define ARRAY_PRT_TILED_THIN1 5 1154# define ARRAY_PRT_2D_TILED_THIN1 6 1155# define PIPE_CONFIG(x) ((x) << 6) 1156# define ADDR_SURF_P2 0 1157# define ADDR_SURF_P4_8x16 4 1158# define ADDR_SURF_P4_16x16 5 1159# define ADDR_SURF_P4_16x32 6 1160# define ADDR_SURF_P4_32x32 7 1161# define ADDR_SURF_P8_16x16_8x16 8 1162# define ADDR_SURF_P8_16x32_8x16 9 1163# define ADDR_SURF_P8_32x32_8x16 10 1164# define ADDR_SURF_P8_16x32_16x16 11 1165# define ADDR_SURF_P8_32x32_16x16 12 1166# define ADDR_SURF_P8_32x32_16x32 13 1167# define ADDR_SURF_P8_32x64_32x32 14 1168# define ADDR_SURF_P16_32x32_8x16 16 1169# define ADDR_SURF_P16_32x32_16x16 17 1170# define TILE_SPLIT(x) ((x) << 11) 1171# define ADDR_SURF_TILE_SPLIT_64B 0 1172# define ADDR_SURF_TILE_SPLIT_128B 1 1173# define ADDR_SURF_TILE_SPLIT_256B 2 1174# define ADDR_SURF_TILE_SPLIT_512B 3 1175# define ADDR_SURF_TILE_SPLIT_1KB 4 1176# define ADDR_SURF_TILE_SPLIT_2KB 5 1177# define ADDR_SURF_TILE_SPLIT_4KB 6 1178# define MICRO_TILE_MODE_NEW(x) ((x) << 22) 1179# define ADDR_SURF_DISPLAY_MICRO_TILING 0 1180# define ADDR_SURF_THIN_MICRO_TILING 1 1181# define ADDR_SURF_DEPTH_MICRO_TILING 2 1182# define ADDR_SURF_ROTATED_MICRO_TILING 3 1183# define SAMPLE_SPLIT(x) ((x) << 25) 1184# define ADDR_SURF_SAMPLE_SPLIT_1 0 1185# define ADDR_SURF_SAMPLE_SPLIT_2 1 1186# define ADDR_SURF_SAMPLE_SPLIT_4 2 1187# define ADDR_SURF_SAMPLE_SPLIT_8 3 1188 1189#define GB_MACROTILE_MODE0 0x9990 1190# define BANK_WIDTH(x) ((x) << 0) 1191# define ADDR_SURF_BANK_WIDTH_1 0 1192# define ADDR_SURF_BANK_WIDTH_2 1 1193# define ADDR_SURF_BANK_WIDTH_4 2 1194# define ADDR_SURF_BANK_WIDTH_8 3 1195# define BANK_HEIGHT(x) ((x) << 2) 1196# define ADDR_SURF_BANK_HEIGHT_1 0 1197# define ADDR_SURF_BANK_HEIGHT_2 1 1198# define ADDR_SURF_BANK_HEIGHT_4 2 1199# define ADDR_SURF_BANK_HEIGHT_8 3 1200# define MACRO_TILE_ASPECT(x) ((x) << 4) 1201# define ADDR_SURF_MACRO_ASPECT_1 0 1202# define ADDR_SURF_MACRO_ASPECT_2 1 1203# define ADDR_SURF_MACRO_ASPECT_4 2 1204# define ADDR_SURF_MACRO_ASPECT_8 3 1205# define NUM_BANKS(x) ((x) << 6) 1206# define ADDR_SURF_2_BANK 0 1207# define ADDR_SURF_4_BANK 1 1208# define ADDR_SURF_8_BANK 2 1209# define ADDR_SURF_16_BANK 3 1210 1211#define CB_HW_CONTROL 0x9A10 1212 1213#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 1214#define BACKEND_DISABLE_MASK 0x00FF0000 1215#define BACKEND_DISABLE_SHIFT 16 1216 1217#define TCP_CHAN_STEER_LO 0xac0c 1218#define TCP_CHAN_STEER_HI 0xac10 1219 1220#define TC_CFG_L1_LOAD_POLICY0 0xAC68 1221#define TC_CFG_L1_LOAD_POLICY1 0xAC6C 1222#define TC_CFG_L1_STORE_POLICY 0xAC70 1223#define TC_CFG_L2_LOAD_POLICY0 0xAC74 1224#define TC_CFG_L2_LOAD_POLICY1 0xAC78 1225#define TC_CFG_L2_STORE_POLICY0 0xAC7C 1226#define TC_CFG_L2_STORE_POLICY1 0xAC80 1227#define TC_CFG_L2_ATOMIC_POLICY 0xAC84 1228#define TC_CFG_L1_VOLATILE 0xAC88 1229#define TC_CFG_L2_VOLATILE 0xAC8C 1230 1231#define CP_RB0_BASE 0xC100 1232#define CP_RB0_CNTL 0xC104 1233#define RB_BUFSZ(x) ((x) << 0) 1234#define RB_BLKSZ(x) ((x) << 8) 1235#define BUF_SWAP_32BIT (2 << 16) 1236#define RB_NO_UPDATE (1 << 27) 1237#define RB_RPTR_WR_ENA (1 << 31) 1238 1239#define CP_RB0_RPTR_ADDR 0xC10C 1240#define RB_RPTR_SWAP_32BIT (2 << 0) 1241#define CP_RB0_RPTR_ADDR_HI 0xC110 1242#define CP_RB0_WPTR 0xC114 1243 1244#define CP_DEVICE_ID 0xC12C 1245#define CP_ENDIAN_SWAP 0xC140 1246#define CP_RB_VMID 0xC144 1247 1248#define CP_PFP_UCODE_ADDR 0xC150 1249#define CP_PFP_UCODE_DATA 0xC154 1250#define CP_ME_RAM_RADDR 0xC158 1251#define CP_ME_RAM_WADDR 0xC15C 1252#define CP_ME_RAM_DATA 0xC160 1253 1254#define CP_CE_UCODE_ADDR 0xC168 1255#define CP_CE_UCODE_DATA 0xC16C 1256#define CP_MEC_ME1_UCODE_ADDR 0xC170 1257#define CP_MEC_ME1_UCODE_DATA 0xC174 1258#define CP_MEC_ME2_UCODE_ADDR 0xC178 1259#define CP_MEC_ME2_UCODE_DATA 0xC17C 1260 1261#define CP_INT_CNTL_RING0 0xC1A8 1262# define CNTX_BUSY_INT_ENABLE (1 << 19) 1263# define CNTX_EMPTY_INT_ENABLE (1 << 20) 1264# define PRIV_INSTR_INT_ENABLE (1 << 22) 1265# define PRIV_REG_INT_ENABLE (1 << 23) 1266# define TIME_STAMP_INT_ENABLE (1 << 26) 1267# define CP_RINGID2_INT_ENABLE (1 << 29) 1268# define CP_RINGID1_INT_ENABLE (1 << 30) 1269# define CP_RINGID0_INT_ENABLE (1 << 31) 1270 1271#define CP_INT_STATUS_RING0 0xC1B4 1272# define PRIV_INSTR_INT_STAT (1 << 22) 1273# define PRIV_REG_INT_STAT (1 << 23) 1274# define TIME_STAMP_INT_STAT (1 << 26) 1275# define CP_RINGID2_INT_STAT (1 << 29) 1276# define CP_RINGID1_INT_STAT (1 << 30) 1277# define CP_RINGID0_INT_STAT (1 << 31) 1278 1279#define CP_MEM_SLP_CNTL 0xC1E4 1280# define CP_MEM_LS_EN (1 << 0) 1281 1282#define CP_CPF_DEBUG 0xC200 1283 1284#define CP_PQ_WPTR_POLL_CNTL 0xC20C 1285#define WPTR_POLL_EN (1 << 31) 1286 1287#define CP_ME1_PIPE0_INT_CNTL 0xC214 1288#define CP_ME1_PIPE1_INT_CNTL 0xC218 1289#define CP_ME1_PIPE2_INT_CNTL 0xC21C 1290#define CP_ME1_PIPE3_INT_CNTL 0xC220 1291#define CP_ME2_PIPE0_INT_CNTL 0xC224 1292#define CP_ME2_PIPE1_INT_CNTL 0xC228 1293#define CP_ME2_PIPE2_INT_CNTL 0xC22C 1294#define CP_ME2_PIPE3_INT_CNTL 0xC230 1295# define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 1296# define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 1297# define PRIV_REG_INT_ENABLE (1 << 23) 1298# define TIME_STAMP_INT_ENABLE (1 << 26) 1299# define GENERIC2_INT_ENABLE (1 << 29) 1300# define GENERIC1_INT_ENABLE (1 << 30) 1301# define GENERIC0_INT_ENABLE (1 << 31) 1302#define CP_ME1_PIPE0_INT_STATUS 0xC214 1303#define CP_ME1_PIPE1_INT_STATUS 0xC218 1304#define CP_ME1_PIPE2_INT_STATUS 0xC21C 1305#define CP_ME1_PIPE3_INT_STATUS 0xC220 1306#define CP_ME2_PIPE0_INT_STATUS 0xC224 1307#define CP_ME2_PIPE1_INT_STATUS 0xC228 1308#define CP_ME2_PIPE2_INT_STATUS 0xC22C 1309#define CP_ME2_PIPE3_INT_STATUS 0xC230 1310# define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 1311# define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 1312# define PRIV_REG_INT_STATUS (1 << 23) 1313# define TIME_STAMP_INT_STATUS (1 << 26) 1314# define GENERIC2_INT_STATUS (1 << 29) 1315# define GENERIC1_INT_STATUS (1 << 30) 1316# define GENERIC0_INT_STATUS (1 << 31) 1317 1318#define CP_MAX_CONTEXT 0xC2B8 1319 1320#define CP_RB0_BASE_HI 0xC2C4 1321 1322#define RLC_CNTL 0xC300 1323# define RLC_ENABLE (1 << 0) 1324 1325#define RLC_MC_CNTL 0xC30C 1326 1327#define RLC_MEM_SLP_CNTL 0xC318 1328# define RLC_MEM_LS_EN (1 << 0) 1329 1330#define RLC_LB_CNTR_MAX 0xC348 1331 1332#define RLC_LB_CNTL 0xC364 1333# define LOAD_BALANCE_ENABLE (1 << 0) 1334 1335#define RLC_LB_CNTR_INIT 0xC36C 1336 1337#define RLC_SAVE_AND_RESTORE_BASE 0xC374 1338#define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 1339#define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 1340#define RLC_PG_DELAY_2 0xC37C 1341 1342#define RLC_GPM_UCODE_ADDR 0xC388 1343#define RLC_GPM_UCODE_DATA 0xC38C 1344#define RLC_GPU_CLOCK_COUNT_LSB 0xC390 1345#define RLC_GPU_CLOCK_COUNT_MSB 0xC394 1346#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 1347#define RLC_UCODE_CNTL 0xC39C 1348 1349#define RLC_GPM_STAT 0xC400 1350# define RLC_GPM_BUSY (1 << 0) 1351# define GFX_POWER_STATUS (1 << 1) 1352# define GFX_CLOCK_STATUS (1 << 2) 1353 1354#define RLC_PG_CNTL 0xC40C 1355# define GFX_PG_ENABLE (1 << 0) 1356# define GFX_PG_SRC (1 << 1) 1357# define DYN_PER_CU_PG_ENABLE (1 << 2) 1358# define STATIC_PER_CU_PG_ENABLE (1 << 3) 1359# define DISABLE_GDS_PG (1 << 13) 1360# define DISABLE_CP_PG (1 << 15) 1361# define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 1362# define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 1363 1364#define RLC_CGTT_MGCG_OVERRIDE 0xC420 1365#define RLC_CGCG_CGLS_CTRL 0xC424 1366# define CGCG_EN (1 << 0) 1367# define CGLS_EN (1 << 1) 1368 1369#define RLC_PG_DELAY 0xC434 1370 1371#define RLC_LB_INIT_CU_MASK 0xC43C 1372 1373#define RLC_LB_PARAMS 0xC444 1374 1375#define RLC_PG_AO_CU_MASK 0xC44C 1376 1377#define RLC_MAX_PG_CU 0xC450 1378# define MAX_PU_CU(x) ((x) << 0) 1379# define MAX_PU_CU_MASK (0xff << 0) 1380#define RLC_AUTO_PG_CTRL 0xC454 1381# define AUTO_PG_EN (1 << 0) 1382# define GRBM_REG_SGIT(x) ((x) << 3) 1383# define GRBM_REG_SGIT_MASK (0xffff << 3) 1384 1385#define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 1386#define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 1387#define RLC_SERDES_WR_CTRL 0xC47C 1388#define BPM_ADDR(x) ((x) << 0) 1389#define BPM_ADDR_MASK (0xff << 0) 1390#define CGLS_ENABLE (1 << 16) 1391#define CGCG_OVERRIDE_0 (1 << 20) 1392#define MGCG_OVERRIDE_0 (1 << 22) 1393#define MGCG_OVERRIDE_1 (1 << 23) 1394 1395#define RLC_SERDES_CU_MASTER_BUSY 0xC484 1396#define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 1397# define SE_MASTER_BUSY_MASK 0x0000ffff 1398# define GC_MASTER_BUSY (1 << 16) 1399# define TC0_MASTER_BUSY (1 << 17) 1400# define TC1_MASTER_BUSY (1 << 18) 1401 1402#define RLC_GPM_SCRATCH_ADDR 0xC4B0 1403#define RLC_GPM_SCRATCH_DATA 0xC4B4 1404 1405#define RLC_GPR_REG2 0xC4E8 1406#define REQ 0x00000001 1407#define MESSAGE(x) ((x) << 1) 1408#define MESSAGE_MASK 0x0000001e 1409#define MSG_ENTER_RLC_SAFE_MODE 1 1410#define MSG_EXIT_RLC_SAFE_MODE 0 1411 1412#define CP_HPD_EOP_BASE_ADDR 0xC904 1413#define CP_HPD_EOP_BASE_ADDR_HI 0xC908 1414#define CP_HPD_EOP_VMID 0xC90C 1415#define CP_HPD_EOP_CONTROL 0xC910 1416#define EOP_SIZE(x) ((x) << 0) 1417#define EOP_SIZE_MASK (0x3f << 0) 1418#define CP_MQD_BASE_ADDR 0xC914 1419#define CP_MQD_BASE_ADDR_HI 0xC918 1420#define CP_HQD_ACTIVE 0xC91C 1421#define CP_HQD_VMID 0xC920 1422 1423#define CP_HQD_PQ_BASE 0xC934 1424#define CP_HQD_PQ_BASE_HI 0xC938 1425#define CP_HQD_PQ_RPTR 0xC93C 1426#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 1427#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 1428#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 1429#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 1430#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 1431#define DOORBELL_OFFSET(x) ((x) << 2) 1432#define DOORBELL_OFFSET_MASK (0x1fffff << 2) 1433#define DOORBELL_SOURCE (1 << 28) 1434#define DOORBELL_SCHD_HIT (1 << 29) 1435#define DOORBELL_EN (1 << 30) 1436#define DOORBELL_HIT (1 << 31) 1437#define CP_HQD_PQ_WPTR 0xC954 1438#define CP_HQD_PQ_CONTROL 0xC958 1439#define QUEUE_SIZE(x) ((x) << 0) 1440#define QUEUE_SIZE_MASK (0x3f << 0) 1441#define RPTR_BLOCK_SIZE(x) ((x) << 8) 1442#define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 1443#define PQ_VOLATILE (1 << 26) 1444#define NO_UPDATE_RPTR (1 << 27) 1445#define UNORD_DISPATCH (1 << 28) 1446#define ROQ_PQ_IB_FLIP (1 << 29) 1447#define PRIV_STATE (1 << 30) 1448#define KMD_QUEUE (1 << 31) 1449 1450#define CP_HQD_DEQUEUE_REQUEST 0xC974 1451 1452#define CP_MQD_CONTROL 0xC99C 1453#define MQD_VMID(x) ((x) << 0) 1454#define MQD_VMID_MASK (0xf << 0) 1455 1456#define DB_RENDER_CONTROL 0x28000 1457 1458#define PA_SC_RASTER_CONFIG 0x28350 1459# define RASTER_CONFIG_RB_MAP_0 0 1460# define RASTER_CONFIG_RB_MAP_1 1 1461# define RASTER_CONFIG_RB_MAP_2 2 1462# define RASTER_CONFIG_RB_MAP_3 3 1463#define PKR_MAP(x) ((x) << 8) 1464 1465#define VGT_EVENT_INITIATOR 0x28a90 1466# define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1467# define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1468# define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1469# define CACHE_FLUSH_TS (4 << 0) 1470# define CACHE_FLUSH (6 << 0) 1471# define CS_PARTIAL_FLUSH (7 << 0) 1472# define VGT_STREAMOUT_RESET (10 << 0) 1473# define END_OF_PIPE_INCR_DE (11 << 0) 1474# define END_OF_PIPE_IB_END (12 << 0) 1475# define RST_PIX_CNT (13 << 0) 1476# define VS_PARTIAL_FLUSH (15 << 0) 1477# define PS_PARTIAL_FLUSH (16 << 0) 1478# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1479# define ZPASS_DONE (21 << 0) 1480# define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1481# define PERFCOUNTER_START (23 << 0) 1482# define PERFCOUNTER_STOP (24 << 0) 1483# define PIPELINESTAT_START (25 << 0) 1484# define PIPELINESTAT_STOP (26 << 0) 1485# define PERFCOUNTER_SAMPLE (27 << 0) 1486# define SAMPLE_PIPELINESTAT (30 << 0) 1487# define SO_VGT_STREAMOUT_FLUSH (31 << 0) 1488# define SAMPLE_STREAMOUTSTATS (32 << 0) 1489# define RESET_VTX_CNT (33 << 0) 1490# define VGT_FLUSH (36 << 0) 1491# define BOTTOM_OF_PIPE_TS (40 << 0) 1492# define DB_CACHE_FLUSH_AND_INV (42 << 0) 1493# define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1494# define FLUSH_AND_INV_DB_META (44 << 0) 1495# define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1496# define FLUSH_AND_INV_CB_META (46 << 0) 1497# define CS_DONE (47 << 0) 1498# define PS_DONE (48 << 0) 1499# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1500# define THREAD_TRACE_START (51 << 0) 1501# define THREAD_TRACE_STOP (52 << 0) 1502# define THREAD_TRACE_FLUSH (54 << 0) 1503# define THREAD_TRACE_FINISH (55 << 0) 1504# define PIXEL_PIPE_STAT_CONTROL (56 << 0) 1505# define PIXEL_PIPE_STAT_DUMP (57 << 0) 1506# define PIXEL_PIPE_STAT_RESET (58 << 0) 1507 1508#define SCRATCH_REG0 0x30100 1509#define SCRATCH_REG1 0x30104 1510#define SCRATCH_REG2 0x30108 1511#define SCRATCH_REG3 0x3010C 1512#define SCRATCH_REG4 0x30110 1513#define SCRATCH_REG5 0x30114 1514#define SCRATCH_REG6 0x30118 1515#define SCRATCH_REG7 0x3011C 1516 1517#define SCRATCH_UMSK 0x30140 1518#define SCRATCH_ADDR 0x30144 1519 1520#define CP_SEM_WAIT_TIMER 0x301BC 1521 1522#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 1523 1524#define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 1525 1526#define GRBM_GFX_INDEX 0x30800 1527#define INSTANCE_INDEX(x) ((x) << 0) 1528#define SH_INDEX(x) ((x) << 8) 1529#define SE_INDEX(x) ((x) << 16) 1530#define SH_BROADCAST_WRITES (1 << 29) 1531#define INSTANCE_BROADCAST_WRITES (1 << 30) 1532#define SE_BROADCAST_WRITES (1 << 31) 1533 1534#define VGT_ESGS_RING_SIZE 0x30900 1535#define VGT_GSVS_RING_SIZE 0x30904 1536#define VGT_PRIMITIVE_TYPE 0x30908 1537#define VGT_INDEX_TYPE 0x3090C 1538 1539#define VGT_NUM_INDICES 0x30930 1540#define VGT_NUM_INSTANCES 0x30934 1541#define VGT_TF_RING_SIZE 0x30938 1542#define VGT_HS_OFFCHIP_PARAM 0x3093C 1543#define VGT_TF_MEMORY_BASE 0x30940 1544 1545#define PA_SU_LINE_STIPPLE_VALUE 0x30a00 1546#define PA_SC_LINE_STIPPLE_STATE 0x30a04 1547 1548#define SQC_CACHES 0x30d20 1549 1550#define CP_PERFMON_CNTL 0x36020 1551 1552#define CGTS_SM_CTRL_REG 0x3c000 1553#define SM_MODE(x) ((x) << 17) 1554#define SM_MODE_MASK (0x7 << 17) 1555#define SM_MODE_ENABLE (1 << 20) 1556#define CGTS_OVERRIDE (1 << 21) 1557#define CGTS_LS_OVERRIDE (1 << 22) 1558#define ON_MONITOR_ADD_EN (1 << 23) 1559#define ON_MONITOR_ADD(x) ((x) << 24) 1560#define ON_MONITOR_ADD_MASK (0xff << 24) 1561 1562#define CGTS_TCC_DISABLE 0x3c00c 1563#define CGTS_USER_TCC_DISABLE 0x3c010 1564#define TCC_DISABLE_MASK 0xFFFF0000 1565#define TCC_DISABLE_SHIFT 16 1566 1567#define CB_CGTT_SCLK_CTRL 0x3c2a0 1568 1569/* 1570 * PM4 1571 */ 1572#define PACKET_TYPE0 0 1573#define PACKET_TYPE1 1 1574#define PACKET_TYPE2 2 1575#define PACKET_TYPE3 3 1576 1577#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1578#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1579#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1580#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1581#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1582 (((reg) >> 2) & 0xFFFF) | \ 1583 ((n) & 0x3FFF) << 16) 1584#define CP_PACKET2 0x80000000 1585#define PACKET2_PAD_SHIFT 0 1586#define PACKET2_PAD_MASK (0x3fffffff << 0) 1587 1588#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1589 1590#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1591 (((op) & 0xFF) << 8) | \ 1592 ((n) & 0x3FFF) << 16) 1593 1594#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1595 1596/* Packet 3 types */ 1597#define PACKET3_NOP 0x10 1598#define PACKET3_SET_BASE 0x11 1599#define PACKET3_BASE_INDEX(x) ((x) << 0) 1600#define CE_PARTITION_BASE 3 1601#define PACKET3_CLEAR_STATE 0x12 1602#define PACKET3_INDEX_BUFFER_SIZE 0x13 1603#define PACKET3_DISPATCH_DIRECT 0x15 1604#define PACKET3_DISPATCH_INDIRECT 0x16 1605#define PACKET3_ATOMIC_GDS 0x1D 1606#define PACKET3_ATOMIC_MEM 0x1E 1607#define PACKET3_OCCLUSION_QUERY 0x1F 1608#define PACKET3_SET_PREDICATION 0x20 1609#define PACKET3_REG_RMW 0x21 1610#define PACKET3_COND_EXEC 0x22 1611#define PACKET3_PRED_EXEC 0x23 1612#define PACKET3_DRAW_INDIRECT 0x24 1613#define PACKET3_DRAW_INDEX_INDIRECT 0x25 1614#define PACKET3_INDEX_BASE 0x26 1615#define PACKET3_DRAW_INDEX_2 0x27 1616#define PACKET3_CONTEXT_CONTROL 0x28 1617#define PACKET3_INDEX_TYPE 0x2A 1618#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1619#define PACKET3_DRAW_INDEX_AUTO 0x2D 1620#define PACKET3_NUM_INSTANCES 0x2F 1621#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1622#define PACKET3_INDIRECT_BUFFER_CONST 0x33 1623#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1624#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1625#define PACKET3_DRAW_PREAMBLE 0x36 1626#define PACKET3_WRITE_DATA 0x37 1627#define WRITE_DATA_DST_SEL(x) ((x) << 8) 1628 /* 0 - register 1629 * 1 - memory (sync - via GRBM) 1630 * 2 - gl2 1631 * 3 - gds 1632 * 4 - reserved 1633 * 5 - memory (async - direct) 1634 */ 1635#define WR_ONE_ADDR (1 << 16) 1636#define WR_CONFIRM (1 << 20) 1637#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 1638 /* 0 - LRU 1639 * 1 - Stream 1640 */ 1641#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1642 /* 0 - me 1643 * 1 - pfp 1644 * 2 - ce 1645 */ 1646#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1647#define PACKET3_MEM_SEMAPHORE 0x39 1648# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 1649# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 1650# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 1651# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1652# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1653#define PACKET3_COPY_DW 0x3B 1654#define PACKET3_WAIT_REG_MEM 0x3C 1655#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1656 /* 0 - always 1657 * 1 - < 1658 * 2 - <= 1659 * 3 - == 1660 * 4 - != 1661 * 5 - >= 1662 * 6 - > 1663 */ 1664#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1665 /* 0 - reg 1666 * 1 - mem 1667 */ 1668#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 1669 /* 0 - wait_reg_mem 1670 * 1 - wr_wait_wr_reg 1671 */ 1672#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1673 /* 0 - me 1674 * 1 - pfp 1675 */ 1676#define PACKET3_INDIRECT_BUFFER 0x3F 1677#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 1678#define INDIRECT_BUFFER_VALID (1 << 23) 1679#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 1680 /* 0 - LRU 1681 * 1 - Stream 1682 * 2 - Bypass 1683 */ 1684#define PACKET3_COPY_DATA 0x40 1685#define PACKET3_PFP_SYNC_ME 0x42 1686#define PACKET3_SURFACE_SYNC 0x43 1687# define PACKET3_DEST_BASE_0_ENA (1 << 0) 1688# define PACKET3_DEST_BASE_1_ENA (1 << 1) 1689# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1690# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1691# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1692# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1693# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1694# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1695# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1696# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1697# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1698# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1699# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1700# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1701# define PACKET3_DEST_BASE_2_ENA (1 << 19) 1702# define PACKET3_DEST_BASE_3_ENA (1 << 21) 1703# define PACKET3_TCL1_ACTION_ENA (1 << 22) 1704# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1705# define PACKET3_CB_ACTION_ENA (1 << 25) 1706# define PACKET3_DB_ACTION_ENA (1 << 26) 1707# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1708# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1709# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1710#define PACKET3_COND_WRITE 0x45 1711#define PACKET3_EVENT_WRITE 0x46 1712#define EVENT_TYPE(x) ((x) << 0) 1713#define EVENT_INDEX(x) ((x) << 8) 1714 /* 0 - any non-TS event 1715 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1716 * 2 - SAMPLE_PIPELINESTAT 1717 * 3 - SAMPLE_STREAMOUTSTAT* 1718 * 4 - *S_PARTIAL_FLUSH 1719 * 5 - EOP events 1720 * 6 - EOS events 1721 */ 1722#define PACKET3_EVENT_WRITE_EOP 0x47 1723#define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1724#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1725#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1726#define EOP_TCL1_ACTION_EN (1 << 16) 1727#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1728#define EOP_CACHE_POLICY(x) ((x) << 25) 1729 /* 0 - LRU 1730 * 1 - Stream 1731 * 2 - Bypass 1732 */ 1733#define EOP_TCL2_VOLATILE (1 << 27) 1734#define DATA_SEL(x) ((x) << 29) 1735 /* 0 - discard 1736 * 1 - send low 32bit data 1737 * 2 - send 64bit data 1738 * 3 - send 64bit GPU counter value 1739 * 4 - send 64bit sys counter value 1740 */ 1741#define INT_SEL(x) ((x) << 24) 1742 /* 0 - none 1743 * 1 - interrupt only (DATA_SEL = 0) 1744 * 2 - interrupt when data write is confirmed 1745 */ 1746#define DST_SEL(x) ((x) << 16) 1747 /* 0 - MC 1748 * 1 - TC/L2 1749 */ 1750#define PACKET3_EVENT_WRITE_EOS 0x48 1751#define PACKET3_RELEASE_MEM 0x49 1752#define PACKET3_PREAMBLE_CNTL 0x4A 1753# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1754# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1755#define PACKET3_DMA_DATA 0x50 1756/* 1. header 1757 * 2. CONTROL 1758 * 3. SRC_ADDR_LO or DATA [31:0] 1759 * 4. SRC_ADDR_HI [31:0] 1760 * 5. DST_ADDR_LO [31:0] 1761 * 6. DST_ADDR_HI [7:0] 1762 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 1763 */ 1764/* CONTROL */ 1765# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 1766 /* 0 - ME 1767 * 1 - PFP 1768 */ 1769# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 1770 /* 0 - LRU 1771 * 1 - Stream 1772 * 2 - Bypass 1773 */ 1774# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 1775# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 1776 /* 0 - DST_ADDR using DAS 1777 * 1 - GDS 1778 * 3 - DST_ADDR using L2 1779 */ 1780# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 1781 /* 0 - LRU 1782 * 1 - Stream 1783 * 2 - Bypass 1784 */ 1785# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 1786# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 1787 /* 0 - SRC_ADDR using SAS 1788 * 1 - GDS 1789 * 2 - DATA 1790 * 3 - SRC_ADDR using L2 1791 */ 1792# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 1793/* COMMAND */ 1794# define PACKET3_DMA_DATA_DIS_WC (1 << 21) 1795# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 1796 /* 0 - none 1797 * 1 - 8 in 16 1798 * 2 - 8 in 32 1799 * 3 - 8 in 64 1800 */ 1801# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 1802 /* 0 - none 1803 * 1 - 8 in 16 1804 * 2 - 8 in 32 1805 * 3 - 8 in 64 1806 */ 1807# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 1808 /* 0 - memory 1809 * 1 - register 1810 */ 1811# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 1812 /* 0 - memory 1813 * 1 - register 1814 */ 1815# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 1816# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 1817# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 1818#define PACKET3_AQUIRE_MEM 0x58 1819#define PACKET3_REWIND 0x59 1820#define PACKET3_LOAD_UCONFIG_REG 0x5E 1821#define PACKET3_LOAD_SH_REG 0x5F 1822#define PACKET3_LOAD_CONFIG_REG 0x60 1823#define PACKET3_LOAD_CONTEXT_REG 0x61 1824#define PACKET3_SET_CONFIG_REG 0x68 1825#define PACKET3_SET_CONFIG_REG_START 0x00008000 1826#define PACKET3_SET_CONFIG_REG_END 0x0000b000 1827#define PACKET3_SET_CONTEXT_REG 0x69 1828#define PACKET3_SET_CONTEXT_REG_START 0x00028000 1829#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1830#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1831#define PACKET3_SET_SH_REG 0x76 1832#define PACKET3_SET_SH_REG_START 0x0000b000 1833#define PACKET3_SET_SH_REG_END 0x0000c000 1834#define PACKET3_SET_SH_REG_OFFSET 0x77 1835#define PACKET3_SET_QUEUE_REG 0x78 1836#define PACKET3_SET_UCONFIG_REG 0x79 1837#define PACKET3_SET_UCONFIG_REG_START 0x00030000 1838#define PACKET3_SET_UCONFIG_REG_END 0x00031000 1839#define PACKET3_SCRATCH_RAM_WRITE 0x7D 1840#define PACKET3_SCRATCH_RAM_READ 0x7E 1841#define PACKET3_LOAD_CONST_RAM 0x80 1842#define PACKET3_WRITE_CONST_RAM 0x81 1843#define PACKET3_DUMP_CONST_RAM 0x83 1844#define PACKET3_INCREMENT_CE_COUNTER 0x84 1845#define PACKET3_INCREMENT_DE_COUNTER 0x85 1846#define PACKET3_WAIT_ON_CE_COUNTER 0x86 1847#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1848#define PACKET3_SWITCH_BUFFER 0x8B 1849 1850/* SDMA - first instance at 0xd000, second at 0xd800 */ 1851#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 1852#define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 1853 1854#define SDMA0_UCODE_ADDR 0xD000 1855#define SDMA0_UCODE_DATA 0xD004 1856#define SDMA0_POWER_CNTL 0xD008 1857#define SDMA0_CLK_CTRL 0xD00C 1858 1859#define SDMA0_CNTL 0xD010 1860# define TRAP_ENABLE (1 << 0) 1861# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1862# define SEM_WAIT_INT_ENABLE (1 << 2) 1863# define DATA_SWAP_ENABLE (1 << 3) 1864# define FENCE_SWAP_ENABLE (1 << 4) 1865# define AUTO_CTXSW_ENABLE (1 << 18) 1866# define CTXEMPTY_INT_ENABLE (1 << 28) 1867 1868#define SDMA0_TILING_CONFIG 0xD018 1869 1870#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 1871#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 1872 1873#define SDMA0_STATUS_REG 0xd034 1874# define SDMA_IDLE (1 << 0) 1875 1876#define SDMA0_ME_CNTL 0xD048 1877# define SDMA_HALT (1 << 0) 1878 1879#define SDMA0_GFX_RB_CNTL 0xD200 1880# define SDMA_RB_ENABLE (1 << 0) 1881# define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1882# define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1883# define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1884# define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1885# define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1886#define SDMA0_GFX_RB_BASE 0xD204 1887#define SDMA0_GFX_RB_BASE_HI 0xD208 1888#define SDMA0_GFX_RB_RPTR 0xD20C 1889#define SDMA0_GFX_RB_WPTR 0xD210 1890 1891#define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 1892#define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 1893#define SDMA0_GFX_IB_CNTL 0xD228 1894# define SDMA_IB_ENABLE (1 << 0) 1895# define SDMA_IB_SWAP_ENABLE (1 << 4) 1896# define SDMA_SWITCH_INSIDE_IB (1 << 8) 1897# define SDMA_CMD_VMID(x) ((x) << 16) 1898 1899#define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 1900#define SDMA0_GFX_APE1_CNTL 0xD2A0 1901 1902#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 1903 (((sub_op) & 0xFF) << 8) | \ 1904 (((op) & 0xFF) << 0)) 1905/* sDMA opcodes */ 1906#define SDMA_OPCODE_NOP 0 1907#define SDMA_OPCODE_COPY 1 1908# define SDMA_COPY_SUB_OPCODE_LINEAR 0 1909# define SDMA_COPY_SUB_OPCODE_TILED 1 1910# define SDMA_COPY_SUB_OPCODE_SOA 3 1911# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 1912# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 1913# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 1914#define SDMA_OPCODE_WRITE 2 1915# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 1916# define SDMA_WRTIE_SUB_OPCODE_TILED 1 1917#define SDMA_OPCODE_INDIRECT_BUFFER 4 1918#define SDMA_OPCODE_FENCE 5 1919#define SDMA_OPCODE_TRAP 6 1920#define SDMA_OPCODE_SEMAPHORE 7 1921# define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 1922 /* 0 - increment 1923 * 1 - write 1 1924 */ 1925# define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 1926 /* 0 - wait 1927 * 1 - signal 1928 */ 1929# define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 1930 /* mailbox */ 1931#define SDMA_OPCODE_POLL_REG_MEM 8 1932# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 1933 /* 0 - wait_reg_mem 1934 * 1 - wr_wait_wr_reg 1935 */ 1936# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 1937 /* 0 - always 1938 * 1 - < 1939 * 2 - <= 1940 * 3 - == 1941 * 4 - != 1942 * 5 - >= 1943 * 6 - > 1944 */ 1945# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 1946 /* 0 = register 1947 * 1 = memory 1948 */ 1949#define SDMA_OPCODE_COND_EXEC 9 1950#define SDMA_OPCODE_CONSTANT_FILL 11 1951# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 1952 /* 0 = byte fill 1953 * 2 = DW fill 1954 */ 1955#define SDMA_OPCODE_GENERATE_PTE_PDE 12 1956#define SDMA_OPCODE_TIMESTAMP 13 1957# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 1958# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 1959# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 1960#define SDMA_OPCODE_SRBM_WRITE 14 1961# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 1962 /* byte mask */ 1963 1964/* UVD */ 1965 1966#define UVD_UDEC_ADDR_CONFIG 0xef4c 1967#define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1968#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1969 1970#define UVD_LMI_EXT40_ADDR 0xf498 1971#define UVD_LMI_ADDR_EXT 0xf594 1972#define UVD_VCPU_CACHE_OFFSET0 0xf608 1973#define UVD_VCPU_CACHE_SIZE0 0xf60c 1974#define UVD_VCPU_CACHE_OFFSET1 0xf610 1975#define UVD_VCPU_CACHE_SIZE1 0xf614 1976#define UVD_VCPU_CACHE_OFFSET2 0xf618 1977#define UVD_VCPU_CACHE_SIZE2 0xf61c 1978 1979#define UVD_RBC_RB_RPTR 0xf690 1980#define UVD_RBC_RB_WPTR 0xf694 1981 1982#define UVD_CGC_CTRL 0xF4B0 1983# define DCM (1 << 0) 1984# define CG_DT(x) ((x) << 2) 1985# define CG_DT_MASK (0xf << 2) 1986# define CLK_OD(x) ((x) << 6) 1987# define CLK_OD_MASK (0x1f << 6) 1988 1989/* UVD clocks */ 1990 1991#define CG_DCLK_CNTL 0xC050009C 1992# define DCLK_DIVIDER_MASK 0x7f 1993# define DCLK_DIR_CNTL_EN (1 << 8) 1994#define CG_DCLK_STATUS 0xC05000A0 1995# define DCLK_STATUS (1 << 0) 1996#define CG_VCLK_CNTL 0xC05000A4 1997#define CG_VCLK_STATUS 0xC05000A8 1998 1999/* UVD CTX indirect */ 2000#define UVD_CGC_MEM_CTRL 0xC0
2001 2002#endif 2003