linux/drivers/mtd/onenand/samsung.c
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   1/*
   2 * Samsung S3C64XX/S5PC1XX OneNAND driver
   3 *
   4 *  Copyright © 2008-2010 Samsung Electronics
   5 *  Kyungmin Park <kyungmin.park@samsung.com>
   6 *  Marek Szyprowski <m.szyprowski@samsung.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * Implementation:
  13 *      S3C64XX and S5PC100: emulate the pseudo BufferRAM
  14 *      S5PC110: use DMA
  15 */
  16
  17#include <linux/module.h>
  18#include <linux/platform_device.h>
  19#include <linux/sched.h>
  20#include <linux/slab.h>
  21#include <linux/mtd/mtd.h>
  22#include <linux/mtd/onenand.h>
  23#include <linux/mtd/partitions.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/interrupt.h>
  26#include <linux/io.h>
  27
  28#include <asm/mach/flash.h>
  29
  30#include "samsung.h"
  31
  32enum soc_type {
  33        TYPE_S3C6400,
  34        TYPE_S3C6410,
  35        TYPE_S5PC100,
  36        TYPE_S5PC110,
  37};
  38
  39#define ONENAND_ERASE_STATUS            0x00
  40#define ONENAND_MULTI_ERASE_SET         0x01
  41#define ONENAND_ERASE_START             0x03
  42#define ONENAND_UNLOCK_START            0x08
  43#define ONENAND_UNLOCK_END              0x09
  44#define ONENAND_LOCK_START              0x0A
  45#define ONENAND_LOCK_END                0x0B
  46#define ONENAND_LOCK_TIGHT_START        0x0C
  47#define ONENAND_LOCK_TIGHT_END          0x0D
  48#define ONENAND_UNLOCK_ALL              0x0E
  49#define ONENAND_OTP_ACCESS              0x12
  50#define ONENAND_SPARE_ACCESS_ONLY       0x13
  51#define ONENAND_MAIN_ACCESS_ONLY        0x14
  52#define ONENAND_ERASE_VERIFY            0x15
  53#define ONENAND_MAIN_SPARE_ACCESS       0x16
  54#define ONENAND_PIPELINE_READ           0x4000
  55
  56#define MAP_00                          (0x0)
  57#define MAP_01                          (0x1)
  58#define MAP_10                          (0x2)
  59#define MAP_11                          (0x3)
  60
  61#define S3C64XX_CMD_MAP_SHIFT           24
  62#define S5PC100_CMD_MAP_SHIFT           26
  63
  64#define S3C6400_FBA_SHIFT               10
  65#define S3C6400_FPA_SHIFT               4
  66#define S3C6400_FSA_SHIFT               2
  67
  68#define S3C6410_FBA_SHIFT               12
  69#define S3C6410_FPA_SHIFT               6
  70#define S3C6410_FSA_SHIFT               4
  71
  72#define S5PC100_FBA_SHIFT               13
  73#define S5PC100_FPA_SHIFT               7
  74#define S5PC100_FSA_SHIFT               5
  75
  76/* S5PC110 specific definitions */
  77#define S5PC110_DMA_SRC_ADDR            0x400
  78#define S5PC110_DMA_SRC_CFG             0x404
  79#define S5PC110_DMA_DST_ADDR            0x408
  80#define S5PC110_DMA_DST_CFG             0x40C
  81#define S5PC110_DMA_TRANS_SIZE          0x414
  82#define S5PC110_DMA_TRANS_CMD           0x418
  83#define S5PC110_DMA_TRANS_STATUS        0x41C
  84#define S5PC110_DMA_TRANS_DIR           0x420
  85#define S5PC110_INTC_DMA_CLR            0x1004
  86#define S5PC110_INTC_ONENAND_CLR        0x1008
  87#define S5PC110_INTC_DMA_MASK           0x1024
  88#define S5PC110_INTC_ONENAND_MASK       0x1028
  89#define S5PC110_INTC_DMA_PEND           0x1044
  90#define S5PC110_INTC_ONENAND_PEND       0x1048
  91#define S5PC110_INTC_DMA_STATUS         0x1064
  92#define S5PC110_INTC_ONENAND_STATUS     0x1068
  93
  94#define S5PC110_INTC_DMA_TD             (1 << 24)
  95#define S5PC110_INTC_DMA_TE             (1 << 16)
  96
  97#define S5PC110_DMA_CFG_SINGLE          (0x0 << 16)
  98#define S5PC110_DMA_CFG_4BURST          (0x2 << 16)
  99#define S5PC110_DMA_CFG_8BURST          (0x3 << 16)
 100#define S5PC110_DMA_CFG_16BURST         (0x4 << 16)
 101
 102#define S5PC110_DMA_CFG_INC             (0x0 << 8)
 103#define S5PC110_DMA_CFG_CNT             (0x1 << 8)
 104
 105#define S5PC110_DMA_CFG_8BIT            (0x0 << 0)
 106#define S5PC110_DMA_CFG_16BIT           (0x1 << 0)
 107#define S5PC110_DMA_CFG_32BIT           (0x2 << 0)
 108
 109#define S5PC110_DMA_SRC_CFG_READ        (S5PC110_DMA_CFG_16BURST | \
 110                                        S5PC110_DMA_CFG_INC | \
 111                                        S5PC110_DMA_CFG_16BIT)
 112#define S5PC110_DMA_DST_CFG_READ        (S5PC110_DMA_CFG_16BURST | \
 113                                        S5PC110_DMA_CFG_INC | \
 114                                        S5PC110_DMA_CFG_32BIT)
 115#define S5PC110_DMA_SRC_CFG_WRITE       (S5PC110_DMA_CFG_16BURST | \
 116                                        S5PC110_DMA_CFG_INC | \
 117                                        S5PC110_DMA_CFG_32BIT)
 118#define S5PC110_DMA_DST_CFG_WRITE       (S5PC110_DMA_CFG_16BURST | \
 119                                        S5PC110_DMA_CFG_INC | \
 120                                        S5PC110_DMA_CFG_16BIT)
 121
 122#define S5PC110_DMA_TRANS_CMD_TDC       (0x1 << 18)
 123#define S5PC110_DMA_TRANS_CMD_TEC       (0x1 << 16)
 124#define S5PC110_DMA_TRANS_CMD_TR        (0x1 << 0)
 125
 126#define S5PC110_DMA_TRANS_STATUS_TD     (0x1 << 18)
 127#define S5PC110_DMA_TRANS_STATUS_TB     (0x1 << 17)
 128#define S5PC110_DMA_TRANS_STATUS_TE     (0x1 << 16)
 129
 130#define S5PC110_DMA_DIR_READ            0x0
 131#define S5PC110_DMA_DIR_WRITE           0x1
 132
 133struct s3c_onenand {
 134        struct mtd_info *mtd;
 135        struct platform_device  *pdev;
 136        enum soc_type   type;
 137        void __iomem    *base;
 138        struct resource *base_res;
 139        void __iomem    *ahb_addr;
 140        struct resource *ahb_res;
 141        int             bootram_command;
 142        void __iomem    *page_buf;
 143        void __iomem    *oob_buf;
 144        unsigned int    (*mem_addr)(int fba, int fpa, int fsa);
 145        unsigned int    (*cmd_map)(unsigned int type, unsigned int val);
 146        void __iomem    *dma_addr;
 147        struct resource *dma_res;
 148        unsigned long   phys_base;
 149        struct completion       complete;
 150};
 151
 152#define CMD_MAP_00(dev, addr)           (dev->cmd_map(MAP_00, ((addr) << 1)))
 153#define CMD_MAP_01(dev, mem_addr)       (dev->cmd_map(MAP_01, (mem_addr)))
 154#define CMD_MAP_10(dev, mem_addr)       (dev->cmd_map(MAP_10, (mem_addr)))
 155#define CMD_MAP_11(dev, addr)           (dev->cmd_map(MAP_11, ((addr) << 2)))
 156
 157static struct s3c_onenand *onenand;
 158
 159static inline int s3c_read_reg(int offset)
 160{
 161        return readl(onenand->base + offset);
 162}
 163
 164static inline void s3c_write_reg(int value, int offset)
 165{
 166        writel(value, onenand->base + offset);
 167}
 168
 169static inline int s3c_read_cmd(unsigned int cmd)
 170{
 171        return readl(onenand->ahb_addr + cmd);
 172}
 173
 174static inline void s3c_write_cmd(int value, unsigned int cmd)
 175{
 176        writel(value, onenand->ahb_addr + cmd);
 177}
 178
 179#ifdef SAMSUNG_DEBUG
 180static void s3c_dump_reg(void)
 181{
 182        int i;
 183
 184        for (i = 0; i < 0x400; i += 0x40) {
 185                printk(KERN_INFO "0x%08X: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 186                        (unsigned int) onenand->base + i,
 187                        s3c_read_reg(i), s3c_read_reg(i + 0x10),
 188                        s3c_read_reg(i + 0x20), s3c_read_reg(i + 0x30));
 189        }
 190}
 191#endif
 192
 193static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
 194{
 195        return (type << S3C64XX_CMD_MAP_SHIFT) | val;
 196}
 197
 198static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
 199{
 200        return (type << S5PC100_CMD_MAP_SHIFT) | val;
 201}
 202
 203static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
 204{
 205        return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
 206                (fsa << S3C6400_FSA_SHIFT);
 207}
 208
 209static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
 210{
 211        return (fba << S3C6410_FBA_SHIFT) | (fpa << S3C6410_FPA_SHIFT) |
 212                (fsa << S3C6410_FSA_SHIFT);
 213}
 214
 215static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa)
 216{
 217        return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) |
 218                (fsa << S5PC100_FSA_SHIFT);
 219}
 220
 221static void s3c_onenand_reset(void)
 222{
 223        unsigned long timeout = 0x10000;
 224        int stat;
 225
 226        s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
 227        while (1 && timeout--) {
 228                stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 229                if (stat & RST_CMP)
 230                        break;
 231        }
 232        stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 233        s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
 234
 235        /* Clear interrupt */
 236        s3c_write_reg(0x0, INT_ERR_ACK_OFFSET);
 237        /* Clear the ECC status */
 238        s3c_write_reg(0x0, ECC_ERR_STAT_OFFSET);
 239}
 240
 241static unsigned short s3c_onenand_readw(void __iomem *addr)
 242{
 243        struct onenand_chip *this = onenand->mtd->priv;
 244        struct device *dev = &onenand->pdev->dev;
 245        int reg = addr - this->base;
 246        int word_addr = reg >> 1;
 247        int value;
 248
 249        /* It's used for probing time */
 250        switch (reg) {
 251        case ONENAND_REG_MANUFACTURER_ID:
 252                return s3c_read_reg(MANUFACT_ID_OFFSET);
 253        case ONENAND_REG_DEVICE_ID:
 254                return s3c_read_reg(DEVICE_ID_OFFSET);
 255        case ONENAND_REG_VERSION_ID:
 256                return s3c_read_reg(FLASH_VER_ID_OFFSET);
 257        case ONENAND_REG_DATA_BUFFER_SIZE:
 258                return s3c_read_reg(DATA_BUF_SIZE_OFFSET);
 259        case ONENAND_REG_TECHNOLOGY:
 260                return s3c_read_reg(TECH_OFFSET);
 261        case ONENAND_REG_SYS_CFG1:
 262                return s3c_read_reg(MEM_CFG_OFFSET);
 263
 264        /* Used at unlock all status */
 265        case ONENAND_REG_CTRL_STATUS:
 266                return 0;
 267
 268        case ONENAND_REG_WP_STATUS:
 269                return ONENAND_WP_US;
 270
 271        default:
 272                break;
 273        }
 274
 275        /* BootRAM access control */
 276        if ((unsigned int) addr < ONENAND_DATARAM && onenand->bootram_command) {
 277                if (word_addr == 0)
 278                        return s3c_read_reg(MANUFACT_ID_OFFSET);
 279                if (word_addr == 1)
 280                        return s3c_read_reg(DEVICE_ID_OFFSET);
 281                if (word_addr == 2)
 282                        return s3c_read_reg(FLASH_VER_ID_OFFSET);
 283        }
 284
 285        value = s3c_read_cmd(CMD_MAP_11(onenand, word_addr)) & 0xffff;
 286        dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
 287                 word_addr, value);
 288        return value;
 289}
 290
 291static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
 292{
 293        struct onenand_chip *this = onenand->mtd->priv;
 294        struct device *dev = &onenand->pdev->dev;
 295        unsigned int reg = addr - this->base;
 296        unsigned int word_addr = reg >> 1;
 297
 298        /* It's used for probing time */
 299        switch (reg) {
 300        case ONENAND_REG_SYS_CFG1:
 301                s3c_write_reg(value, MEM_CFG_OFFSET);
 302                return;
 303
 304        case ONENAND_REG_START_ADDRESS1:
 305        case ONENAND_REG_START_ADDRESS2:
 306                return;
 307
 308        /* Lock/lock-tight/unlock/unlock_all */
 309        case ONENAND_REG_START_BLOCK_ADDRESS:
 310                return;
 311
 312        default:
 313                break;
 314        }
 315
 316        /* BootRAM access control */
 317        if ((unsigned int)addr < ONENAND_DATARAM) {
 318                if (value == ONENAND_CMD_READID) {
 319                        onenand->bootram_command = 1;
 320                        return;
 321                }
 322                if (value == ONENAND_CMD_RESET) {
 323                        s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
 324                        onenand->bootram_command = 0;
 325                        return;
 326                }
 327        }
 328
 329        dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
 330                 word_addr, value);
 331
 332        s3c_write_cmd(value, CMD_MAP_11(onenand, word_addr));
 333}
 334
 335static int s3c_onenand_wait(struct mtd_info *mtd, int state)
 336{
 337        struct device *dev = &onenand->pdev->dev;
 338        unsigned int flags = INT_ACT;
 339        unsigned int stat, ecc;
 340        unsigned long timeout;
 341
 342        switch (state) {
 343        case FL_READING:
 344                flags |= BLK_RW_CMP | LOAD_CMP;
 345                break;
 346        case FL_WRITING:
 347                flags |= BLK_RW_CMP | PGM_CMP;
 348                break;
 349        case FL_ERASING:
 350                flags |= BLK_RW_CMP | ERS_CMP;
 351                break;
 352        case FL_LOCKING:
 353                flags |= BLK_RW_CMP;
 354                break;
 355        default:
 356                break;
 357        }
 358
 359        /* The 20 msec is enough */
 360        timeout = jiffies + msecs_to_jiffies(20);
 361        while (time_before(jiffies, timeout)) {
 362                stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 363                if (stat & flags)
 364                        break;
 365
 366                if (state != FL_READING)
 367                        cond_resched();
 368        }
 369        /* To get correct interrupt status in timeout case */
 370        stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 371        s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
 372
 373        /*
 374         * In the Spec. it checks the controller status first
 375         * However if you get the correct information in case of
 376         * power off recovery (POR) test, it should read ECC status first
 377         */
 378        if (stat & LOAD_CMP) {
 379                ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
 380                if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
 381                        dev_info(dev, "%s: ECC error = 0x%04x\n", __func__,
 382                                 ecc);
 383                        mtd->ecc_stats.failed++;
 384                        return -EBADMSG;
 385                }
 386        }
 387
 388        if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
 389                dev_info(dev, "%s: controller error = 0x%04x\n", __func__,
 390                         stat);
 391                if (stat & LOCKED_BLK)
 392                        dev_info(dev, "%s: it's locked error = 0x%04x\n",
 393                                 __func__, stat);
 394
 395                return -EIO;
 396        }
 397
 398        return 0;
 399}
 400
 401static int s3c_onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
 402                               size_t len)
 403{
 404        struct onenand_chip *this = mtd->priv;
 405        unsigned int *m, *s;
 406        int fba, fpa, fsa = 0;
 407        unsigned int mem_addr, cmd_map_01, cmd_map_10;
 408        int i, mcount, scount;
 409        int index;
 410
 411        fba = (int) (addr >> this->erase_shift);
 412        fpa = (int) (addr >> this->page_shift);
 413        fpa &= this->page_mask;
 414
 415        mem_addr = onenand->mem_addr(fba, fpa, fsa);
 416        cmd_map_01 = CMD_MAP_01(onenand, mem_addr);
 417        cmd_map_10 = CMD_MAP_10(onenand, mem_addr);
 418
 419        switch (cmd) {
 420        case ONENAND_CMD_READ:
 421        case ONENAND_CMD_READOOB:
 422        case ONENAND_CMD_BUFFERRAM:
 423                ONENAND_SET_NEXT_BUFFERRAM(this);
 424        default:
 425                break;
 426        }
 427
 428        index = ONENAND_CURRENT_BUFFERRAM(this);
 429
 430        /*
 431         * Emulate Two BufferRAMs and access with 4 bytes pointer
 432         */
 433        m = (unsigned int *) onenand->page_buf;
 434        s = (unsigned int *) onenand->oob_buf;
 435
 436        if (index) {
 437                m += (this->writesize >> 2);
 438                s += (mtd->oobsize >> 2);
 439        }
 440
 441        mcount = mtd->writesize >> 2;
 442        scount = mtd->oobsize >> 2;
 443
 444        switch (cmd) {
 445        case ONENAND_CMD_READ:
 446                /* Main */
 447                for (i = 0; i < mcount; i++)
 448                        *m++ = s3c_read_cmd(cmd_map_01);
 449                return 0;
 450
 451        case ONENAND_CMD_READOOB:
 452                s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
 453                /* Main */
 454                for (i = 0; i < mcount; i++)
 455                        *m++ = s3c_read_cmd(cmd_map_01);
 456
 457                /* Spare */
 458                for (i = 0; i < scount; i++)
 459                        *s++ = s3c_read_cmd(cmd_map_01);
 460
 461                s3c_write_reg(0, TRANS_SPARE_OFFSET);
 462                return 0;
 463
 464        case ONENAND_CMD_PROG:
 465                /* Main */
 466                for (i = 0; i < mcount; i++)
 467                        s3c_write_cmd(*m++, cmd_map_01);
 468                return 0;
 469
 470        case ONENAND_CMD_PROGOOB:
 471                s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
 472
 473                /* Main - dummy write */
 474                for (i = 0; i < mcount; i++)
 475                        s3c_write_cmd(0xffffffff, cmd_map_01);
 476
 477                /* Spare */
 478                for (i = 0; i < scount; i++)
 479                        s3c_write_cmd(*s++, cmd_map_01);
 480
 481                s3c_write_reg(0, TRANS_SPARE_OFFSET);
 482                return 0;
 483
 484        case ONENAND_CMD_UNLOCK_ALL:
 485                s3c_write_cmd(ONENAND_UNLOCK_ALL, cmd_map_10);
 486                return 0;
 487
 488        case ONENAND_CMD_ERASE:
 489                s3c_write_cmd(ONENAND_ERASE_START, cmd_map_10);
 490                return 0;
 491
 492        default:
 493                break;
 494        }
 495
 496        return 0;
 497}
 498
 499static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
 500{
 501        struct onenand_chip *this = mtd->priv;
 502        int index = ONENAND_CURRENT_BUFFERRAM(this);
 503        unsigned char *p;
 504
 505        if (area == ONENAND_DATARAM) {
 506                p = (unsigned char *) onenand->page_buf;
 507                if (index == 1)
 508                        p += this->writesize;
 509        } else {
 510                p = (unsigned char *) onenand->oob_buf;
 511                if (index == 1)
 512                        p += mtd->oobsize;
 513        }
 514
 515        return p;
 516}
 517
 518static int onenand_read_bufferram(struct mtd_info *mtd, int area,
 519                                  unsigned char *buffer, int offset,
 520                                  size_t count)
 521{
 522        unsigned char *p;
 523
 524        p = s3c_get_bufferram(mtd, area);
 525        memcpy(buffer, p + offset, count);
 526        return 0;
 527}
 528
 529static int onenand_write_bufferram(struct mtd_info *mtd, int area,
 530                                   const unsigned char *buffer, int offset,
 531                                   size_t count)
 532{
 533        unsigned char *p;
 534
 535        p = s3c_get_bufferram(mtd, area);
 536        memcpy(p + offset, buffer, count);
 537        return 0;
 538}
 539
 540static int (*s5pc110_dma_ops)(void *dst, void *src, size_t count, int direction);
 541
 542static int s5pc110_dma_poll(void *dst, void *src, size_t count, int direction)
 543{
 544        void __iomem *base = onenand->dma_addr;
 545        int status;
 546        unsigned long timeout;
 547
 548        writel(src, base + S5PC110_DMA_SRC_ADDR);
 549        writel(dst, base + S5PC110_DMA_DST_ADDR);
 550
 551        if (direction == S5PC110_DMA_DIR_READ) {
 552                writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
 553                writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
 554        } else {
 555                writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
 556                writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
 557        }
 558
 559        writel(count, base + S5PC110_DMA_TRANS_SIZE);
 560        writel(direction, base + S5PC110_DMA_TRANS_DIR);
 561
 562        writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
 563
 564        /*
 565         * There's no exact timeout values at Spec.
 566         * In real case it takes under 1 msec.
 567         * So 20 msecs are enough.
 568         */
 569        timeout = jiffies + msecs_to_jiffies(20);
 570
 571        do {
 572                status = readl(base + S5PC110_DMA_TRANS_STATUS);
 573                if (status & S5PC110_DMA_TRANS_STATUS_TE) {
 574                        writel(S5PC110_DMA_TRANS_CMD_TEC,
 575                                        base + S5PC110_DMA_TRANS_CMD);
 576                        return -EIO;
 577                }
 578        } while (!(status & S5PC110_DMA_TRANS_STATUS_TD) &&
 579                time_before(jiffies, timeout));
 580
 581        writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
 582
 583        return 0;
 584}
 585
 586static irqreturn_t s5pc110_onenand_irq(int irq, void *data)
 587{
 588        void __iomem *base = onenand->dma_addr;
 589        int status, cmd = 0;
 590
 591        status = readl(base + S5PC110_INTC_DMA_STATUS);
 592
 593        if (likely(status & S5PC110_INTC_DMA_TD))
 594                cmd = S5PC110_DMA_TRANS_CMD_TDC;
 595
 596        if (unlikely(status & S5PC110_INTC_DMA_TE))
 597                cmd = S5PC110_DMA_TRANS_CMD_TEC;
 598
 599        writel(cmd, base + S5PC110_DMA_TRANS_CMD);
 600        writel(status, base + S5PC110_INTC_DMA_CLR);
 601
 602        if (!onenand->complete.done)
 603                complete(&onenand->complete);
 604
 605        return IRQ_HANDLED;
 606}
 607
 608static int s5pc110_dma_irq(void *dst, void *src, size_t count, int direction)
 609{
 610        void __iomem *base = onenand->dma_addr;
 611        int status;
 612
 613        status = readl(base + S5PC110_INTC_DMA_MASK);
 614        if (status) {
 615                status &= ~(S5PC110_INTC_DMA_TD | S5PC110_INTC_DMA_TE);
 616                writel(status, base + S5PC110_INTC_DMA_MASK);
 617        }
 618
 619        writel(src, base + S5PC110_DMA_SRC_ADDR);
 620        writel(dst, base + S5PC110_DMA_DST_ADDR);
 621
 622        if (direction == S5PC110_DMA_DIR_READ) {
 623                writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
 624                writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
 625        } else {
 626                writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
 627                writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
 628        }
 629
 630        writel(count, base + S5PC110_DMA_TRANS_SIZE);
 631        writel(direction, base + S5PC110_DMA_TRANS_DIR);
 632
 633        writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
 634
 635        wait_for_completion_timeout(&onenand->complete, msecs_to_jiffies(20));
 636
 637        return 0;
 638}
 639
 640static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
 641                unsigned char *buffer, int offset, size_t count)
 642{
 643        struct onenand_chip *this = mtd->priv;
 644        void __iomem *p;
 645        void *buf = (void *) buffer;
 646        dma_addr_t dma_src, dma_dst;
 647        int err, ofs, page_dma = 0;
 648        struct device *dev = &onenand->pdev->dev;
 649
 650        p = this->base + area;
 651        if (ONENAND_CURRENT_BUFFERRAM(this)) {
 652                if (area == ONENAND_DATARAM)
 653                        p += this->writesize;
 654                else
 655                        p += mtd->oobsize;
 656        }
 657
 658        if (offset & 3 || (size_t) buf & 3 ||
 659                !onenand->dma_addr || count != mtd->writesize)
 660                goto normal;
 661
 662        /* Handle vmalloc address */
 663        if (buf >= high_memory) {
 664                struct page *page;
 665
 666                if (((size_t) buf & PAGE_MASK) !=
 667                    ((size_t) (buf + count - 1) & PAGE_MASK))
 668                        goto normal;
 669                page = vmalloc_to_page(buf);
 670                if (!page)
 671                        goto normal;
 672
 673                /* Page offset */
 674                ofs = ((size_t) buf & ~PAGE_MASK);
 675                page_dma = 1;
 676
 677                /* DMA routine */
 678                dma_src = onenand->phys_base + (p - this->base);
 679                dma_dst = dma_map_page(dev, page, ofs, count, DMA_FROM_DEVICE);
 680        } else {
 681                /* DMA routine */
 682                dma_src = onenand->phys_base + (p - this->base);
 683                dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
 684        }
 685        if (dma_mapping_error(dev, dma_dst)) {
 686                dev_err(dev, "Couldn't map a %d byte buffer for DMA\n", count);
 687                goto normal;
 688        }
 689        err = s5pc110_dma_ops((void *) dma_dst, (void *) dma_src,
 690                        count, S5PC110_DMA_DIR_READ);
 691
 692        if (page_dma)
 693                dma_unmap_page(dev, dma_dst, count, DMA_FROM_DEVICE);
 694        else
 695                dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
 696
 697        if (!err)
 698                return 0;
 699
 700normal:
 701        if (count != mtd->writesize) {
 702                /* Copy the bufferram to memory to prevent unaligned access */
 703                memcpy(this->page_buf, p, mtd->writesize);
 704                p = this->page_buf + offset;
 705        }
 706
 707        memcpy(buffer, p, count);
 708
 709        return 0;
 710}
 711
 712static int s5pc110_chip_probe(struct mtd_info *mtd)
 713{
 714        /* Now just return 0 */
 715        return 0;
 716}
 717
 718static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
 719{
 720        unsigned int flags = INT_ACT | LOAD_CMP;
 721        unsigned int stat;
 722        unsigned long timeout;
 723
 724        /* The 20 msec is enough */
 725        timeout = jiffies + msecs_to_jiffies(20);
 726        while (time_before(jiffies, timeout)) {
 727                stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 728                if (stat & flags)
 729                        break;
 730        }
 731        /* To get correct interrupt status in timeout case */
 732        stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
 733        s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
 734
 735        if (stat & LD_FAIL_ECC_ERR) {
 736                s3c_onenand_reset();
 737                return ONENAND_BBT_READ_ERROR;
 738        }
 739
 740        if (stat & LOAD_CMP) {
 741                int ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
 742                if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
 743                        s3c_onenand_reset();
 744                        return ONENAND_BBT_READ_ERROR;
 745                }
 746        }
 747
 748        return 0;
 749}
 750
 751static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
 752{
 753        struct onenand_chip *this = mtd->priv;
 754        struct device *dev = &onenand->pdev->dev;
 755        unsigned int block, end;
 756        int tmp;
 757
 758        end = this->chipsize >> this->erase_shift;
 759
 760        for (block = 0; block < end; block++) {
 761                unsigned int mem_addr = onenand->mem_addr(block, 0, 0);
 762                tmp = s3c_read_cmd(CMD_MAP_01(onenand, mem_addr));
 763
 764                if (s3c_read_reg(INT_ERR_STAT_OFFSET) & LOCKED_BLK) {
 765                        dev_err(dev, "block %d is write-protected!\n", block);
 766                        s3c_write_reg(LOCKED_BLK, INT_ERR_ACK_OFFSET);
 767                }
 768        }
 769}
 770
 771static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
 772                                    size_t len, int cmd)
 773{
 774        struct onenand_chip *this = mtd->priv;
 775        int start, end, start_mem_addr, end_mem_addr;
 776
 777        start = ofs >> this->erase_shift;
 778        start_mem_addr = onenand->mem_addr(start, 0, 0);
 779        end = start + (len >> this->erase_shift) - 1;
 780        end_mem_addr = onenand->mem_addr(end, 0, 0);
 781
 782        if (cmd == ONENAND_CMD_LOCK) {
 783                s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(onenand,
 784                                                             start_mem_addr));
 785                s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(onenand,
 786                                                           end_mem_addr));
 787        } else {
 788                s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(onenand,
 789                                                               start_mem_addr));
 790                s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(onenand,
 791                                                             end_mem_addr));
 792        }
 793
 794        this->wait(mtd, FL_LOCKING);
 795}
 796
 797static void s3c_unlock_all(struct mtd_info *mtd)
 798{
 799        struct onenand_chip *this = mtd->priv;
 800        loff_t ofs = 0;
 801        size_t len = this->chipsize;
 802
 803        if (this->options & ONENAND_HAS_UNLOCK_ALL) {
 804                /* Write unlock command */
 805                this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
 806
 807                /* No need to check return value */
 808                this->wait(mtd, FL_LOCKING);
 809
 810                /* Workaround for all block unlock in DDP */
 811                if (!ONENAND_IS_DDP(this)) {
 812                        s3c_onenand_check_lock_status(mtd);
 813                        return;
 814                }
 815
 816                /* All blocks on another chip */
 817                ofs = this->chipsize >> 1;
 818                len = this->chipsize >> 1;
 819        }
 820
 821        s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
 822
 823        s3c_onenand_check_lock_status(mtd);
 824}
 825
 826static void s3c_onenand_setup(struct mtd_info *mtd)
 827{
 828        struct onenand_chip *this = mtd->priv;
 829
 830        onenand->mtd = mtd;
 831
 832        if (onenand->type == TYPE_S3C6400) {
 833                onenand->mem_addr = s3c6400_mem_addr;
 834                onenand->cmd_map = s3c64xx_cmd_map;
 835        } else if (onenand->type == TYPE_S3C6410) {
 836                onenand->mem_addr = s3c6410_mem_addr;
 837                onenand->cmd_map = s3c64xx_cmd_map;
 838        } else if (onenand->type == TYPE_S5PC100) {
 839                onenand->mem_addr = s5pc100_mem_addr;
 840                onenand->cmd_map = s5pc1xx_cmd_map;
 841        } else if (onenand->type == TYPE_S5PC110) {
 842                /* Use generic onenand functions */
 843                this->read_bufferram = s5pc110_read_bufferram;
 844                this->chip_probe = s5pc110_chip_probe;
 845                return;
 846        } else {
 847                BUG();
 848        }
 849
 850        this->read_word = s3c_onenand_readw;
 851        this->write_word = s3c_onenand_writew;
 852
 853        this->wait = s3c_onenand_wait;
 854        this->bbt_wait = s3c_onenand_bbt_wait;
 855        this->unlock_all = s3c_unlock_all;
 856        this->command = s3c_onenand_command;
 857
 858        this->read_bufferram = onenand_read_bufferram;
 859        this->write_bufferram = onenand_write_bufferram;
 860}
 861
 862static int s3c_onenand_probe(struct platform_device *pdev)
 863{
 864        struct onenand_platform_data *pdata;
 865        struct onenand_chip *this;
 866        struct mtd_info *mtd;
 867        struct resource *r;
 868        int size, err;
 869
 870        pdata = dev_get_platdata(&pdev->dev);
 871        /* No need to check pdata. the platform data is optional */
 872
 873        size = sizeof(struct mtd_info) + sizeof(struct onenand_chip);
 874        mtd = kzalloc(size, GFP_KERNEL);
 875        if (!mtd) {
 876                dev_err(&pdev->dev, "failed to allocate memory\n");
 877                return -ENOMEM;
 878        }
 879
 880        onenand = kzalloc(sizeof(struct s3c_onenand), GFP_KERNEL);
 881        if (!onenand) {
 882                err = -ENOMEM;
 883                goto onenand_fail;
 884        }
 885
 886        this = (struct onenand_chip *) &mtd[1];
 887        mtd->priv = this;
 888        mtd->dev.parent = &pdev->dev;
 889        mtd->owner = THIS_MODULE;
 890        onenand->pdev = pdev;
 891        onenand->type = platform_get_device_id(pdev)->driver_data;
 892
 893        s3c_onenand_setup(mtd);
 894
 895        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 896        if (!r) {
 897                dev_err(&pdev->dev, "no memory resource defined\n");
 898                return -ENOENT;
 899                goto ahb_resource_failed;
 900        }
 901
 902        onenand->base_res = request_mem_region(r->start, resource_size(r),
 903                                               pdev->name);
 904        if (!onenand->base_res) {
 905                dev_err(&pdev->dev, "failed to request memory resource\n");
 906                err = -EBUSY;
 907                goto resource_failed;
 908        }
 909
 910        onenand->base = ioremap(r->start, resource_size(r));
 911        if (!onenand->base) {
 912                dev_err(&pdev->dev, "failed to map memory resource\n");
 913                err = -EFAULT;
 914                goto ioremap_failed;
 915        }
 916        /* Set onenand_chip also */
 917        this->base = onenand->base;
 918
 919        /* Use runtime badblock check */
 920        this->options |= ONENAND_SKIP_UNLOCK_CHECK;
 921
 922        if (onenand->type != TYPE_S5PC110) {
 923                r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 924                if (!r) {
 925                        dev_err(&pdev->dev, "no buffer memory resource defined\n");
 926                        err = -ENOENT;
 927                        goto ahb_resource_failed;
 928                }
 929
 930                onenand->ahb_res = request_mem_region(r->start, resource_size(r),
 931                                                      pdev->name);
 932                if (!onenand->ahb_res) {
 933                        dev_err(&pdev->dev, "failed to request buffer memory resource\n");
 934                        err = -EBUSY;
 935                        goto ahb_resource_failed;
 936                }
 937
 938                onenand->ahb_addr = ioremap(r->start, resource_size(r));
 939                if (!onenand->ahb_addr) {
 940                        dev_err(&pdev->dev, "failed to map buffer memory resource\n");
 941                        err = -EINVAL;
 942                        goto ahb_ioremap_failed;
 943                }
 944
 945                /* Allocate 4KiB BufferRAM */
 946                onenand->page_buf = kzalloc(SZ_4K, GFP_KERNEL);
 947                if (!onenand->page_buf) {
 948                        err = -ENOMEM;
 949                        goto page_buf_fail;
 950                }
 951
 952                /* Allocate 128 SpareRAM */
 953                onenand->oob_buf = kzalloc(128, GFP_KERNEL);
 954                if (!onenand->oob_buf) {
 955                        err = -ENOMEM;
 956                        goto oob_buf_fail;
 957                }
 958
 959                /* S3C doesn't handle subpage write */
 960                mtd->subpage_sft = 0;
 961                this->subpagesize = mtd->writesize;
 962
 963        } else { /* S5PC110 */
 964                r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 965                if (!r) {
 966                        dev_err(&pdev->dev, "no dma memory resource defined\n");
 967                        err = -ENOENT;
 968                        goto dma_resource_failed;
 969                }
 970
 971                onenand->dma_res = request_mem_region(r->start, resource_size(r),
 972                                                      pdev->name);
 973                if (!onenand->dma_res) {
 974                        dev_err(&pdev->dev, "failed to request dma memory resource\n");
 975                        err = -EBUSY;
 976                        goto dma_resource_failed;
 977                }
 978
 979                onenand->dma_addr = ioremap(r->start, resource_size(r));
 980                if (!onenand->dma_addr) {
 981                        dev_err(&pdev->dev, "failed to map dma memory resource\n");
 982                        err = -EINVAL;
 983                        goto dma_ioremap_failed;
 984                }
 985
 986                onenand->phys_base = onenand->base_res->start;
 987
 988                s5pc110_dma_ops = s5pc110_dma_poll;
 989                /* Interrupt support */
 990                r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 991                if (r) {
 992                        init_completion(&onenand->complete);
 993                        s5pc110_dma_ops = s5pc110_dma_irq;
 994                        err = request_irq(r->start, s5pc110_onenand_irq,
 995                                        IRQF_SHARED, "onenand", &onenand);
 996                        if (err) {
 997                                dev_err(&pdev->dev, "failed to get irq\n");
 998                                goto scan_failed;
 999                        }
1000                }
1001        }
1002
1003        if (onenand_scan(mtd, 1)) {
1004                err = -EFAULT;
1005                goto scan_failed;
1006        }
1007
1008        if (onenand->type != TYPE_S5PC110) {
1009                /* S3C doesn't handle subpage write */
1010                mtd->subpage_sft = 0;
1011                this->subpagesize = mtd->writesize;
1012        }
1013
1014        if (s3c_read_reg(MEM_CFG_OFFSET) & ONENAND_SYS_CFG1_SYNC_READ)
1015                dev_info(&onenand->pdev->dev, "OneNAND Sync. Burst Read enabled\n");
1016
1017        err = mtd_device_parse_register(mtd, NULL, NULL,
1018                                        pdata ? pdata->parts : NULL,
1019                                        pdata ? pdata->nr_parts : 0);
1020
1021        platform_set_drvdata(pdev, mtd);
1022
1023        return 0;
1024
1025scan_failed:
1026        if (onenand->dma_addr)
1027                iounmap(onenand->dma_addr);
1028dma_ioremap_failed:
1029        if (onenand->dma_res)
1030                release_mem_region(onenand->dma_res->start,
1031                                   resource_size(onenand->dma_res));
1032        kfree(onenand->oob_buf);
1033oob_buf_fail:
1034        kfree(onenand->page_buf);
1035page_buf_fail:
1036        if (onenand->ahb_addr)
1037                iounmap(onenand->ahb_addr);
1038ahb_ioremap_failed:
1039        if (onenand->ahb_res)
1040                release_mem_region(onenand->ahb_res->start,
1041                                   resource_size(onenand->ahb_res));
1042dma_resource_failed:
1043ahb_resource_failed:
1044        iounmap(onenand->base);
1045ioremap_failed:
1046        if (onenand->base_res)
1047                release_mem_region(onenand->base_res->start,
1048                                   resource_size(onenand->base_res));
1049resource_failed:
1050        kfree(onenand);
1051onenand_fail:
1052        kfree(mtd);
1053        return err;
1054}
1055
1056static int s3c_onenand_remove(struct platform_device *pdev)
1057{
1058        struct mtd_info *mtd = platform_get_drvdata(pdev);
1059
1060        onenand_release(mtd);
1061        if (onenand->ahb_addr)
1062                iounmap(onenand->ahb_addr);
1063        if (onenand->ahb_res)
1064                release_mem_region(onenand->ahb_res->start,
1065                                   resource_size(onenand->ahb_res));
1066        if (onenand->dma_addr)
1067                iounmap(onenand->dma_addr);
1068        if (onenand->dma_res)
1069                release_mem_region(onenand->dma_res->start,
1070                                   resource_size(onenand->dma_res));
1071
1072        iounmap(onenand->base);
1073        release_mem_region(onenand->base_res->start,
1074                           resource_size(onenand->base_res));
1075
1076        kfree(onenand->oob_buf);
1077        kfree(onenand->page_buf);
1078        kfree(onenand);
1079        kfree(mtd);
1080        return 0;
1081}
1082
1083static int s3c_pm_ops_suspend(struct device *dev)
1084{
1085        struct platform_device *pdev = to_platform_device(dev);
1086        struct mtd_info *mtd = platform_get_drvdata(pdev);
1087        struct onenand_chip *this = mtd->priv;
1088
1089        this->wait(mtd, FL_PM_SUSPENDED);
1090        return 0;
1091}
1092
1093static  int s3c_pm_ops_resume(struct device *dev)
1094{
1095        struct platform_device *pdev = to_platform_device(dev);
1096        struct mtd_info *mtd = platform_get_drvdata(pdev);
1097        struct onenand_chip *this = mtd->priv;
1098
1099        this->unlock_all(mtd);
1100        return 0;
1101}
1102
1103static const struct dev_pm_ops s3c_pm_ops = {
1104        .suspend        = s3c_pm_ops_suspend,
1105        .resume         = s3c_pm_ops_resume,
1106};
1107
1108static struct platform_device_id s3c_onenand_driver_ids[] = {
1109        {
1110                .name           = "s3c6400-onenand",
1111                .driver_data    = TYPE_S3C6400,
1112        }, {
1113                .name           = "s3c6410-onenand",
1114                .driver_data    = TYPE_S3C6410,
1115        }, {
1116                .name           = "s5pc100-onenand",
1117                .driver_data    = TYPE_S5PC100,
1118        }, {
1119                .name           = "s5pc110-onenand",
1120                .driver_data    = TYPE_S5PC110,
1121        }, { },
1122};
1123MODULE_DEVICE_TABLE(platform, s3c_onenand_driver_ids);
1124
1125static struct platform_driver s3c_onenand_driver = {
1126        .driver         = {
1127                .name   = "samsung-onenand",
1128                .pm     = &s3c_pm_ops,
1129        },
1130        .id_table       = s3c_onenand_driver_ids,
1131        .probe          = s3c_onenand_probe,
1132        .remove         = s3c_onenand_remove,
1133};
1134
1135module_platform_driver(s3c_onenand_driver);
1136
1137MODULE_LICENSE("GPL");
1138MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
1139MODULE_DESCRIPTION("Samsung OneNAND controller support");
1140