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25#ifndef __IBM_NEWEMAC_CORE_H
26#define __IBM_NEWEMAC_CORE_H
27
28#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/list.h>
31#include <linux/kernel.h>
32#include <linux/interrupt.h>
33#include <linux/netdevice.h>
34#include <linux/dma-mapping.h>
35#include <linux/spinlock.h>
36#include <linux/of_platform.h>
37#include <linux/slab.h>
38
39#include <asm/io.h>
40#include <asm/dcr.h>
41
42#include "emac.h"
43#include "phy.h"
44#include "zmii.h"
45#include "rgmii.h"
46#include "mal.h"
47#include "tah.h"
48#include "debug.h"
49
50#define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB
51#define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB
52
53
54#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
55#error Invalid number of buffer descriptors (greater than 256)
56#endif
57
58#define EMAC_MIN_MTU 46
59
60
61#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
62
63
64static inline int emac_rx_size(int mtu)
65{
66 if (mtu > ETH_DATA_LEN)
67 return MAL_MAX_RX_SIZE;
68 else
69 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
70}
71
72#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
73
74#define EMAC_RX_SKB_HEADROOM \
75 EMAC_DMA_ALIGN(CONFIG_IBM_EMAC_RX_SKB_HEADROOM)
76
77
78static inline int emac_rx_skb_size(int mtu)
79{
80 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
81 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
82}
83
84
85static inline int emac_rx_sync_size(int mtu)
86{
87 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
88}
89
90
91
92
93
94
95
96
97
98
99
100
101struct emac_stats {
102 u64 rx_packets;
103 u64 rx_bytes;
104 u64 tx_packets;
105 u64 tx_bytes;
106 u64 rx_packets_csum;
107 u64 tx_packets_csum;
108};
109
110
111struct emac_error_stats {
112 u64 tx_undo;
113
114
115 u64 rx_dropped_stack;
116 u64 rx_dropped_oom;
117 u64 rx_dropped_error;
118 u64 rx_dropped_resize;
119 u64 rx_dropped_mtu;
120 u64 rx_stopped;
121
122 u64 rx_bd_errors;
123 u64 rx_bd_overrun;
124 u64 rx_bd_bad_packet;
125 u64 rx_bd_runt_packet;
126 u64 rx_bd_short_event;
127 u64 rx_bd_alignment_error;
128 u64 rx_bd_bad_fcs;
129 u64 rx_bd_packet_too_long;
130 u64 rx_bd_out_of_range;
131 u64 rx_bd_in_range;
132
133 u64 rx_parity;
134 u64 rx_fifo_overrun;
135 u64 rx_overrun;
136 u64 rx_bad_packet;
137 u64 rx_runt_packet;
138 u64 rx_short_event;
139 u64 rx_alignment_error;
140 u64 rx_bad_fcs;
141 u64 rx_packet_too_long;
142 u64 rx_out_of_range;
143 u64 rx_in_range;
144
145
146 u64 tx_dropped;
147
148 u64 tx_bd_errors;
149 u64 tx_bd_bad_fcs;
150 u64 tx_bd_carrier_loss;
151 u64 tx_bd_excessive_deferral;
152 u64 tx_bd_excessive_collisions;
153 u64 tx_bd_late_collision;
154 u64 tx_bd_multple_collisions;
155 u64 tx_bd_single_collision;
156 u64 tx_bd_underrun;
157 u64 tx_bd_sqe;
158
159 u64 tx_parity;
160 u64 tx_underrun;
161 u64 tx_sqe;
162 u64 tx_errors;
163};
164
165#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \
166 sizeof(struct emac_error_stats)) \
167 / sizeof(u64))
168
169struct emac_instance {
170 struct net_device *ndev;
171 struct resource rsrc_regs;
172 struct emac_regs __iomem *emacp;
173 struct platform_device *ofdev;
174 struct device_node **blist;
175
176
177 u32 mal_ph;
178 struct platform_device *mal_dev;
179 u32 mal_rx_chan;
180 u32 mal_tx_chan;
181 struct mal_instance *mal;
182 struct mal_commac commac;
183
184
185 u32 phy_mode;
186 u32 phy_map;
187 u32 phy_address;
188 u32 phy_feat_exc;
189 struct mii_phy phy;
190 struct mutex link_lock;
191 struct delayed_work link_work;
192 int link_polling;
193
194
195 u32 gpcs_address;
196
197
198 u32 mdio_ph;
199 struct platform_device *mdio_dev;
200 struct emac_instance *mdio_instance;
201 struct mutex mdio_lock;
202
203
204 u32 zmii_ph;
205 u32 zmii_port;
206 struct platform_device *zmii_dev;
207
208
209 u32 rgmii_ph;
210 u32 rgmii_port;
211 struct platform_device *rgmii_dev;
212
213
214 u32 tah_ph;
215 u32 tah_port;
216 struct platform_device *tah_dev;
217
218
219 int wol_irq;
220 int emac_irq;
221
222
223 u32 opb_bus_freq;
224
225
226 u32 cell_index;
227
228
229 u32 max_mtu;
230
231
232 unsigned int features;
233
234
235 u32 tx_fifo_size;
236 u32 tx_fifo_size_gige;
237 u32 rx_fifo_size;
238 u32 rx_fifo_size_gige;
239 u32 fifo_entry_size;
240 u32 mal_burst_size;
241
242
243 u32 xaht_slots_shift;
244 u32 xaht_width_shift;
245
246
247
248 struct mal_descriptor *tx_desc;
249 int tx_cnt;
250 int tx_slot;
251 int ack_slot;
252
253 struct mal_descriptor *rx_desc;
254 int rx_slot;
255 struct sk_buff *rx_sg_skb;
256 int rx_skb_size;
257 int rx_sync_size;
258
259 struct sk_buff *tx_skb[NUM_TX_BUFF];
260 struct sk_buff *rx_skb[NUM_RX_BUFF];
261
262
263
264 struct emac_error_stats estats;
265 struct net_device_stats nstats;
266 struct emac_stats stats;
267
268
269
270 int reset_failed;
271 int stop_timeout;
272 int no_mcast;
273 int mcast_pending;
274 int opened;
275 struct work_struct reset_work;
276 spinlock_t lock;
277};
278
279
280
281
282
283
284
285
286#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001
287
288
289
290#define EMAC_FTR_EMAC4 0x00000002
291
292
293
294
295#define EMAC_FTR_STACR_OC_INVERT 0x00000004
296
297
298
299#define EMAC_FTR_HAS_TAH 0x00000008
300
301
302
303#define EMAC_FTR_HAS_ZMII 0x00000010
304
305
306
307#define EMAC_FTR_HAS_RGMII 0x00000020
308
309
310
311#define EMAC_FTR_HAS_NEW_STACR 0x00000040
312
313
314
315#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
316
317
318
319#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100
320
321
322
323#define EMAC_FTR_EMAC4SYNC 0x00000200
324
325
326
327#define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400
328
329
330
331#define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE 0x00000800
332
333
334
335#define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000
336
337
338
339
340
341enum {
342 EMAC_FTRS_ALWAYS = 0,
343
344 EMAC_FTRS_POSSIBLE =
345#ifdef CONFIG_IBM_EMAC_EMAC4
346 EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC |
347 EMAC_FTR_HAS_NEW_STACR |
348 EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
349#endif
350#ifdef CONFIG_IBM_EMAC_TAH
351 EMAC_FTR_HAS_TAH |
352#endif
353#ifdef CONFIG_IBM_EMAC_ZMII
354 EMAC_FTR_HAS_ZMII |
355#endif
356#ifdef CONFIG_IBM_EMAC_RGMII
357 EMAC_FTR_HAS_RGMII |
358#endif
359#ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
360 EMAC_FTR_NO_FLOW_CONTROL_40x |
361#endif
362 EMAC_FTR_460EX_PHY_CLK_FIX |
363 EMAC_FTR_440EP_PHY_CLK_FIX |
364 EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
365 EMAC_FTR_APM821XX_NO_HALF_DUPLEX,
366};
367
368static inline int emac_has_feature(struct emac_instance *dev,
369 unsigned long feature)
370{
371 return (EMAC_FTRS_ALWAYS & feature) ||
372 (EMAC_FTRS_POSSIBLE & dev->features & feature);
373}
374
375
376
377
378
379
380
381
382
383
384
385
386#define EMAC4_XAHT_SLOTS_SHIFT 6
387#define EMAC4_XAHT_WIDTH_SHIFT 4
388
389#define EMAC4SYNC_XAHT_SLOTS_SHIFT 8
390#define EMAC4SYNC_XAHT_WIDTH_SHIFT 5
391
392#define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift)
393#define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift)
394#define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \
395 (dev)->xaht_width_shift))
396
397#define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \
398 ((EMAC_XAHT_SLOTS(dev) - 1) - \
399 ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \
400 (dev)->xaht_slots_shift)))
401
402#define EMAC_XAHT_SLOT_TO_REG(dev, slot) \
403 ((slot) >> (dev)->xaht_width_shift)
404
405#define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \
406 ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \
407 ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
408
409static inline u32 *emac_xaht_base(struct emac_instance *dev)
410{
411 struct emac_regs __iomem *p = dev->emacp;
412 int offset;
413
414
415
416
417 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
418 offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
419 else
420 offset = offsetof(struct emac_regs, u0.emac4.iaht1);
421
422 return (u32 *)((ptrdiff_t)p + offset);
423}
424
425static inline u32 *emac_gaht_base(struct emac_instance *dev)
426{
427
428
429
430 return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev);
431}
432
433static inline u32 *emac_iaht_base(struct emac_instance *dev)
434{
435
436
437
438 return emac_xaht_base(dev);
439}
440
441
442
443
444
445
446
447
448
449
450
451#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
452#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
453#define EMAC_ETHTOOL_REGS_TAH 0x00000004
454
455struct emac_ethtool_regs_hdr {
456 u32 components;
457};
458
459struct emac_ethtool_regs_subhdr {
460 u32 version;
461 u32 index;
462};
463
464#define EMAC_ETHTOOL_REGS_VER 0
465#define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \
466 (dev)->rsrc_regs.start + 1)
467#define EMAC4_ETHTOOL_REGS_VER 1
468#define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \
469 (dev)->rsrc_regs.start + 1)
470
471#endif
472