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17#include "hw.h"
18#include "hw-ops.h"
19#include <linux/export.h>
20
21static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
22 struct ath9k_tx_queue_info *qi)
23{
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT,
25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
28 ah->txurn_interrupt_mask);
29
30 ENABLE_REGWRITE_BUFFER(ah);
31
32 REG_WRITE(ah, AR_IMR_S0,
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
35 REG_WRITE(ah, AR_IMR_S1,
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
42
43 REGWRITE_BUFFER_FLUSH(ah);
44}
45
46u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47{
48 return REG_READ(ah, AR_QTXDP(q));
49}
50EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51
52void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53{
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
55}
56EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57
58void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59{
60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
62}
63EXPORT_SYMBOL(ath9k_hw_txstart);
64
65u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
66{
67 u32 npend;
68
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
70 if (npend == 0) {
71
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 npend = 1;
74 }
75
76 return npend;
77}
78EXPORT_SYMBOL(ath9k_hw_numtxpending);
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105bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
106{
107 u32 txcfg, curLevel, newLevel;
108
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
110 return false;
111
112 ath9k_hw_disable_interrupts(ah);
113
114 txcfg = REG_READ(ah, AR_TXCFG);
115 curLevel = MS(txcfg, AR_FTRIG);
116 newLevel = curLevel;
117 if (bIncTrigLevel) {
118 if (curLevel < ah->config.max_txtrig_level)
119 newLevel++;
120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
121 newLevel--;
122 if (newLevel != curLevel)
123 REG_WRITE(ah, AR_TXCFG,
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
125
126 ath9k_hw_enable_interrupts(ah);
127
128 ah->tx_trig_level = newLevel;
129
130 return newLevel != curLevel;
131}
132EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
133
134void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
135{
136 int maxdelay = 1000;
137 int i, q;
138
139 if (ah->curchan) {
140 if (IS_CHAN_HALF_RATE(ah->curchan))
141 maxdelay *= 2;
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan))
143 maxdelay *= 4;
144 }
145
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
147
148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
151
152 for (q = 0; q < AR_NUM_QCU; q++) {
153 for (i = 0; i < maxdelay; i++) {
154 if (i)
155 udelay(5);
156
157 if (!ath9k_hw_numtxpending(ah, q))
158 break;
159 }
160 }
161
162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
165
166 REG_WRITE(ah, AR_Q_TXD, 0);
167}
168EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
169
170bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
171{
172#define ATH9K_TX_STOP_DMA_TIMEOUT 1000
173#define ATH9K_TIME_QUANTUM 100
174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
175 int wait;
176
177 REG_WRITE(ah, AR_Q_TXD, 1 << q);
178
179 for (wait = wait_time; wait != 0; wait--) {
180 if (wait != wait_time)
181 udelay(ATH9K_TIME_QUANTUM);
182
183 if (ath9k_hw_numtxpending(ah, q) == 0)
184 break;
185 }
186
187 REG_WRITE(ah, AR_Q_TXD, 0);
188
189 return wait != 0;
190
191#undef ATH9K_TX_STOP_DMA_TIMEOUT
192#undef ATH9K_TIME_QUANTUM
193}
194EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
195
196bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
197 const struct ath9k_tx_queue_info *qinfo)
198{
199 u32 cw;
200 struct ath_common *common = ath9k_hw_common(ah);
201 struct ath9k_tx_queue_info *qi;
202
203 qi = &ah->txq[q];
204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
205 ath_dbg(common, QUEUE,
206 "Set TXQ properties, inactive queue: %u\n", q);
207 return false;
208 }
209
210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
211
212 qi->tqi_ver = qinfo->tqi_ver;
213 qi->tqi_subtype = qinfo->tqi_subtype;
214 qi->tqi_qflags = qinfo->tqi_qflags;
215 qi->tqi_priority = qinfo->tqi_priority;
216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
218 else
219 qi->tqi_aifs = INIT_AIFS;
220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
221 cw = min(qinfo->tqi_cwmin, 1024U);
222 qi->tqi_cwmin = 1;
223 while (qi->tqi_cwmin < cw)
224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
225 } else
226 qi->tqi_cwmin = qinfo->tqi_cwmin;
227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
228 cw = min(qinfo->tqi_cwmax, 1024U);
229 qi->tqi_cwmax = 1;
230 while (qi->tqi_cwmax < cw)
231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
232 } else
233 qi->tqi_cwmax = INIT_CWMAX;
234
235 if (qinfo->tqi_shretry != 0)
236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
237 else
238 qi->tqi_shretry = INIT_SH_RETRY;
239 if (qinfo->tqi_lgretry != 0)
240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
241 else
242 qi->tqi_lgretry = INIT_LG_RETRY;
243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
245 qi->tqi_burstTime = qinfo->tqi_burstTime;
246 qi->tqi_readyTime = qinfo->tqi_readyTime;
247
248 switch (qinfo->tqi_subtype) {
249 case ATH9K_WME_UPSD:
250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
252 break;
253 default:
254 break;
255 }
256
257 return true;
258}
259EXPORT_SYMBOL(ath9k_hw_set_txq_props);
260
261bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
262 struct ath9k_tx_queue_info *qinfo)
263{
264 struct ath_common *common = ath9k_hw_common(ah);
265 struct ath9k_tx_queue_info *qi;
266
267 qi = &ah->txq[q];
268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
269 ath_dbg(common, QUEUE,
270 "Get TXQ properties, inactive queue: %u\n", q);
271 return false;
272 }
273
274 qinfo->tqi_qflags = qi->tqi_qflags;
275 qinfo->tqi_ver = qi->tqi_ver;
276 qinfo->tqi_subtype = qi->tqi_subtype;
277 qinfo->tqi_qflags = qi->tqi_qflags;
278 qinfo->tqi_priority = qi->tqi_priority;
279 qinfo->tqi_aifs = qi->tqi_aifs;
280 qinfo->tqi_cwmin = qi->tqi_cwmin;
281 qinfo->tqi_cwmax = qi->tqi_cwmax;
282 qinfo->tqi_shretry = qi->tqi_shretry;
283 qinfo->tqi_lgretry = qi->tqi_lgretry;
284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
286 qinfo->tqi_burstTime = qi->tqi_burstTime;
287 qinfo->tqi_readyTime = qi->tqi_readyTime;
288
289 return true;
290}
291EXPORT_SYMBOL(ath9k_hw_get_txq_props);
292
293int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
294 const struct ath9k_tx_queue_info *qinfo)
295{
296 struct ath_common *common = ath9k_hw_common(ah);
297 struct ath9k_tx_queue_info *qi;
298 int q;
299
300 switch (type) {
301 case ATH9K_TX_QUEUE_BEACON:
302 q = ATH9K_NUM_TX_QUEUES - 1;
303 break;
304 case ATH9K_TX_QUEUE_CAB:
305 q = ATH9K_NUM_TX_QUEUES - 2;
306 break;
307 case ATH9K_TX_QUEUE_PSPOLL:
308 q = 1;
309 break;
310 case ATH9K_TX_QUEUE_UAPSD:
311 q = ATH9K_NUM_TX_QUEUES - 3;
312 break;
313 case ATH9K_TX_QUEUE_DATA:
314 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
315 if (ah->txq[q].tqi_type ==
316 ATH9K_TX_QUEUE_INACTIVE)
317 break;
318 if (q == ATH9K_NUM_TX_QUEUES) {
319 ath_err(common, "No available TX queue\n");
320 return -1;
321 }
322 break;
323 default:
324 ath_err(common, "Invalid TX queue type: %u\n", type);
325 return -1;
326 }
327
328 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
329
330 qi = &ah->txq[q];
331 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
332 ath_err(common, "TX queue: %u already active\n", q);
333 return -1;
334 }
335 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
336 qi->tqi_type = type;
337 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
338 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
339
340 return q;
341}
342EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
343
344static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q)
345{
346 ah->txok_interrupt_mask &= ~(1 << q);
347 ah->txerr_interrupt_mask &= ~(1 << q);
348 ah->txdesc_interrupt_mask &= ~(1 << q);
349 ah->txeol_interrupt_mask &= ~(1 << q);
350 ah->txurn_interrupt_mask &= ~(1 << q);
351}
352
353bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
354{
355 struct ath_common *common = ath9k_hw_common(ah);
356 struct ath9k_tx_queue_info *qi;
357
358 qi = &ah->txq[q];
359 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
360 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
361 return false;
362 }
363
364 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
365
366 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
367 ath9k_hw_clear_queue_interrupts(ah, q);
368 ath9k_hw_set_txq_interrupts(ah, qi);
369
370 return true;
371}
372EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
373
374bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
375{
376 struct ath_common *common = ath9k_hw_common(ah);
377 struct ath9k_tx_queue_info *qi;
378 u32 cwMin, chanCwMin, value;
379
380 qi = &ah->txq[q];
381 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
382 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
383 return true;
384 }
385
386 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
387
388 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
389 chanCwMin = INIT_CWMIN;
390
391 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
392 } else
393 cwMin = qi->tqi_cwmin;
394
395 ENABLE_REGWRITE_BUFFER(ah);
396
397 REG_WRITE(ah, AR_DLCL_IFS(q),
398 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
399 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
400 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
401
402 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
403 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
404 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
405 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
406
407 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
408
409 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
410 REG_WRITE(ah, AR_DMISC(q),
411 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
412 else
413 REG_WRITE(ah, AR_DMISC(q),
414 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
415
416 if (qi->tqi_cbrPeriod) {
417 REG_WRITE(ah, AR_QCBRCFG(q),
418 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
419 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
420 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
421 (qi->tqi_cbrOverflowLimit ?
422 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
423 }
424 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
425 REG_WRITE(ah, AR_QRDYTIMECFG(q),
426 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
427 AR_Q_RDYTIMECFG_EN);
428 }
429
430 REG_WRITE(ah, AR_DCHNTIME(q),
431 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
432 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
433
434 if (qi->tqi_burstTime
435 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
436 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
437
438 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
439 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
440
441 REGWRITE_BUFFER_FLUSH(ah);
442
443 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
444 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
445
446 switch (qi->tqi_type) {
447 case ATH9K_TX_QUEUE_BEACON:
448 ENABLE_REGWRITE_BUFFER(ah);
449
450 REG_SET_BIT(ah, AR_QMISC(q),
451 AR_Q_MISC_FSP_DBA_GATED
452 | AR_Q_MISC_BEACON_USE
453 | AR_Q_MISC_CBR_INCR_DIS1);
454
455 REG_SET_BIT(ah, AR_DMISC(q),
456 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
457 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
458 | AR_D_MISC_BEACON_USE
459 | AR_D_MISC_POST_FR_BKOFF_DIS);
460
461 REGWRITE_BUFFER_FLUSH(ah);
462
463
464
465
466
467
468 if (AR_SREV_9300_20_OR_LATER(ah) &&
469 ah->opmode != NL80211_IFTYPE_ADHOC) {
470 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
471 | SM(0, AR_D_LCL_IFS_CWMAX)
472 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
473 }
474 break;
475 case ATH9K_TX_QUEUE_CAB:
476 ENABLE_REGWRITE_BUFFER(ah);
477
478 REG_SET_BIT(ah, AR_QMISC(q),
479 AR_Q_MISC_FSP_DBA_GATED
480 | AR_Q_MISC_CBR_INCR_DIS1
481 | AR_Q_MISC_CBR_INCR_DIS0);
482 value = (qi->tqi_readyTime -
483 (ah->config.sw_beacon_response_time -
484 ah->config.dma_beacon_response_time) -
485 ah->config.additional_swba_backoff) * 1024;
486 REG_WRITE(ah, AR_QRDYTIMECFG(q),
487 value | AR_Q_RDYTIMECFG_EN);
488 REG_SET_BIT(ah, AR_DMISC(q),
489 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
490 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
491
492 REGWRITE_BUFFER_FLUSH(ah);
493
494 break;
495 case ATH9K_TX_QUEUE_PSPOLL:
496 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
497 break;
498 case ATH9K_TX_QUEUE_UAPSD:
499 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
500 break;
501 default:
502 break;
503 }
504
505 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
506 REG_SET_BIT(ah, AR_DMISC(q),
507 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
508 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
509 AR_D_MISC_POST_FR_BKOFF_DIS);
510 }
511
512 if (AR_SREV_9300_20_OR_LATER(ah))
513 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
514
515 ath9k_hw_clear_queue_interrupts(ah, q);
516 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
517 ah->txok_interrupt_mask |= 1 << q;
518 ah->txerr_interrupt_mask |= 1 << q;
519 }
520 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
521 ah->txdesc_interrupt_mask |= 1 << q;
522 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
523 ah->txeol_interrupt_mask |= 1 << q;
524 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
525 ah->txurn_interrupt_mask |= 1 << q;
526 ath9k_hw_set_txq_interrupts(ah, qi);
527
528 return true;
529}
530EXPORT_SYMBOL(ath9k_hw_resettxqueue);
531
532int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
533 struct ath_rx_status *rs)
534{
535 struct ar5416_desc ads;
536 struct ar5416_desc *adsp = AR5416DESC(ds);
537 u32 phyerr;
538
539 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
540 return -EINPROGRESS;
541
542 ads.u.rx = adsp->u.rx;
543
544 rs->rs_status = 0;
545 rs->rs_flags = 0;
546 rs->flag = 0;
547
548 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
549 rs->rs_tstamp = ads.AR_RcvTimestamp;
550
551 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
552 rs->rs_rssi = ATH9K_RSSI_BAD;
553 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
554 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
555 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
556 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
557 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
558 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
559 } else {
560 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
561 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
562 AR_RxRSSIAnt00);
563 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
564 AR_RxRSSIAnt01);
565 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
566 AR_RxRSSIAnt02);
567 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
568 AR_RxRSSIAnt10);
569 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
570 AR_RxRSSIAnt11);
571 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
572 AR_RxRSSIAnt12);
573 }
574 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
575 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
576 else
577 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
578
579 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
580 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
581
582 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0;
583 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
584 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
585 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
586
587
588 rs->flag |=
589 (ads.ds_rxstatus3 & AR_GI) ? RX_FLAG_SHORT_GI : 0;
590 rs->flag |=
591 (ads.ds_rxstatus3 & AR_2040) ? RX_FLAG_40MHZ : 0;
592 if (AR_SREV_9280_20_OR_LATER(ah))
593 rs->flag |=
594 (ads.ds_rxstatus3 & AR_STBC) ?
595
596 (1 << RX_FLAG_STBC_SHIFT) : 0;
597
598 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
599 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
600 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
601 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
602 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
603 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
604
605 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
606
607
608
609
610
611
612 if (ads.ds_rxstatus8 & AR_PHYErr) {
613 rs->rs_status |= ATH9K_RXERR_PHY;
614 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
615 rs->rs_phyerr = phyerr;
616 } else if (ads.ds_rxstatus8 & AR_CRCErr)
617 rs->rs_status |= ATH9K_RXERR_CRC;
618 else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
619 rs->rs_status |= ATH9K_RXERR_DECRYPT;
620 else if (ads.ds_rxstatus8 & AR_MichaelErr)
621 rs->rs_status |= ATH9K_RXERR_MIC;
622 } else {
623 if (ads.ds_rxstatus8 &
624 (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr))
625 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
626
627
628 if (rs->rs_rate >= 0x90)
629 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
630 }
631
632 if (ads.ds_rxstatus8 & AR_KeyMiss)
633 rs->rs_status |= ATH9K_RXERR_KEYMISS;
634
635 return 0;
636}
637EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
638
639
640
641
642
643
644
645
646bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
647{
648 u32 reg;
649
650 if (set) {
651 REG_SET_BIT(ah, AR_DIAG_SW,
652 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
653
654 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
655 0, AH_WAIT_TIMEOUT)) {
656 REG_CLR_BIT(ah, AR_DIAG_SW,
657 (AR_DIAG_RX_DIS |
658 AR_DIAG_RX_ABORT));
659
660 reg = REG_READ(ah, AR_OBS_BUS_1);
661 ath_err(ath9k_hw_common(ah),
662 "RX failed to go idle in 10 ms RXSM=0x%x\n",
663 reg);
664
665 return false;
666 }
667 } else {
668 REG_CLR_BIT(ah, AR_DIAG_SW,
669 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
670 }
671
672 return true;
673}
674EXPORT_SYMBOL(ath9k_hw_setrxabort);
675
676void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
677{
678 REG_WRITE(ah, AR_RXDP, rxdp);
679}
680EXPORT_SYMBOL(ath9k_hw_putrxbuf);
681
682void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
683{
684 ath9k_enable_mib_counters(ah);
685
686 ath9k_ani_reset(ah, is_scanning);
687
688 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
689}
690EXPORT_SYMBOL(ath9k_hw_startpcureceive);
691
692void ath9k_hw_abortpcurecv(struct ath_hw *ah)
693{
694 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
695
696 ath9k_hw_disable_mib_counters(ah);
697}
698EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
699
700bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
701{
702#define AH_RX_STOP_DMA_TIMEOUT 10000
703 struct ath_common *common = ath9k_hw_common(ah);
704 u32 mac_status, last_mac_status = 0;
705 int i;
706
707
708 REG_WRITE(ah, AR_MACMISC,
709 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
710 (AR_MACMISC_MISC_OBS_BUS_1 <<
711 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
712
713 REG_WRITE(ah, AR_CR, AR_CR_RXD);
714
715
716 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
717 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
718 break;
719
720 if (!AR_SREV_9300_20_OR_LATER(ah)) {
721 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
722 if (mac_status == 0x1c0 && mac_status == last_mac_status) {
723 *reset = true;
724 break;
725 }
726
727 last_mac_status = mac_status;
728 }
729
730 udelay(AH_TIME_QUANTUM);
731 }
732
733 if (i == 0) {
734 ath_err(common,
735 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
736 AH_RX_STOP_DMA_TIMEOUT / 1000,
737 REG_READ(ah, AR_CR),
738 REG_READ(ah, AR_DIAG_SW),
739 REG_READ(ah, AR_DMADBG_7));
740 return false;
741 } else {
742 return true;
743 }
744
745#undef AH_RX_STOP_DMA_TIMEOUT
746}
747EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
748
749int ath9k_hw_beaconq_setup(struct ath_hw *ah)
750{
751 struct ath9k_tx_queue_info qi;
752
753 memset(&qi, 0, sizeof(qi));
754 qi.tqi_aifs = 1;
755 qi.tqi_cwmin = 0;
756 qi.tqi_cwmax = 0;
757
758 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
759 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
760
761 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
762}
763EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
764
765bool ath9k_hw_intrpend(struct ath_hw *ah)
766{
767 u32 host_isr;
768
769 if (AR_SREV_9100(ah))
770 return true;
771
772 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
773
774 if (((host_isr & AR_INTR_MAC_IRQ) ||
775 (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
776 (host_isr != AR_INTR_SPURIOUS))
777 return true;
778
779 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
780 if ((host_isr & AR_INTR_SYNC_DEFAULT)
781 && (host_isr != AR_INTR_SPURIOUS))
782 return true;
783
784 return false;
785}
786EXPORT_SYMBOL(ath9k_hw_intrpend);
787
788void ath9k_hw_kill_interrupts(struct ath_hw *ah)
789{
790 struct ath_common *common = ath9k_hw_common(ah);
791
792 ath_dbg(common, INTERRUPT, "disable IER\n");
793 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
794 (void) REG_READ(ah, AR_IER);
795 if (!AR_SREV_9100(ah)) {
796 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
797 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
798
799 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
800 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
801 }
802}
803EXPORT_SYMBOL(ath9k_hw_kill_interrupts);
804
805void ath9k_hw_disable_interrupts(struct ath_hw *ah)
806{
807 if (!(ah->imask & ATH9K_INT_GLOBAL))
808 atomic_set(&ah->intr_ref_cnt, -1);
809 else
810 atomic_dec(&ah->intr_ref_cnt);
811
812 ath9k_hw_kill_interrupts(ah);
813}
814EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
815
816void ath9k_hw_enable_interrupts(struct ath_hw *ah)
817{
818 struct ath_common *common = ath9k_hw_common(ah);
819 u32 sync_default = AR_INTR_SYNC_DEFAULT;
820 u32 async_mask;
821
822 if (!(ah->imask & ATH9K_INT_GLOBAL))
823 return;
824
825 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
826 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
827 atomic_read(&ah->intr_ref_cnt));
828 return;
829 }
830
831 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
832 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
833
834 async_mask = AR_INTR_MAC_IRQ;
835
836 if (ah->imask & ATH9K_INT_MCI)
837 async_mask |= AR_INTR_ASYNC_MASK_MCI;
838
839 ath_dbg(common, INTERRUPT, "enable IER\n");
840 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
841 if (!AR_SREV_9100(ah)) {
842 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
843 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
844
845 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
846 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
847 }
848 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
849 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
850}
851EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
852
853void ath9k_hw_set_interrupts(struct ath_hw *ah)
854{
855 enum ath9k_int ints = ah->imask;
856 u32 mask, mask2;
857 struct ath9k_hw_capabilities *pCap = &ah->caps;
858 struct ath_common *common = ath9k_hw_common(ah);
859
860 if (!(ints & ATH9K_INT_GLOBAL))
861 ath9k_hw_disable_interrupts(ah);
862
863 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
864
865 mask = ints & ATH9K_INT_COMMON;
866 mask2 = 0;
867
868 if (ints & ATH9K_INT_TX) {
869 if (ah->config.tx_intr_mitigation)
870 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
871 else {
872 if (ah->txok_interrupt_mask)
873 mask |= AR_IMR_TXOK;
874 if (ah->txdesc_interrupt_mask)
875 mask |= AR_IMR_TXDESC;
876 }
877 if (ah->txerr_interrupt_mask)
878 mask |= AR_IMR_TXERR;
879 if (ah->txeol_interrupt_mask)
880 mask |= AR_IMR_TXEOL;
881 }
882 if (ints & ATH9K_INT_RX) {
883 if (AR_SREV_9300_20_OR_LATER(ah)) {
884 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
885 if (ah->config.rx_intr_mitigation) {
886 mask &= ~AR_IMR_RXOK_LP;
887 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
888 } else {
889 mask |= AR_IMR_RXOK_LP;
890 }
891 } else {
892 if (ah->config.rx_intr_mitigation)
893 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
894 else
895 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
896 }
897 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
898 mask |= AR_IMR_GENTMR;
899 }
900
901 if (ints & ATH9K_INT_GENTIMER)
902 mask |= AR_IMR_GENTMR;
903
904 if (ints & (ATH9K_INT_BMISC)) {
905 mask |= AR_IMR_BCNMISC;
906 if (ints & ATH9K_INT_TIM)
907 mask2 |= AR_IMR_S2_TIM;
908 if (ints & ATH9K_INT_DTIM)
909 mask2 |= AR_IMR_S2_DTIM;
910 if (ints & ATH9K_INT_DTIMSYNC)
911 mask2 |= AR_IMR_S2_DTIMSYNC;
912 if (ints & ATH9K_INT_CABEND)
913 mask2 |= AR_IMR_S2_CABEND;
914 if (ints & ATH9K_INT_TSFOOR)
915 mask2 |= AR_IMR_S2_TSFOOR;
916 }
917
918 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
919 mask |= AR_IMR_BCNMISC;
920 if (ints & ATH9K_INT_GTT)
921 mask2 |= AR_IMR_S2_GTT;
922 if (ints & ATH9K_INT_CST)
923 mask2 |= AR_IMR_S2_CST;
924 }
925
926 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
927 REG_WRITE(ah, AR_IMR, mask);
928 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
929 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
930 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
931 ah->imrs2_reg |= mask2;
932 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
933
934 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
935 if (ints & ATH9K_INT_TIM_TIMER)
936 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
937 else
938 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
939 }
940
941 return;
942}
943EXPORT_SYMBOL(ath9k_hw_set_interrupts);
944
