1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
34#include <linux/io.h>
35#include <net/mac80211.h>
36#include <net/ieee80211_radiotap.h>
37
38#include "commands.h"
39#include "csr.h"
40#include "prph.h"
41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54
55
56
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62
63#define CT_KILL_THRESHOLD_LEGACY 110
64
65
66
67
68
69
70
71
72
73
74
75
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
77
78
79
80
81
82
83
84
85
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103
104struct il_device_cmd;
105
106struct il_cmd_meta {
107
108 struct il_host_cmd *source;
109
110
111
112
113
114
115
116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
118
119
120
121 u32 flags;
122
123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
125};
126
127
128
129
130
131
132struct il_queue {
133 int n_bd;
134 int write_ptr;
135 int read_ptr;
136
137 dma_addr_t dma_addr;
138 int n_win;
139 u32 id;
140 int low_mark;
141
142 int high_mark;
143
144};
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161#define TFD_TX_CMD_SLOTS 256
162#define TFD_CMD_SLOTS 32
163
164struct il_tx_queue {
165 struct il_queue q;
166 void *tfds;
167 struct il_device_cmd **cmd;
168 struct il_cmd_meta *meta;
169 struct sk_buff **skbs;
170 unsigned long time_stamp;
171 u8 need_update;
172 u8 sched_retry;
173 u8 active;
174 u8 swq_id;
175};
176
177
178
179
180
181
182
183
184
185#define IL_EEPROM_ACCESS_TIMEOUT 5000
186
187#define IL_EEPROM_SEM_TIMEOUT 10
188#define IL_EEPROM_SEM_RETRY_LIMIT 1000
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206#define IL_NUM_TX_CALIB_GROUPS 5
207enum {
208 EEPROM_CHANNEL_VALID = (1 << 0),
209 EEPROM_CHANNEL_IBSS = (1 << 1),
210
211 EEPROM_CHANNEL_ACTIVE = (1 << 3),
212 EEPROM_CHANNEL_RADAR = (1 << 4),
213 EEPROM_CHANNEL_WIDE = (1 << 5),
214
215 EEPROM_CHANNEL_DFS = (1 << 7),
216};
217
218
219
220#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
221#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
222
223
224
225struct il_eeprom_channel {
226 u8 flags;
227 s8 max_power_avg;
228} __packed;
229
230
231#define EEPROM_3945_EEPROM_VERSION (0x2f)
232
233
234#define EEPROM_TX_POWER_TX_CHAINS (2)
235
236
237#define EEPROM_TX_POWER_BANDS (8)
238
239
240
241#define EEPROM_TX_POWER_MEASUREMENTS (3)
242
243
244
245#define EEPROM_4965_TX_POWER_VERSION (5)
246#define EEPROM_4965_EEPROM_VERSION (0x2f)
247#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6)
248#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8)
249#define EEPROM_4965_BOARD_REVISION (2*0x4F)
250#define EEPROM_4965_BOARD_PBA (2*0x56+1)
251
252
253extern const u8 il_eeprom_band_1[14];
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269struct il_eeprom_calib_measure {
270 u8 temperature;
271 u8 gain_idx;
272 u8 actual_pow;
273 s8 pa_det;
274} __packed;
275
276
277
278
279
280
281
282
283
284struct il_eeprom_calib_ch_info {
285 u8 ch_num;
286 struct il_eeprom_calib_measure
287 measurements[EEPROM_TX_POWER_TX_CHAINS]
288 [EEPROM_TX_POWER_MEASUREMENTS];
289} __packed;
290
291
292
293
294
295
296
297
298
299
300
301struct il_eeprom_calib_subband_info {
302 u8 ch_from;
303 u8 ch_to;
304 struct il_eeprom_calib_ch_info ch1;
305 struct il_eeprom_calib_ch_info ch2;
306} __packed;
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328struct il_eeprom_calib_info {
329 u8 saturation_power24;
330 u8 saturation_power52;
331 __le16 voltage;
332 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
333} __packed;
334
335
336#define EEPROM_DEVICE_ID (2*0x08)
337#define EEPROM_MAC_ADDRESS (2*0x15)
338#define EEPROM_BOARD_REVISION (2*0x35)
339#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1)
340#define EEPROM_VERSION (2*0x44)
341#define EEPROM_SKU_CAP (2*0x45)
342#define EEPROM_OEM_MODE (2*0x46)
343#define EEPROM_WOWLAN_MODE (2*0x47)
344#define EEPROM_RADIO_CONFIG (2*0x48)
345#define EEPROM_NUM_MAC_ADDRESS (2*0x4C)
346
347
348#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3)
349#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3)
350#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3)
351#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3)
352#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF)
353#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)
354
355#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
356#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
357
358
359
360
361
362
363
364
365
366
367
368
369
370#define EEPROM_REGULATORY_SKU_ID (2*0x60)
371#define EEPROM_REGULATORY_BAND_1 (2*0x62)
372#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63)
373
374
375
376
377
378
379#define EEPROM_REGULATORY_BAND_2 (2*0x71)
380#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72)
381
382
383
384
385
386#define EEPROM_REGULATORY_BAND_3 (2*0x7F)
387#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80)
388
389
390
391
392
393#define EEPROM_REGULATORY_BAND_4 (2*0x8C)
394#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D)
395
396
397
398
399
400#define EEPROM_REGULATORY_BAND_5 (2*0x98)
401#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99)
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)
419
420
421
422
423
424#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)
425
426#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
427
428int il_eeprom_init(struct il_priv *il);
429void il_eeprom_free(struct il_priv *il);
430const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
431u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
432int il_init_channel_map(struct il_priv *il);
433void il_free_channel_map(struct il_priv *il);
434const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
435 enum ieee80211_band band,
436 u16 channel);
437
438#define IL_NUM_SCAN_RATES (2)
439
440struct il4965_channel_tgd_info {
441 u8 type;
442 s8 max_power;
443};
444
445struct il4965_channel_tgh_info {
446 s64 last_radar_time;
447};
448
449#define IL4965_MAX_RATE (33)
450
451struct il3945_clip_group {
452
453
454 const s8 clip_powers[IL_MAX_RATES];
455};
456
457
458
459
460
461
462
463
464struct il3945_channel_power_info {
465 struct il3945_tx_power tpc;
466 s8 power_table_idx;
467 s8 base_power_idx;
468 s8 requested_power;
469};
470
471
472
473struct il3945_scan_power_info {
474 struct il3945_tx_power tpc;
475 s8 power_table_idx;
476 s8 requested_power;
477};
478
479
480
481
482
483
484struct il_channel_info {
485 struct il4965_channel_tgd_info tgd;
486 struct il4965_channel_tgh_info tgh;
487 struct il_eeprom_channel eeprom;
488 struct il_eeprom_channel ht40_eeprom;
489
490
491 u8 channel;
492 u8 flags;
493 s8 max_power_avg;
494 s8 curr_txpow;
495 s8 min_power;
496 s8 scan_power;
497
498 u8 group_idx;
499 u8 band_idx;
500 enum ieee80211_band band;
501
502
503 s8 ht40_max_power_avg;
504 u8 ht40_flags;
505 u8 ht40_extension_channel;
506
507
508
509
510 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
511
512
513 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
514};
515
516#define IL_TX_FIFO_BK 0
517#define IL_TX_FIFO_BE 1
518#define IL_TX_FIFO_VI 2
519#define IL_TX_FIFO_VO 3
520#define IL_TX_FIFO_UNUSED -1
521
522
523
524
525#define IL_MIN_NUM_QUEUES 10
526
527#define IL_DEFAULT_CMD_QUEUE_NUM 4
528
529#define IEEE80211_DATA_LEN 2304
530#define IEEE80211_4ADDR_LEN 30
531#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
532#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
533
534struct il_frame {
535 union {
536 struct ieee80211_hdr frame;
537 struct il_tx_beacon_cmd beacon;
538 u8 raw[IEEE80211_FRAME_LEN];
539 u8 cmd[360];
540 } u;
541 struct list_head list;
542};
543
544enum {
545 CMD_SYNC = 0,
546 CMD_SIZE_NORMAL = 0,
547 CMD_NO_SKB = 0,
548 CMD_SIZE_HUGE = (1 << 0),
549 CMD_ASYNC = (1 << 1),
550 CMD_WANT_SKB = (1 << 2),
551 CMD_MAPPED = (1 << 3),
552};
553
554#define DEF_CMD_PAYLOAD_SIZE 320
555
556
557
558
559
560
561
562
563struct il_device_cmd {
564 struct il_cmd_header hdr;
565 union {
566 u32 flags;
567 u8 val8;
568 u16 val16;
569 u32 val32;
570 struct il_tx_cmd tx;
571 u8 payload[DEF_CMD_PAYLOAD_SIZE];
572 } __packed cmd;
573} __packed;
574
575#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
576
577struct il_host_cmd {
578 const void *data;
579 unsigned long reply_page;
580 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
581 struct il_rx_pkt *pkt);
582 u32 flags;
583 u16 len;
584 u8 id;
585};
586
587#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
588#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
589#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606struct il_rx_queue {
607 __le32 *bd;
608 dma_addr_t bd_dma;
609 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
610 struct il_rx_buf *queue[RX_QUEUE_SIZE];
611 u32 read;
612 u32 write;
613 u32 free_count;
614 u32 write_actual;
615 struct list_head rx_free;
616 struct list_head rx_used;
617 int need_update;
618 struct il_rb_status *rb_stts;
619 dma_addr_t rb_stts_dma;
620 spinlock_t lock;
621};
622
623#define IL_SUPPORTED_RATES_IE_LEN 8
624
625#define MAX_TID_COUNT 9
626
627#define IL_INVALID_RATE 0xFF
628#define IL_INVALID_VALUE -1
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644struct il_ht_agg {
645 u16 txq_id;
646 u16 frame_count;
647 u16 wait_for_ba;
648 u16 start_idx;
649 u64 bitmap;
650 u32 rate_n_flags;
651#define IL_AGG_OFF 0
652#define IL_AGG_ON 1
653#define IL_EMPTYING_HW_QUEUE_ADDBA 2
654#define IL_EMPTYING_HW_QUEUE_DELBA 3
655 u8 state;
656};
657
658struct il_tid_data {
659 u16 seq_number;
660 u16 tfds_in_queue;
661 struct il_ht_agg agg;
662};
663
664struct il_hw_key {
665 u32 cipher;
666 int keylen;
667 u8 keyidx;
668 u8 key[32];
669};
670
671union il_ht_rate_supp {
672 u16 rates;
673 struct {
674 u8 siso_rate;
675 u8 mimo_rate;
676 };
677};
678
679#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
680#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
681#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
682#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
683#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
684#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
685#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
686
687
688
689
690
691
692
693
694#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
695#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
696#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
697#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
698#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
699#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
700#define CFG_HT_MPDU_DENSITY_MIN (0x1)
701
702struct il_ht_config {
703 bool single_chain_sufficient;
704 enum ieee80211_smps_mode smps;
705};
706
707
708struct il_qos_info {
709 int qos_active;
710 struct il_qosparam_cmd def_qos_parm;
711};
712
713
714
715
716
717
718
719struct il_station_entry {
720 struct il_addsta_cmd sta;
721 struct il_tid_data tid[MAX_TID_COUNT];
722 u8 used;
723 struct il_hw_key keyinfo;
724 struct il_link_quality_cmd *lq;
725};
726
727struct il_station_priv_common {
728 u8 sta_id;
729};
730
731
732
733
734
735
736
737struct il_vif_priv {
738 u8 ibss_bssid_sta_id;
739};
740
741
742struct fw_desc {
743 void *v_addr;
744 dma_addr_t p_addr;
745 u32 len;
746};
747
748
749struct il_ucode_header {
750 __le32 ver;
751 struct {
752 __le32 inst_size;
753 __le32 data_size;
754 __le32 init_size;
755 __le32 init_data_size;
756 __le32 boot_size;
757 u8 data[0];
758 } v1;
759};
760
761struct il4965_ibss_seq {
762 u8 mac[ETH_ALEN];
763 u16 seq_num;
764 u16 frag_num;
765 unsigned long packet_time;
766 struct list_head list;
767};
768
769struct il_sensitivity_ranges {
770 u16 min_nrg_cck;
771 u16 max_nrg_cck;
772
773 u16 nrg_th_cck;
774 u16 nrg_th_ofdm;
775
776 u16 auto_corr_min_ofdm;
777 u16 auto_corr_min_ofdm_mrc;
778 u16 auto_corr_min_ofdm_x1;
779 u16 auto_corr_min_ofdm_mrc_x1;
780
781 u16 auto_corr_max_ofdm;
782 u16 auto_corr_max_ofdm_mrc;
783 u16 auto_corr_max_ofdm_x1;
784 u16 auto_corr_max_ofdm_mrc_x1;
785
786 u16 auto_corr_max_cck;
787 u16 auto_corr_max_cck_mrc;
788 u16 auto_corr_min_cck;
789 u16 auto_corr_min_cck_mrc;
790
791 u16 barker_corr_th_min;
792 u16 barker_corr_th_min_mrc;
793 u16 nrg_th_cca;
794};
795
796#define KELVIN_TO_CELSIUS(x) ((x)-273)
797#define CELSIUS_TO_KELVIN(x) ((x)+273)
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821struct il_hw_params {
822 u8 bcast_id;
823 u8 max_txq_num;
824 u8 dma_chnl_num;
825 u16 scd_bc_tbls_size;
826 u32 tfd_size;
827 u8 tx_chains_num;
828 u8 rx_chains_num;
829 u8 valid_tx_ant;
830 u8 valid_rx_ant;
831 u16 max_rxq_size;
832 u16 max_rxq_log;
833 u32 rx_page_order;
834 u32 rx_wrt_ptr_reg;
835 u8 max_stations;
836 u8 ht40_channel;
837 u8 max_beacon_itrvl;
838 u32 max_inst_size;
839 u32 max_data_size;
840 u32 max_bsm_size;
841 u32 ct_kill_threshold;
842 u16 beacon_time_tsf_bits;
843 const struct il_sensitivity_ranges *sens;
844};
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861void il4965_update_chain_flags(struct il_priv *il);
862extern const u8 il_bcast_addr[ETH_ALEN];
863int il_queue_space(const struct il_queue *q);
864static inline int
865il_queue_used(const struct il_queue *q, int i)
866{
867 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
868 i < q->write_ptr) : !(i <
869 q->read_ptr
870 && i >=
871 q->
872 write_ptr);
873}
874
875static inline u8
876il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
877{
878
879
880
881
882
883 if (is_huge)
884 return q->n_win;
885
886
887 return idx & (q->n_win - 1);
888}
889
890struct il_dma_ptr {
891 dma_addr_t dma;
892 void *addr;
893 size_t size;
894};
895
896#define IL_OPERATION_MODE_AUTO 0
897#define IL_OPERATION_MODE_HT_ONLY 1
898#define IL_OPERATION_MODE_MIXED 2
899#define IL_OPERATION_MODE_20MHZ 3
900
901#define IL_TX_CRC_SIZE 4
902#define IL_TX_DELIMITER_SIZE 4
903
904#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
905
906
907#define INITIALIZATION_VALUE 0xFFFF
908#define IL4965_CAL_NUM_BEACONS 20
909#define IL_CAL_NUM_BEACONS 16
910#define MAXIMUM_ALLOWED_PATHLOSS 15
911
912#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
913
914#define MAX_FA_OFDM 50
915#define MIN_FA_OFDM 5
916#define MAX_FA_CCK 50
917#define MIN_FA_CCK 5
918
919#define AUTO_CORR_STEP_OFDM 1
920
921#define AUTO_CORR_STEP_CCK 3
922#define AUTO_CORR_MAX_TH_CCK 160
923
924#define NRG_DIFF 2
925#define NRG_STEP_CCK 2
926#define NRG_MARGIN 8
927#define MAX_NUMBER_CCK_NO_FA 100
928
929#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
930
931#define CHAIN_A 0
932#define CHAIN_B 1
933#define CHAIN_C 2
934#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
935#define ALL_BAND_FILTER 0xFF00
936#define IN_BAND_FILTER 0xFF
937#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
938
939#define NRG_NUM_PREV_STAT_L 20
940#define NUM_RX_CHAINS 3
941
942enum il4965_false_alarm_state {
943 IL_FA_TOO_MANY = 0,
944 IL_FA_TOO_FEW = 1,
945 IL_FA_GOOD_RANGE = 2,
946};
947
948enum il4965_chain_noise_state {
949 IL_CHAIN_NOISE_ALIVE = 0,
950 IL_CHAIN_NOISE_ACCUMULATE,
951 IL_CHAIN_NOISE_CALIBRATED,
952 IL_CHAIN_NOISE_DONE,
953};
954
955enum ucode_type {
956 UCODE_NONE = 0,
957 UCODE_INIT,
958 UCODE_RT
959};
960
961
962struct il_sensitivity_data {
963 u32 auto_corr_ofdm;
964 u32 auto_corr_ofdm_mrc;
965 u32 auto_corr_ofdm_x1;
966 u32 auto_corr_ofdm_mrc_x1;
967 u32 auto_corr_cck;
968 u32 auto_corr_cck_mrc;
969
970 u32 last_bad_plcp_cnt_ofdm;
971 u32 last_fa_cnt_ofdm;
972 u32 last_bad_plcp_cnt_cck;
973 u32 last_fa_cnt_cck;
974
975 u32 nrg_curr_state;
976 u32 nrg_prev_state;
977 u32 nrg_value[10];
978 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
979 u32 nrg_silence_ref;
980 u32 nrg_energy_idx;
981 u32 nrg_silence_idx;
982 u32 nrg_th_cck;
983 s32 nrg_auto_corr_silence_diff;
984 u32 num_in_cck_no_fa;
985 u32 nrg_th_ofdm;
986
987 u16 barker_corr_th_min;
988 u16 barker_corr_th_min_mrc;
989 u16 nrg_th_cca;
990};
991
992
993struct il_chain_noise_data {
994 u32 active_chains;
995 u32 chain_noise_a;
996 u32 chain_noise_b;
997 u32 chain_noise_c;
998 u32 chain_signal_a;
999 u32 chain_signal_b;
1000 u32 chain_signal_c;
1001 u16 beacon_count;
1002 u8 disconn_array[NUM_RX_CHAINS];
1003 u8 delta_gain_code[NUM_RX_CHAINS];
1004 u8 radio_write;
1005 u8 state;
1006};
1007
1008#define EEPROM_SEM_TIMEOUT 10
1009#define EEPROM_SEM_RETRY_LIMIT 1000
1010
1011#define IL_TRAFFIC_ENTRIES (256)
1012#define IL_TRAFFIC_ENTRY_SIZE (64)
1013
1014enum {
1015 MEASUREMENT_READY = (1 << 0),
1016 MEASUREMENT_ACTIVE = (1 << 1),
1017};
1018
1019
1020struct isr_stats {
1021 u32 hw;
1022 u32 sw;
1023 u32 err_code;
1024 u32 sch;
1025 u32 alive;
1026 u32 rfkill;
1027 u32 ctkill;
1028 u32 wakeup;
1029 u32 rx;
1030 u32 handlers[IL_CN_MAX];
1031 u32 tx;
1032 u32 unhandled;
1033};
1034
1035
1036enum il_mgmt_stats {
1037 MANAGEMENT_ASSOC_REQ = 0,
1038 MANAGEMENT_ASSOC_RESP,
1039 MANAGEMENT_REASSOC_REQ,
1040 MANAGEMENT_REASSOC_RESP,
1041 MANAGEMENT_PROBE_REQ,
1042 MANAGEMENT_PROBE_RESP,
1043 MANAGEMENT_BEACON,
1044 MANAGEMENT_ATIM,
1045 MANAGEMENT_DISASSOC,
1046 MANAGEMENT_AUTH,
1047 MANAGEMENT_DEAUTH,
1048 MANAGEMENT_ACTION,
1049 MANAGEMENT_MAX,
1050};
1051
1052enum il_ctrl_stats {
1053 CONTROL_BACK_REQ = 0,
1054 CONTROL_BACK,
1055 CONTROL_PSPOLL,
1056 CONTROL_RTS,
1057 CONTROL_CTS,
1058 CONTROL_ACK,
1059 CONTROL_CFEND,
1060 CONTROL_CFENDACK,
1061 CONTROL_MAX,
1062};
1063
1064struct traffic_stats {
1065#ifdef CONFIG_IWLEGACY_DEBUGFS
1066 u32 mgmt[MANAGEMENT_MAX];
1067 u32 ctrl[CONTROL_MAX];
1068 u32 data_cnt;
1069 u64 data_bytes;
1070#endif
1071};
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1082#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1083#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1084#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1085#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1086#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1087
1088#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1089
1090
1091#define IL_DEF_WD_TIMEOUT (2000)
1092#define IL_LONG_WD_TIMEOUT (10000)
1093#define IL_MAX_WD_TIMEOUT (120000)
1094
1095struct il_force_reset {
1096 int reset_request_count;
1097 int reset_success_count;
1098 int reset_reject_count;
1099 unsigned long reset_duration;
1100 unsigned long last_force_reset_jiffies;
1101};
1102
1103
1104
1105
1106
1107
1108
1109#define IL3945_EXT_BEACON_TIME_POS 24
1110
1111
1112
1113
1114
1115#define IL4965_EXT_BEACON_TIME_POS 22
1116
1117struct il_rxon_context {
1118 struct ieee80211_vif *vif;
1119};
1120
1121struct il_power_mgr {
1122 struct il_powertable_cmd sleep_cmd;
1123 struct il_powertable_cmd sleep_cmd_next;
1124 int debug_sleep_level_override;
1125 bool pci_pm;
1126};
1127
1128struct il_priv {
1129 struct ieee80211_hw *hw;
1130 struct ieee80211_channel *ieee_channels;
1131 struct ieee80211_rate *ieee_rates;
1132
1133 struct il_cfg *cfg;
1134 const struct il_ops *ops;
1135#ifdef CONFIG_IWLEGACY_DEBUGFS
1136 const struct il_debugfs_ops *debugfs_ops;
1137#endif
1138
1139
1140 struct list_head free_frames;
1141 int frames_count;
1142
1143 enum ieee80211_band band;
1144 int alloc_rxb_page;
1145
1146 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1147 struct il_rx_buf *rxb);
1148
1149 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1150
1151
1152 struct il_spectrum_notification measure_report;
1153 u8 measurement_status;
1154
1155
1156 u32 ucode_beacon_time;
1157 int missed_beacon_threshold;
1158
1159
1160 u32 ibss_manager;
1161
1162
1163 struct il_force_reset force_reset;
1164
1165
1166
1167 struct il_channel_info *channel_info;
1168 u8 channel_count;
1169
1170
1171 s32 temperature;
1172 s32 last_temperature;
1173
1174
1175 unsigned long scan_start;
1176 unsigned long scan_start_tsf;
1177 void *scan_cmd;
1178 enum ieee80211_band scan_band;
1179 struct cfg80211_scan_request *scan_request;
1180 struct ieee80211_vif *scan_vif;
1181 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1182 u8 mgmt_tx_ant;
1183
1184
1185 spinlock_t lock;
1186 spinlock_t hcmd_lock;
1187 spinlock_t reg_lock;
1188 struct mutex mutex;
1189
1190
1191 struct pci_dev *pci_dev;
1192
1193
1194 void __iomem *hw_base;
1195 u32 hw_rev;
1196 u32 hw_wa_rev;
1197 u8 rev_id;
1198
1199
1200 u8 cmd_queue;
1201
1202
1203 u8 sta_key_max_num;
1204
1205
1206 struct mac_address addresses[1];
1207
1208
1209 int fw_idx;
1210 u32 ucode_ver;
1211
1212 struct fw_desc ucode_code;
1213 struct fw_desc ucode_data;
1214 struct fw_desc ucode_data_backup;
1215 struct fw_desc ucode_init;
1216 struct fw_desc ucode_init_data;
1217 struct fw_desc ucode_boot;
1218 enum ucode_type ucode_type;
1219 u8 ucode_write_complete;
1220 char firmware_name[25];
1221
1222 struct ieee80211_vif *vif;
1223
1224 struct il_qos_info qos_data;
1225
1226 struct {
1227 bool enabled;
1228 bool is_40mhz;
1229 bool non_gf_sta_present;
1230 u8 protection;
1231 u8 extension_chan_offset;
1232 } ht;
1233
1234
1235
1236
1237
1238
1239
1240 const struct il_rxon_cmd active;
1241 struct il_rxon_cmd staging;
1242
1243 struct il_rxon_time_cmd timing;
1244
1245 __le16 switch_channel;
1246
1247
1248
1249 struct il_init_alive_resp card_alive_init;
1250 struct il_alive_resp card_alive;
1251
1252 u16 active_rate;
1253
1254 u8 start_calib;
1255 struct il_sensitivity_data sensitivity_data;
1256 struct il_chain_noise_data chain_noise_data;
1257 __le16 sensitivity_tbl[HD_TBL_SIZE];
1258
1259 struct il_ht_config current_ht_config;
1260
1261
1262 u8 retry_rate;
1263
1264 wait_queue_head_t wait_command_queue;
1265
1266 int activity_timer_active;
1267
1268
1269 struct il_rx_queue rxq;
1270 struct il_tx_queue *txq;
1271 unsigned long txq_ctx_active_msk;
1272 struct il_dma_ptr kw;
1273 struct il_dma_ptr scd_bc_tbls;
1274
1275 u32 scd_base_addr;
1276
1277 unsigned long status;
1278
1279
1280 struct traffic_stats tx_stats;
1281 struct traffic_stats rx_stats;
1282
1283
1284 struct isr_stats isr_stats;
1285
1286 struct il_power_mgr power_data;
1287
1288
1289 u8 bssid[ETH_ALEN];
1290
1291
1292
1293
1294 spinlock_t sta_lock;
1295 int num_stations;
1296 struct il_station_entry stations[IL_STATION_COUNT];
1297 unsigned long ucode_key_table;
1298
1299
1300#define IL_MAX_HW_QUEUES 32
1301 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1302#define IL_STOP_REASON_PASSIVE 0
1303 unsigned long stop_reason;
1304
1305 atomic_t queue_stop_count[4];
1306
1307
1308 u8 is_open;
1309
1310 u8 mac80211_registered;
1311
1312
1313 u8 *eeprom;
1314 struct il_eeprom_calib_info *calib_info;
1315
1316 enum nl80211_iftype iw_mode;
1317
1318
1319 u64 timestamp;
1320
1321 union {
1322#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1323 struct {
1324 void *shared_virt;
1325 dma_addr_t shared_phys;
1326
1327 struct delayed_work thermal_periodic;
1328 struct delayed_work rfkill_poll;
1329
1330 struct il3945_notif_stats stats;
1331#ifdef CONFIG_IWLEGACY_DEBUGFS
1332 struct il3945_notif_stats accum_stats;
1333 struct il3945_notif_stats delta_stats;
1334 struct il3945_notif_stats max_delta;
1335#endif
1336
1337 u32 sta_supp_rates;
1338 int last_rx_rssi;
1339
1340
1341 u32 last_beacon_time;
1342 u64 last_tsf;
1343
1344
1345
1346
1347
1348
1349 const struct il3945_clip_group clip_groups[5];
1350
1351 } _3945;
1352#endif
1353#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1354 struct {
1355 struct il_rx_phy_res last_phy_res;
1356 bool last_phy_res_valid;
1357 u32 ampdu_ref;
1358
1359 struct completion firmware_loading_complete;
1360
1361
1362
1363
1364
1365
1366 u8 phy_calib_chain_noise_reset_cmd;
1367 u8 phy_calib_chain_noise_gain_cmd;
1368
1369 u8 key_mapping_keys;
1370 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1371
1372 struct il_notif_stats stats;
1373#ifdef CONFIG_IWLEGACY_DEBUGFS
1374 struct il_notif_stats accum_stats;
1375 struct il_notif_stats delta_stats;
1376 struct il_notif_stats max_delta;
1377#endif
1378
1379 } _4965;
1380#endif
1381 };
1382
1383 struct il_hw_params hw_params;
1384
1385 u32 inta_mask;
1386
1387 struct workqueue_struct *workqueue;
1388
1389 struct work_struct restart;
1390 struct work_struct scan_completed;
1391 struct work_struct rx_replenish;
1392 struct work_struct abort_scan;
1393
1394 bool beacon_enabled;
1395 struct sk_buff *beacon_skb;
1396
1397 struct work_struct tx_flush;
1398
1399 struct tasklet_struct irq_tasklet;
1400
1401 struct delayed_work init_alive_start;
1402 struct delayed_work alive_start;
1403 struct delayed_work scan_check;
1404
1405
1406 s8 tx_power_user_lmt;
1407 s8 tx_power_device_lmt;
1408 s8 tx_power_next;
1409
1410#ifdef CONFIG_IWLEGACY_DEBUG
1411
1412 u32 debug_level;
1413
1414#endif
1415#ifdef CONFIG_IWLEGACY_DEBUGFS
1416
1417 u16 tx_traffic_idx;
1418 u16 rx_traffic_idx;
1419 u8 *tx_traffic;
1420 u8 *rx_traffic;
1421 struct dentry *debugfs_dir;
1422 u32 dbgfs_sram_offset, dbgfs_sram_len;
1423 bool disable_ht40;
1424#endif
1425
1426 struct work_struct txpower_work;
1427 u32 disable_sens_cal;
1428 u32 disable_chain_noise_cal;
1429 u32 disable_tx_power_cal;
1430 struct work_struct run_time_calib_work;
1431 struct timer_list stats_periodic;
1432 struct timer_list watchdog;
1433 bool hw_ready;
1434
1435 struct led_classdev led;
1436 unsigned long blink_on, blink_off;
1437 bool led_registered;
1438};
1439
1440static inline void
1441il_txq_ctx_activate(struct il_priv *il, int txq_id)
1442{
1443 set_bit(txq_id, &il->txq_ctx_active_msk);
1444}
1445
1446static inline void
1447il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1448{
1449 clear_bit(txq_id, &il->txq_ctx_active_msk);
1450}
1451
1452static inline int
1453il_is_associated(struct il_priv *il)
1454{
1455 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1456}
1457
1458static inline int
1459il_is_any_associated(struct il_priv *il)
1460{
1461 return il_is_associated(il);
1462}
1463
1464static inline int
1465il_is_channel_valid(const struct il_channel_info *ch_info)
1466{
1467 if (ch_info == NULL)
1468 return 0;
1469 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1470}
1471
1472static inline int
1473il_is_channel_radar(const struct il_channel_info *ch_info)
1474{
1475 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1476}
1477
1478static inline u8
1479il_is_channel_a_band(const struct il_channel_info *ch_info)
1480{
1481 return ch_info->band == IEEE80211_BAND_5GHZ;
1482}
1483
1484static inline int
1485il_is_channel_passive(const struct il_channel_info *ch)
1486{
1487 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1488}
1489
1490static inline int
1491il_is_channel_ibss(const struct il_channel_info *ch)
1492{
1493 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1494}
1495
1496static inline void
1497__il_free_pages(struct il_priv *il, struct page *page)
1498{
1499 __free_pages(page, il->hw_params.rx_page_order);
1500 il->alloc_rxb_page--;
1501}
1502
1503static inline void
1504il_free_pages(struct il_priv *il, unsigned long page)
1505{
1506 free_pages(page, il->hw_params.rx_page_order);
1507 il->alloc_rxb_page--;
1508}
1509
1510#define IWLWIFI_VERSION "in-tree:"
1511#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1512#define DRV_AUTHOR "<ilw@linux.intel.com>"
1513
1514#define IL_PCI_DEVICE(dev, subdev, cfg) \
1515 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1516 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1517 .driver_data = (kernel_ulong_t)&(cfg)
1518
1519#define TIME_UNIT 1024
1520
1521#define IL_SKU_G 0x1
1522#define IL_SKU_A 0x2
1523#define IL_SKU_N 0x8
1524
1525#define IL_CMD(x) case x: return #x
1526
1527
1528#define IL_RX_BUF_SIZE_3K (3 * 1000)
1529#define IL_RX_BUF_SIZE_4K (4 * 1024)
1530#define IL_RX_BUF_SIZE_8K (8 * 1024)
1531
1532#ifdef CONFIG_IWLEGACY_DEBUGFS
1533struct il_debugfs_ops {
1534 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1535 size_t count, loff_t *ppos);
1536 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1537 size_t count, loff_t *ppos);
1538 ssize_t(*general_stats_read) (struct file *file,
1539 char __user *user_buf, size_t count,
1540 loff_t *ppos);
1541};
1542#endif
1543
1544struct il_ops {
1545
1546 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1547 struct il_tx_queue *txq,
1548 u16 byte_cnt);
1549 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1550 struct il_tx_queue *txq, dma_addr_t addr,
1551 u16 len, u8 reset, u8 pad);
1552 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1553 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1554
1555 void (*init_alive_start) (struct il_priv *il);
1556
1557 int (*is_valid_rtc_data_addr) (u32 addr);
1558
1559 int (*load_ucode) (struct il_priv *il);
1560
1561 void (*dump_nic_error_log) (struct il_priv *il);
1562 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1563 int (*set_channel_switch) (struct il_priv *il,
1564 struct ieee80211_channel_switch *ch_switch);
1565
1566 int (*apm_init) (struct il_priv *il);
1567
1568
1569 int (*send_tx_power) (struct il_priv *il);
1570 void (*update_chain_flags) (struct il_priv *il);
1571
1572
1573 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1574 void (*eeprom_release_semaphore) (struct il_priv *il);
1575
1576 int (*rxon_assoc) (struct il_priv *il);
1577 int (*commit_rxon) (struct il_priv *il);
1578 void (*set_rxon_chain) (struct il_priv *il);
1579
1580 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1581 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1582
1583 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1584 void (*post_scan) (struct il_priv *il);
1585 void (*post_associate) (struct il_priv *il);
1586 void (*config_ap) (struct il_priv *il);
1587
1588 int (*update_bcast_stations) (struct il_priv *il);
1589 int (*manage_ibss_station) (struct il_priv *il,
1590 struct ieee80211_vif *vif, bool add);
1591
1592 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1593};
1594
1595struct il_mod_params {
1596 int sw_crypto;
1597 int disable_hw_scan;
1598 int num_of_queues;
1599 int disable_11n;
1600 int amsdu_size_8K;
1601 int antenna;
1602 int restart_fw;
1603};
1604
1605#define IL_LED_SOLID 11
1606#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1607
1608#define IL_LED_ACTIVITY (0<<1)
1609#define IL_LED_LINK (1<<1)
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619enum il_led_mode {
1620 IL_LED_DEFAULT,
1621 IL_LED_RF_STATE,
1622 IL_LED_BLINK,
1623};
1624
1625void il_leds_init(struct il_priv *il);
1626void il_leds_exit(struct il_priv *il);
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659struct il_cfg {
1660
1661 const char *name;
1662 const char *fw_name_pre;
1663 const unsigned int ucode_api_max;
1664 const unsigned int ucode_api_min;
1665 u8 valid_tx_ant;
1666 u8 valid_rx_ant;
1667 unsigned int sku;
1668 u16 eeprom_ver;
1669 u16 eeprom_calib_ver;
1670
1671 const struct il_mod_params *mod_params;
1672
1673 struct il_base_params *base_params;
1674
1675 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
1676 enum il_led_mode led_mode;
1677
1678 int eeprom_size;
1679 int num_of_queues;
1680 int num_of_ampdu_queues;
1681
1682 u32 pll_cfg_val;
1683 bool set_l0s;
1684 bool use_bsm;
1685
1686 u16 led_compensation;
1687 int chain_noise_num_beacons;
1688 unsigned int wd_timeout;
1689 bool temperature_kelvin;
1690 const bool ucode_tracing;
1691 const bool sensitivity_calib_by_driver;
1692 const bool chain_noise_calib_by_driver;
1693
1694 const u32 regulatory_bands[7];
1695};
1696
1697
1698
1699
1700
1701int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1702 u16 queue, const struct ieee80211_tx_queue_params *params);
1703int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1704
1705void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1706int il_check_rxon_cmd(struct il_priv *il);
1707int il_full_rxon_required(struct il_priv *il);
1708int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1709void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1710 struct ieee80211_vif *vif);
1711u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1712void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1713bool il_is_ht40_tx_allowed(struct il_priv *il,
1714 struct ieee80211_sta_ht_cap *ht_cap);
1715void il_connection_init_rx_config(struct il_priv *il);
1716void il_set_rate(struct il_priv *il);
1717int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1718 u32 decrypt_res, struct ieee80211_rx_status *stats);
1719void il_irq_handle_error(struct il_priv *il);
1720int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1721void il_mac_remove_interface(struct ieee80211_hw *hw,
1722 struct ieee80211_vif *vif);
1723int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1724 enum nl80211_iftype newtype, bool newp2p);
1725void il_mac_flush(struct ieee80211_hw *hw, u32 queues, bool drop);
1726int il_alloc_txq_mem(struct il_priv *il);
1727void il_free_txq_mem(struct il_priv *il);
1728
1729#ifdef CONFIG_IWLEGACY_DEBUGFS
1730void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1731#else
1732static inline void
1733il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1734{
1735}
1736#endif
1737
1738
1739
1740
1741void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1742void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1743void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1744void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1745
1746
1747
1748
1749void il_cmd_queue_unmap(struct il_priv *il);
1750void il_cmd_queue_free(struct il_priv *il);
1751int il_rx_queue_alloc(struct il_priv *il);
1752void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1753int il_rx_queue_space(const struct il_rx_queue *q);
1754void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1755
1756void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1757void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1758void il_chswitch_done(struct il_priv *il, bool is_success);
1759
1760
1761
1762
1763void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1764int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1765void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1766void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1767void il_tx_queue_free(struct il_priv *il, int txq_id);
1768void il_setup_watchdog(struct il_priv *il);
1769
1770
1771
1772int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1773
1774
1775
1776
1777
1778u8 il_get_lowest_plcp(struct il_priv *il);
1779
1780
1781
1782
1783void il_init_scan_params(struct il_priv *il);
1784int il_scan_cancel(struct il_priv *il);
1785int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1786void il_force_scan_end(struct il_priv *il);
1787int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1788 struct cfg80211_scan_request *req);
1789void il_internal_short_hw_scan(struct il_priv *il);
1790int il_force_reset(struct il_priv *il, bool external);
1791u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1792 const u8 *ta, const u8 *ie, int ie_len, int left);
1793void il_setup_rx_scan_handlers(struct il_priv *il);
1794u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1795 u8 n_probes);
1796u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1797 struct ieee80211_vif *vif);
1798void il_setup_scan_deferred_work(struct il_priv *il);
1799void il_cancel_scan_deferred_work(struct il_priv *il);
1800
1801
1802
1803
1804
1805
1806
1807#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10)
1808#define IL_PLCP_QUIET_THRESH cpu_to_le16(1)
1809
1810#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1811
1812
1813
1814
1815
1816const char *il_get_cmd_string(u8 cmd);
1817int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1818int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1819int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1820 const void *data);
1821int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1822 void (*callback) (struct il_priv *il,
1823 struct il_device_cmd *cmd,
1824 struct il_rx_pkt *pkt));
1825
1826int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1827
1828
1829
1830
1831
1832void il_bg_watchdog(unsigned long data);
1833u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1834__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1835 u32 beacon_interval);
1836
1837#ifdef CONFIG_PM_SLEEP
1838extern const struct dev_pm_ops il_pm_ops;
1839
1840#define IL_LEGACY_PM_OPS (&il_pm_ops)
1841
1842#else
1843
1844#define IL_LEGACY_PM_OPS NULL
1845
1846#endif
1847
1848
1849
1850
1851void il4965_dump_nic_error_log(struct il_priv *il);
1852#ifdef CONFIG_IWLEGACY_DEBUG
1853void il_print_rx_config_cmd(struct il_priv *il);
1854#else
1855static inline void
1856il_print_rx_config_cmd(struct il_priv *il)
1857{
1858}
1859#endif
1860
1861void il_clear_isr_stats(struct il_priv *il);
1862
1863
1864
1865
1866int il_init_geos(struct il_priv *il);
1867void il_free_geos(struct il_priv *il);
1868
1869
1870
1871#define S_HCMD_ACTIVE 0
1872
1873#define S_INT_ENABLED 2
1874#define S_RFKILL 3
1875#define S_CT_KILL 4
1876#define S_INIT 5
1877#define S_ALIVE 6
1878#define S_READY 7
1879#define S_TEMPERATURE 8
1880#define S_GEO_CONFIGURED 9
1881#define S_EXIT_PENDING 10
1882#define S_STATS 12
1883#define S_SCANNING 13
1884#define S_SCAN_ABORTING 14
1885#define S_SCAN_HW 15
1886#define S_POWER_PMI 16
1887#define S_FW_ERROR 17
1888#define S_CHANNEL_SWITCH_PENDING 18
1889
1890static inline int
1891il_is_ready(struct il_priv *il)
1892{
1893
1894
1895 return test_bit(S_READY, &il->status) &&
1896 test_bit(S_GEO_CONFIGURED, &il->status) &&
1897 !test_bit(S_EXIT_PENDING, &il->status);
1898}
1899
1900static inline int
1901il_is_alive(struct il_priv *il)
1902{
1903 return test_bit(S_ALIVE, &il->status);
1904}
1905
1906static inline int
1907il_is_init(struct il_priv *il)
1908{
1909 return test_bit(S_INIT, &il->status);
1910}
1911
1912static inline int
1913il_is_rfkill(struct il_priv *il)
1914{
1915 return test_bit(S_RFKILL, &il->status);
1916}
1917
1918static inline int
1919il_is_ctkill(struct il_priv *il)
1920{
1921 return test_bit(S_CT_KILL, &il->status);
1922}
1923
1924static inline int
1925il_is_ready_rf(struct il_priv *il)
1926{
1927
1928 if (il_is_rfkill(il))
1929 return 0;
1930
1931 return il_is_ready(il);
1932}
1933
1934void il_send_bt_config(struct il_priv *il);
1935int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1936void il_apm_stop(struct il_priv *il);
1937void _il_apm_stop(struct il_priv *il);
1938
1939int il_apm_init(struct il_priv *il);
1940
1941int il_send_rxon_timing(struct il_priv *il);
1942
1943static inline int
1944il_send_rxon_assoc(struct il_priv *il)
1945{
1946 return il->ops->rxon_assoc(il);
1947}
1948
1949static inline int
1950il_commit_rxon(struct il_priv *il)
1951{
1952 return il->ops->commit_rxon(il);
1953}
1954
1955static inline const struct ieee80211_supported_band *
1956il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
1957{
1958 return il->hw->wiphy->bands[band];
1959}
1960
1961
1962int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1963void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1964void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1965 struct ieee80211_bss_conf *bss_conf, u32 changes);
1966void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1967 __le16 fc, __le32 *tx_flags);
1968
1969irqreturn_t il_isr(int irq, void *data);
1970
1971void il_set_bit(struct il_priv *p, u32 r, u32 m);
1972void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1973bool _il_grab_nic_access(struct il_priv *il);
1974int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1975int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1976u32 il_rd_prph(struct il_priv *il, u32 reg);
1977void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1978u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1979void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1980
1981static inline void
1982_il_write8(struct il_priv *il, u32 ofs, u8 val)
1983{
1984 writeb(val, il->hw_base + ofs);
1985}
1986#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1987
1988static inline void
1989_il_wr(struct il_priv *il, u32 ofs, u32 val)
1990{
1991 writel(val, il->hw_base + ofs);
1992}
1993
1994static inline u32
1995_il_rd(struct il_priv *il, u32 ofs)
1996{
1997 return readl(il->hw_base + ofs);
1998}
1999
2000static inline void
2001_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2002{
2003 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2004}
2005
2006static inline void
2007_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2008{
2009 _il_wr(il, reg, _il_rd(il, reg) | mask);
2010}
2011
2012static inline void
2013_il_release_nic_access(struct il_priv *il)
2014{
2015 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2016
2017
2018
2019
2020
2021
2022 mmiowb();
2023}
2024
2025static inline u32
2026il_rd(struct il_priv *il, u32 reg)
2027{
2028 u32 value;
2029 unsigned long reg_flags;
2030
2031 spin_lock_irqsave(&il->reg_lock, reg_flags);
2032 _il_grab_nic_access(il);
2033 value = _il_rd(il, reg);
2034 _il_release_nic_access(il);
2035 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2036 return value;
2037}
2038
2039static inline void
2040il_wr(struct il_priv *il, u32 reg, u32 value)
2041{
2042 unsigned long reg_flags;
2043
2044 spin_lock_irqsave(&il->reg_lock, reg_flags);
2045 if (likely(_il_grab_nic_access(il))) {
2046 _il_wr(il, reg, value);
2047 _il_release_nic_access(il);
2048 }
2049 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2050}
2051
2052static inline u32
2053_il_rd_prph(struct il_priv *il, u32 reg)
2054{
2055 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2056 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2057}
2058
2059static inline void
2060_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2061{
2062 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2063 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2064}
2065
2066static inline void
2067il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2068{
2069 unsigned long reg_flags;
2070
2071 spin_lock_irqsave(&il->reg_lock, reg_flags);
2072 if (likely(_il_grab_nic_access(il))) {
2073 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2074 _il_release_nic_access(il);
2075 }
2076 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2077}
2078
2079static inline void
2080il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2081{
2082 unsigned long reg_flags;
2083
2084 spin_lock_irqsave(&il->reg_lock, reg_flags);
2085 if (likely(_il_grab_nic_access(il))) {
2086 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2087 _il_release_nic_access(il);
2088 }
2089 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2090}
2091
2092static inline void
2093il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2094{
2095 unsigned long reg_flags;
2096 u32 val;
2097
2098 spin_lock_irqsave(&il->reg_lock, reg_flags);
2099 if (likely(_il_grab_nic_access(il))) {
2100 val = _il_rd_prph(il, reg);
2101 _il_wr_prph(il, reg, (val & ~mask));
2102 _il_release_nic_access(il);
2103 }
2104 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2105}
2106
2107#define HW_KEY_DYNAMIC 0
2108#define HW_KEY_DEFAULT 1
2109
2110#define IL_STA_DRIVER_ACTIVE BIT(0)
2111#define IL_STA_UCODE_ACTIVE BIT(1)
2112#define IL_STA_UCODE_INPROGRESS BIT(2)
2113
2114#define IL_STA_LOCAL BIT(3)
2115
2116#define IL_STA_BCAST BIT(4)
2117
2118void il_restore_stations(struct il_priv *il);
2119void il_clear_ucode_stations(struct il_priv *il);
2120void il_dealloc_bcast_stations(struct il_priv *il);
2121int il_get_free_ucode_key_idx(struct il_priv *il);
2122int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2123int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2124 struct ieee80211_sta *sta, u8 *sta_id_r);
2125int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2126int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2127 struct ieee80211_sta *sta);
2128
2129u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2130 struct ieee80211_sta *sta);
2131
2132int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2133 u8 flags, bool init);
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144static inline void
2145il_clear_driver_stations(struct il_priv *il)
2146{
2147 unsigned long flags;
2148
2149 spin_lock_irqsave(&il->sta_lock, flags);
2150 memset(il->stations, 0, sizeof(il->stations));
2151 il->num_stations = 0;
2152 il->ucode_key_table = 0;
2153 spin_unlock_irqrestore(&il->sta_lock, flags);
2154}
2155
2156static inline int
2157il_sta_id(struct ieee80211_sta *sta)
2158{
2159 if (WARN_ON(!sta))
2160 return IL_INVALID_STATION;
2161
2162 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2163}
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176static inline int
2177il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2178{
2179 int sta_id;
2180
2181 if (!sta)
2182 return il->hw_params.bcast_id;
2183
2184 sta_id = il_sta_id(sta);
2185
2186
2187
2188
2189
2190 WARN_ON(sta_id == IL_INVALID_STATION);
2191
2192 return sta_id;
2193}
2194
2195
2196
2197
2198
2199
2200static inline int
2201il_queue_inc_wrap(int idx, int n_bd)
2202{
2203 return ++idx & (n_bd - 1);
2204}
2205
2206
2207
2208
2209
2210
2211static inline int
2212il_queue_dec_wrap(int idx, int n_bd)
2213{
2214 return --idx & (n_bd - 1);
2215}
2216
2217
2218static inline void
2219il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2220{
2221 if (desc->v_addr)
2222 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2223 desc->p_addr);
2224 desc->v_addr = NULL;
2225 desc->len = 0;
2226}
2227
2228static inline int
2229il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2230{
2231 if (!desc->len) {
2232 desc->v_addr = NULL;
2233 return -EINVAL;
2234 }
2235
2236 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2237 &desc->p_addr, GFP_KERNEL);
2238 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2239}
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252static inline void
2253il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2254{
2255 BUG_ON(ac > 3);
2256 BUG_ON(hwq > 31);
2257
2258 txq->swq_id = (hwq << 2) | ac;
2259}
2260
2261static inline void
2262_il_wake_queue(struct il_priv *il, u8 ac)
2263{
2264 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2265 ieee80211_wake_queue(il->hw, ac);
2266}
2267
2268static inline void
2269_il_stop_queue(struct il_priv *il, u8 ac)
2270{
2271 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2272 ieee80211_stop_queue(il->hw, ac);
2273}
2274static inline void
2275il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2276{
2277 u8 queue = txq->swq_id;
2278 u8 ac = queue & 3;
2279 u8 hwq = (queue >> 2) & 0x1f;
2280
2281 if (test_and_clear_bit(hwq, il->queue_stopped))
2282 _il_wake_queue(il, ac);
2283}
2284
2285static inline void
2286il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2287{
2288 u8 queue = txq->swq_id;
2289 u8 ac = queue & 3;
2290 u8 hwq = (queue >> 2) & 0x1f;
2291
2292 if (!test_and_set_bit(hwq, il->queue_stopped))
2293 _il_stop_queue(il, ac);
2294}
2295
2296static inline void
2297il_wake_queues_by_reason(struct il_priv *il, int reason)
2298{
2299 u8 ac;
2300
2301 if (test_and_clear_bit(reason, &il->stop_reason))
2302 for (ac = 0; ac < 4; ac++)
2303 _il_wake_queue(il, ac);
2304}
2305
2306static inline void
2307il_stop_queues_by_reason(struct il_priv *il, int reason)
2308{
2309 u8 ac;
2310
2311 if (!test_and_set_bit(reason, &il->stop_reason))
2312 for (ac = 0; ac < 4; ac++)
2313 _il_stop_queue(il, ac);
2314}
2315
2316#ifdef ieee80211_stop_queue
2317#undef ieee80211_stop_queue
2318#endif
2319
2320#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2321
2322#ifdef ieee80211_wake_queue
2323#undef ieee80211_wake_queue
2324#endif
2325
2326#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2327
2328static inline void
2329il_disable_interrupts(struct il_priv *il)
2330{
2331 clear_bit(S_INT_ENABLED, &il->status);
2332
2333
2334 _il_wr(il, CSR_INT_MASK, 0x00000000);
2335
2336
2337
2338 _il_wr(il, CSR_INT, 0xffffffff);
2339 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2340}
2341
2342static inline void
2343il_enable_rfkill_int(struct il_priv *il)
2344{
2345 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2346}
2347
2348static inline void
2349il_enable_interrupts(struct il_priv *il)
2350{
2351 set_bit(S_INT_ENABLED, &il->status);
2352 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2353}
2354
2355
2356
2357
2358
2359
2360static inline u32
2361il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2362{
2363 return (1 << tsf_bits) - 1;
2364}
2365
2366
2367
2368
2369
2370
2371static inline u32
2372il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2373{
2374 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2375}
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387struct il_rb_status {
2388 __le16 closed_rb_num;
2389 __le16 closed_fr_num;
2390 __le16 finished_rb_num;
2391 __le16 finished_fr_nam;
2392 __le32 __unused;
2393} __packed;
2394
2395#define TFD_QUEUE_SIZE_MAX 256
2396#define TFD_QUEUE_SIZE_BC_DUP 64
2397#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2398#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2399#define IL_NUM_OF_TBS 20
2400
2401static inline u8
2402il_get_dma_hi_addr(dma_addr_t addr)
2403{
2404 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2405}
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417struct il_tfd_tb {
2418 __le32 lo;
2419 __le16 hi_n_len;
2420} __packed;
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450struct il_tfd {
2451 u8 __reserved1[3];
2452 u8 num_tbs;
2453 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2454 __le32 __pad;
2455} __packed;
2456
2457#define PCI_CFG_RETRY_TIMEOUT 0x041
2458
2459struct il_rate_info {
2460 u8 plcp;
2461 u8 plcp_siso;
2462 u8 plcp_mimo2;
2463 u8 ieee;
2464 u8 prev_ieee;
2465 u8 next_ieee;
2466 u8 prev_rs;
2467 u8 next_rs;
2468 u8 prev_rs_tgg;
2469 u8 next_rs_tgg;
2470};
2471
2472struct il3945_rate_info {
2473 u8 plcp;
2474 u8 ieee;
2475 u8 prev_ieee;
2476 u8 next_ieee;
2477 u8 prev_rs;
2478 u8 next_rs;
2479 u8 prev_rs_tgg;
2480 u8 next_rs_tgg;
2481 u8 table_rs_idx;
2482 u8 prev_table_rs;
2483};
2484
2485
2486
2487
2488
2489enum {
2490 RATE_1M_IDX = 0,
2491 RATE_2M_IDX,
2492 RATE_5M_IDX,
2493 RATE_11M_IDX,
2494 RATE_6M_IDX,
2495 RATE_9M_IDX,
2496 RATE_12M_IDX,
2497 RATE_18M_IDX,
2498 RATE_24M_IDX,
2499 RATE_36M_IDX,
2500 RATE_48M_IDX,
2501 RATE_54M_IDX,
2502 RATE_60M_IDX,
2503 RATE_COUNT,
2504 RATE_COUNT_LEGACY = RATE_COUNT - 1,
2505 RATE_COUNT_3945 = RATE_COUNT - 1,
2506 RATE_INVM_IDX = RATE_COUNT,
2507 RATE_INVALID = RATE_COUNT,
2508};
2509
2510enum {
2511 RATE_6M_IDX_TBL = 0,
2512 RATE_9M_IDX_TBL,
2513 RATE_12M_IDX_TBL,
2514 RATE_18M_IDX_TBL,
2515 RATE_24M_IDX_TBL,
2516 RATE_36M_IDX_TBL,
2517 RATE_48M_IDX_TBL,
2518 RATE_54M_IDX_TBL,
2519 RATE_1M_IDX_TBL,
2520 RATE_2M_IDX_TBL,
2521 RATE_5M_IDX_TBL,
2522 RATE_11M_IDX_TBL,
2523 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2524};
2525
2526enum {
2527 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2528 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2529 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2530 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2531 IL_LAST_CCK_RATE = RATE_11M_IDX,
2532};
2533
2534
2535#define RATE_6M_MASK (1 << RATE_6M_IDX)
2536#define RATE_9M_MASK (1 << RATE_9M_IDX)
2537#define RATE_12M_MASK (1 << RATE_12M_IDX)
2538#define RATE_18M_MASK (1 << RATE_18M_IDX)
2539#define RATE_24M_MASK (1 << RATE_24M_IDX)
2540#define RATE_36M_MASK (1 << RATE_36M_IDX)
2541#define RATE_48M_MASK (1 << RATE_48M_IDX)
2542#define RATE_54M_MASK (1 << RATE_54M_IDX)
2543#define RATE_60M_MASK (1 << RATE_60M_IDX)
2544#define RATE_1M_MASK (1 << RATE_1M_IDX)
2545#define RATE_2M_MASK (1 << RATE_2M_IDX)
2546#define RATE_5M_MASK (1 << RATE_5M_IDX)
2547#define RATE_11M_MASK (1 << RATE_11M_IDX)
2548
2549
2550enum {
2551 RATE_6M_PLCP = 13,
2552 RATE_9M_PLCP = 15,
2553 RATE_12M_PLCP = 5,
2554 RATE_18M_PLCP = 7,
2555 RATE_24M_PLCP = 9,
2556 RATE_36M_PLCP = 11,
2557 RATE_48M_PLCP = 1,
2558 RATE_54M_PLCP = 3,
2559 RATE_60M_PLCP = 3,
2560 RATE_1M_PLCP = 10,
2561 RATE_2M_PLCP = 20,
2562 RATE_5M_PLCP = 55,
2563 RATE_11M_PLCP = 110,
2564
2565};
2566
2567
2568enum {
2569 RATE_SISO_6M_PLCP = 0,
2570 RATE_SISO_12M_PLCP = 1,
2571 RATE_SISO_18M_PLCP = 2,
2572 RATE_SISO_24M_PLCP = 3,
2573 RATE_SISO_36M_PLCP = 4,
2574 RATE_SISO_48M_PLCP = 5,
2575 RATE_SISO_54M_PLCP = 6,
2576 RATE_SISO_60M_PLCP = 7,
2577 RATE_MIMO2_6M_PLCP = 0x8,
2578 RATE_MIMO2_12M_PLCP = 0x9,
2579 RATE_MIMO2_18M_PLCP = 0xa,
2580 RATE_MIMO2_24M_PLCP = 0xb,
2581 RATE_MIMO2_36M_PLCP = 0xc,
2582 RATE_MIMO2_48M_PLCP = 0xd,
2583 RATE_MIMO2_54M_PLCP = 0xe,
2584 RATE_MIMO2_60M_PLCP = 0xf,
2585 RATE_SISO_INVM_PLCP,
2586 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2587};
2588
2589
2590enum {
2591 RATE_6M_IEEE = 12,
2592 RATE_9M_IEEE = 18,
2593 RATE_12M_IEEE = 24,
2594 RATE_18M_IEEE = 36,
2595 RATE_24M_IEEE = 48,
2596 RATE_36M_IEEE = 72,
2597 RATE_48M_IEEE = 96,
2598 RATE_54M_IEEE = 108,
2599 RATE_60M_IEEE = 120,
2600 RATE_1M_IEEE = 2,
2601 RATE_2M_IEEE = 4,
2602 RATE_5M_IEEE = 11,
2603 RATE_11M_IEEE = 22,
2604};
2605
2606#define IL_CCK_BASIC_RATES_MASK \
2607 (RATE_1M_MASK | \
2608 RATE_2M_MASK)
2609
2610#define IL_CCK_RATES_MASK \
2611 (IL_CCK_BASIC_RATES_MASK | \
2612 RATE_5M_MASK | \
2613 RATE_11M_MASK)
2614
2615#define IL_OFDM_BASIC_RATES_MASK \
2616 (RATE_6M_MASK | \
2617 RATE_12M_MASK | \
2618 RATE_24M_MASK)
2619
2620#define IL_OFDM_RATES_MASK \
2621 (IL_OFDM_BASIC_RATES_MASK | \
2622 RATE_9M_MASK | \
2623 RATE_18M_MASK | \
2624 RATE_36M_MASK | \
2625 RATE_48M_MASK | \
2626 RATE_54M_MASK)
2627
2628#define IL_BASIC_RATES_MASK \
2629 (IL_OFDM_BASIC_RATES_MASK | \
2630 IL_CCK_BASIC_RATES_MASK)
2631
2632#define RATES_MASK ((1 << RATE_COUNT) - 1)
2633#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2634
2635#define IL_INVALID_VALUE -1
2636
2637#define IL_MIN_RSSI_VAL -100
2638#define IL_MAX_RSSI_VAL 0
2639
2640
2641
2642#define IL_LEGACY_FAILURE_LIMIT 160
2643#define IL_LEGACY_SUCCESS_LIMIT 480
2644#define IL_LEGACY_TBL_COUNT 160
2645
2646#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2647#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2648#define IL_NONE_LEGACY_TBL_COUNT 1500
2649
2650
2651#define IL_RS_GOOD_RATIO 12800
2652#define RATE_SCALE_SWITCH 10880
2653#define RATE_HIGH_TH 10880
2654#define RATE_INCREASE_TH 6400
2655#define RATE_DECREASE_TH 1920
2656
2657
2658#define IL_LEGACY_SWITCH_ANTENNA1 0
2659#define IL_LEGACY_SWITCH_ANTENNA2 1
2660#define IL_LEGACY_SWITCH_SISO 2
2661#define IL_LEGACY_SWITCH_MIMO2_AB 3
2662#define IL_LEGACY_SWITCH_MIMO2_AC 4
2663#define IL_LEGACY_SWITCH_MIMO2_BC 5
2664
2665
2666#define IL_SISO_SWITCH_ANTENNA1 0
2667#define IL_SISO_SWITCH_ANTENNA2 1
2668#define IL_SISO_SWITCH_MIMO2_AB 2
2669#define IL_SISO_SWITCH_MIMO2_AC 3
2670#define IL_SISO_SWITCH_MIMO2_BC 4
2671#define IL_SISO_SWITCH_GI 5
2672
2673
2674#define IL_MIMO2_SWITCH_ANTENNA1 0
2675#define IL_MIMO2_SWITCH_ANTENNA2 1
2676#define IL_MIMO2_SWITCH_SISO_A 2
2677#define IL_MIMO2_SWITCH_SISO_B 3
2678#define IL_MIMO2_SWITCH_SISO_C 4
2679#define IL_MIMO2_SWITCH_GI 5
2680
2681#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2682
2683#define IL_ACTION_LIMIT 3
2684
2685#define LQ_SIZE 2
2686
2687
2688#define IL_AGG_TPT_THREHOLD 0
2689#define IL_AGG_LOAD_THRESHOLD 10
2690#define IL_AGG_ALL_TID 0xff
2691#define TID_QUEUE_CELL_SPACING 50
2692#define TID_QUEUE_MAX_SIZE 20
2693#define TID_ROUND_VALUE 5
2694#define TID_MAX_LOAD_COUNT 8
2695
2696#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2697#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2698
2699extern const struct il_rate_info il_rates[RATE_COUNT];
2700
2701enum il_table_type {
2702 LQ_NONE,
2703 LQ_G,
2704 LQ_A,
2705 LQ_SISO,
2706 LQ_MIMO2,
2707 LQ_MAX,
2708};
2709
2710#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2711#define is_siso(tbl) ((tbl) == LQ_SISO)
2712#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2713#define is_mimo(tbl) (is_mimo2(tbl))
2714#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2715#define is_a_band(tbl) ((tbl) == LQ_A)
2716#define is_g_and(tbl) ((tbl) == LQ_G)
2717
2718#define ANT_NONE 0x0
2719#define ANT_A BIT(0)
2720#define ANT_B BIT(1)
2721#define ANT_AB (ANT_A | ANT_B)
2722#define ANT_C BIT(2)
2723#define ANT_AC (ANT_A | ANT_C)
2724#define ANT_BC (ANT_B | ANT_C)
2725#define ANT_ABC (ANT_AB | ANT_C)
2726
2727#define IL_MAX_MCS_DISPLAY_SIZE 12
2728
2729struct il_rate_mcs_info {
2730 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2731 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2732};
2733
2734
2735
2736
2737struct il_rate_scale_data {
2738 u64 data;
2739 s32 success_counter;
2740 s32 success_ratio;
2741 s32 counter;
2742 s32 average_tpt;
2743 unsigned long stamp;
2744};
2745
2746
2747
2748
2749
2750
2751
2752struct il_scale_tbl_info {
2753 enum il_table_type lq_type;
2754 u8 ant_type;
2755 u8 is_SGI;
2756 u8 is_ht40;
2757 u8 is_dup;
2758 u8 action;
2759 u8 max_search;
2760 s32 *expected_tpt;
2761 u32 current_rate;
2762 struct il_rate_scale_data win[RATE_COUNT];
2763};
2764
2765struct il_traffic_load {
2766 unsigned long time_stamp;
2767 u32 packet_count[TID_QUEUE_MAX_SIZE];
2768
2769 u32 total;
2770
2771 u8 queue_count;
2772
2773 u8 head;
2774};
2775
2776
2777
2778
2779
2780
2781struct il_lq_sta {
2782 u8 active_tbl;
2783 u8 enable_counter;
2784 u8 stay_in_tbl;
2785 u8 search_better_tbl;
2786 s32 last_tpt;
2787
2788
2789 u32 table_count_limit;
2790 u32 max_failure_limit;
2791 u32 max_success_limit;
2792 u32 table_count;
2793 u32 total_failed;
2794 u32 total_success;
2795 u64 flush_timer;
2796
2797 u8 action_counter;
2798 u8 is_green;
2799 u8 is_dup;
2800 enum ieee80211_band band;
2801
2802
2803 u32 supp_rates;
2804 u16 active_legacy_rate;
2805 u16 active_siso_rate;
2806 u16 active_mimo2_rate;
2807 s8 max_rate_idx;
2808 u8 missed_rate_counter;
2809
2810 struct il_link_quality_cmd lq;
2811 struct il_scale_tbl_info lq_info[LQ_SIZE];
2812 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2813 u8 tx_agg_tid_en;
2814#ifdef CONFIG_MAC80211_DEBUGFS
2815 struct dentry *rs_sta_dbgfs_scale_table_file;
2816 struct dentry *rs_sta_dbgfs_stats_table_file;
2817 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2818 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2819 u32 dbg_fixed_rate;
2820#endif
2821 struct il_priv *drv;
2822
2823
2824 int last_txrate_idx;
2825
2826 u32 last_rate_n_flags;
2827
2828 u8 is_agg;
2829};
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841struct il_station_priv {
2842 struct il_station_priv_common common;
2843 struct il_lq_sta lq_sta;
2844 atomic_t pending_frames;
2845 bool client;
2846 bool asleep;
2847};
2848
2849static inline u8
2850il4965_num_of_ant(u8 m)
2851{
2852 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2853}
2854
2855static inline u8
2856il4965_first_antenna(u8 mask)
2857{
2858 if (mask & ANT_A)
2859 return ANT_A;
2860 if (mask & ANT_B)
2861 return ANT_B;
2862 return ANT_C;
2863}
2864
2865
2866
2867
2868
2869
2870
2871void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2872
2873
2874void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2875 u8 sta_id);
2876void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2877 u8 sta_id);
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889int il4965_rate_control_register(void);
2890int il3945_rate_control_register(void);
2891
2892
2893
2894
2895
2896
2897
2898void il4965_rate_control_unregister(void);
2899void il3945_rate_control_unregister(void);
2900
2901int il_power_update_mode(struct il_priv *il, bool force);
2902void il_power_initialize(struct il_priv *il);
2903
2904extern u32 il_debug_level;
2905
2906#ifdef CONFIG_IWLEGACY_DEBUG
2907
2908
2909
2910
2911
2912
2913
2914static inline u32
2915il_get_debug_level(struct il_priv *il)
2916{
2917 if (il->debug_level)
2918 return il->debug_level;
2919 else
2920 return il_debug_level;
2921}
2922#else
2923static inline u32
2924il_get_debug_level(struct il_priv *il)
2925{
2926 return il_debug_level;
2927}
2928#endif
2929
2930#define il_print_hex_error(il, p, len) \
2931do { \
2932 print_hex_dump(KERN_ERR, "iwl data: ", \
2933 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2934} while (0)
2935
2936#ifdef CONFIG_IWLEGACY_DEBUG
2937#define IL_DBG(level, fmt, args...) \
2938do { \
2939 if (il_get_debug_level(il) & level) \
2940 dev_err(&il->hw->wiphy->dev, "%c %s " fmt, \
2941 in_interrupt() ? 'I' : 'U', __func__ , ##args); \
2942} while (0)
2943
2944#define il_print_hex_dump(il, level, p, len) \
2945do { \
2946 if (il_get_debug_level(il) & level) \
2947 print_hex_dump(KERN_DEBUG, "iwl data: ", \
2948 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2949} while (0)
2950
2951#else
2952#define IL_DBG(level, fmt, args...)
2953static inline void
2954il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2955{
2956}
2957#endif
2958
2959#ifdef CONFIG_IWLEGACY_DEBUGFS
2960int il_dbgfs_register(struct il_priv *il, const char *name);
2961void il_dbgfs_unregister(struct il_priv *il);
2962#else
2963static inline int
2964il_dbgfs_register(struct il_priv *il, const char *name)
2965{
2966 return 0;
2967}
2968
2969static inline void
2970il_dbgfs_unregister(struct il_priv *il)
2971{
2972}
2973#endif
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999#define IL_DL_INFO (1 << 0)
3000#define IL_DL_MAC80211 (1 << 1)
3001#define IL_DL_HCMD (1 << 2)
3002#define IL_DL_STATE (1 << 3)
3003
3004#define IL_DL_MACDUMP (1 << 4)
3005#define IL_DL_HCMD_DUMP (1 << 5)
3006#define IL_DL_EEPROM (1 << 6)
3007#define IL_DL_RADIO (1 << 7)
3008
3009#define IL_DL_POWER (1 << 8)
3010#define IL_DL_TEMP (1 << 9)
3011#define IL_DL_NOTIF (1 << 10)
3012#define IL_DL_SCAN (1 << 11)
3013
3014#define IL_DL_ASSOC (1 << 12)
3015#define IL_DL_DROP (1 << 13)
3016#define IL_DL_TXPOWER (1 << 14)
3017#define IL_DL_AP (1 << 15)
3018
3019#define IL_DL_FW (1 << 16)
3020#define IL_DL_RF_KILL (1 << 17)
3021#define IL_DL_FW_ERRORS (1 << 18)
3022#define IL_DL_LED (1 << 19)
3023
3024#define IL_DL_RATE (1 << 20)
3025#define IL_DL_CALIB (1 << 21)
3026#define IL_DL_WEP (1 << 22)
3027#define IL_DL_TX (1 << 23)
3028
3029#define IL_DL_RX (1 << 24)
3030#define IL_DL_ISR (1 << 25)
3031#define IL_DL_HT (1 << 26)
3032
3033#define IL_DL_11H (1 << 28)
3034#define IL_DL_STATS (1 << 29)
3035#define IL_DL_TX_REPLY (1 << 30)
3036#define IL_DL_QOS (1 << 31)
3037
3038#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3039#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3040#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3041#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3042#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3043#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3044#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3045#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3046#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3047#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3048#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3049#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3050#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3051#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3052#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3053#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3054#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3055#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3056#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3057#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3058#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3059#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3060#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3061#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3062#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3063#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3064#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3065#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3066#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3067
3068#endif
3069