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64#ifndef __fw_api_h__
65#define __fw_api_h__
66
67#include "fw-api-rs.h"
68#include "fw-api-tx.h"
69#include "fw-api-sta.h"
70#include "fw-api-mac.h"
71#include "fw-api-power.h"
72#include "fw-api-d3.h"
73#include "fw-api-bt-coex.h"
74
75
76#define IWL_MVM_MAX_QUEUES 20
77
78
79enum {
80 IWL_MVM_OFFCHANNEL_QUEUE = 8,
81 IWL_MVM_CMD_QUEUE = 9,
82};
83
84#define IWL_MVM_CMD_FIFO 7
85
86#define IWL_MVM_STATION_COUNT 16
87
88
89enum {
90 MVM_ALIVE = 0x1,
91 REPLY_ERROR = 0x2,
92
93 INIT_COMPLETE_NOTIF = 0x4,
94
95
96 PHY_CONTEXT_CMD = 0x8,
97 DBG_CFG = 0x9,
98
99
100 ADD_STA_KEY = 0x17,
101 ADD_STA = 0x18,
102 REMOVE_STA = 0x19,
103
104
105 TX_CMD = 0x1c,
106 TXPATH_FLUSH = 0x1e,
107 MGMT_MCAST_KEY = 0x1f,
108
109
110 WEP_KEY = 0x20,
111
112
113 MAC_CONTEXT_CMD = 0x28,
114 TIME_EVENT_CMD = 0x29,
115 TIME_EVENT_NOTIFICATION = 0x2a,
116 BINDING_CONTEXT_CMD = 0x2b,
117 TIME_QUOTA_CMD = 0x2c,
118 NON_QOS_TX_COUNTER_CMD = 0x2d,
119
120 LQ_CMD = 0x4e,
121
122
123 TEMPERATURE_NOTIFICATION = 0x62,
124 CALIBRATION_CFG_CMD = 0x65,
125 CALIBRATION_RES_NOTIFICATION = 0x66,
126 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
127 RADIO_VERSION_NOTIFICATION = 0x68,
128
129
130 SCAN_OFFLOAD_REQUEST_CMD = 0x51,
131 SCAN_OFFLOAD_ABORT_CMD = 0x52,
132 SCAN_OFFLOAD_COMPLETE = 0x6D,
133 SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
134 SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
135 MATCH_FOUND_NOTIFICATION = 0xd9,
136
137
138 PHY_CONFIGURATION_CMD = 0x6a,
139 CALIB_RES_NOTIF_PHY_DB = 0x6b,
140
141
142
143 POWER_TABLE_CMD = 0x77,
144
145
146 REPLY_THERMAL_MNG_BACKOFF = 0x7e,
147
148
149 SCAN_REQUEST_CMD = 0x80,
150 SCAN_ABORT_CMD = 0x81,
151 SCAN_START_NOTIFICATION = 0x82,
152 SCAN_RESULTS_NOTIFICATION = 0x83,
153 SCAN_COMPLETE_NOTIFICATION = 0x84,
154
155
156 NVM_ACCESS_CMD = 0x88,
157
158 SET_CALIB_DEFAULT_CMD = 0x8e,
159
160 BEACON_NOTIFICATION = 0x90,
161 BEACON_TEMPLATE_CMD = 0x91,
162 TX_ANT_CONFIGURATION_CMD = 0x98,
163 BT_CONFIG = 0x9b,
164 STATISTICS_NOTIFICATION = 0x9d,
165 REDUCE_TX_POWER_CMD = 0x9f,
166
167
168 CARD_STATE_CMD = 0xa0,
169 CARD_STATE_NOTIFICATION = 0xa1,
170
171 MISSED_BEACONS_NOTIFICATION = 0xa2,
172
173
174 MAC_PM_POWER_TABLE = 0xa9,
175
176 REPLY_RX_PHY_CMD = 0xc0,
177 REPLY_RX_MPDU_CMD = 0xc1,
178 BA_NOTIF = 0xc5,
179
180
181 BT_COEX_PRIO_TABLE = 0xcc,
182 BT_COEX_PROT_ENV = 0xcd,
183 BT_PROFILE_NOTIFICATION = 0xce,
184 BT_COEX_CI = 0x5d,
185
186 REPLY_BEACON_FILTERING_CMD = 0xd2,
187
188 REPLY_DEBUG_CMD = 0xf0,
189 DEBUG_LOG_MSG = 0xf7,
190
191 MCAST_FILTER_CMD = 0xd0,
192
193
194 D3_CONFIG_CMD = 0xd3,
195 PROT_OFFLOAD_CONFIG_CMD = 0xd4,
196 OFFLOADS_QUERY_CMD = 0xd5,
197 REMOTE_WAKE_CONFIG_CMD = 0xd6,
198
199
200 WOWLAN_PATTERNS = 0xe0,
201 WOWLAN_CONFIGURATION = 0xe1,
202 WOWLAN_TSC_RSC_PARAM = 0xe2,
203 WOWLAN_TKIP_PARAM = 0xe3,
204 WOWLAN_KEK_KCK_MATERIAL = 0xe4,
205 WOWLAN_GET_STATUSES = 0xe5,
206 WOWLAN_TX_POWER_PER_DB = 0xe6,
207
208
209 NET_DETECT_CONFIG_CMD = 0x54,
210 NET_DETECT_PROFILES_QUERY_CMD = 0x56,
211 NET_DETECT_PROFILES_CMD = 0x57,
212 NET_DETECT_HOTSPOTS_CMD = 0x58,
213 NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
214
215 REPLY_MAX = 0xff,
216};
217
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219
220
221
222struct iwl_cmd_response {
223 __le32 status;
224};
225
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228
229
230struct iwl_tx_ant_cfg_cmd {
231 __le32 valid;
232} __packed;
233
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240
241struct iwl_reduce_tx_power_cmd {
242 u8 flags;
243 u8 mac_context_id;
244 __le16 pwr_restriction;
245} __packed;
246
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254
255struct iwl_calib_ctrl {
256 __le32 flow_trigger;
257 __le32 event_trigger;
258} __packed;
259
260
261
262
263enum iwl_calib_cfg {
264 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
265 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
266 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
267 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
268 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
269 IWL_CALIB_CFG_DC_IDX = BIT(5),
270 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
271 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
272 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
273 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
274 IWL_CALIB_CFG_RX_IQ_IDX = BIT(10),
275 IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11),
276 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12),
277 IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13),
278 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14),
279 IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15),
280 IWL_CALIB_CFG_DAC_IDX = BIT(16),
281 IWL_CALIB_CFG_ABS_IDX = BIT(17),
282 IWL_CALIB_CFG_AGC_IDX = BIT(18),
283};
284
285
286
287
288struct iwl_phy_cfg_cmd {
289 __le32 phy_cfg;
290 struct iwl_calib_ctrl calib_control;
291} __packed;
292
293#define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
294#define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
295#define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
296#define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
297#define PHY_CFG_TX_CHAIN_A BIT(8)
298#define PHY_CFG_TX_CHAIN_B BIT(9)
299#define PHY_CFG_TX_CHAIN_C BIT(10)
300#define PHY_CFG_RX_CHAIN_A BIT(12)
301#define PHY_CFG_RX_CHAIN_B BIT(13)
302#define PHY_CFG_RX_CHAIN_C BIT(14)
303
304
305
306enum {
307 NVM_ACCESS_TARGET_CACHE = 0,
308 NVM_ACCESS_TARGET_OTP = 1,
309 NVM_ACCESS_TARGET_EEPROM = 2,
310};
311
312
313enum {
314 NVM_SECTION_TYPE_HW = 0,
315 NVM_SECTION_TYPE_SW,
316 NVM_SECTION_TYPE_PAPD,
317 NVM_SECTION_TYPE_BT,
318 NVM_SECTION_TYPE_CALIBRATION,
319 NVM_SECTION_TYPE_PRODUCTION,
320 NVM_SECTION_TYPE_POST_FCS_CALIB,
321 NVM_NUM_OF_SECTIONS,
322};
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332
333struct iwl_nvm_access_cmd {
334 u8 op_code;
335 u8 target;
336 __le16 type;
337 __le16 offset;
338 __le16 length;
339 u8 data[];
340} __packed;
341
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349
350struct iwl_nvm_access_resp {
351 __le16 offset;
352 __le16 length;
353 __le16 type;
354 __le16 status;
355 u8 data[];
356} __packed;
357
358
359
360
361#define ALIVE_RESP_UCODE_OK BIT(0)
362#define ALIVE_RESP_RFKILL BIT(1)
363
364
365enum {
366 FW_TYPE_HW = 0,
367 FW_TYPE_PROT = 1,
368 FW_TYPE_AP = 2,
369 FW_TYPE_WOWLAN = 3,
370 FW_TYPE_TIMING = 4,
371 FW_TYPE_WIPAN = 5
372};
373
374
375enum {
376 FW_SUBTYPE_FULL_FEATURE = 0,
377 FW_SUBTYPE_BOOTSRAP = 1,
378 FW_SUBTYPE_REDUCED = 2,
379 FW_SUBTYPE_ALIVE_ONLY = 3,
380 FW_SUBTYPE_WOWLAN = 4,
381 FW_SUBTYPE_AP_SUBTYPE = 5,
382 FW_SUBTYPE_WIPAN = 6,
383 FW_SUBTYPE_INITIALIZE = 9
384};
385
386#define IWL_ALIVE_STATUS_ERR 0xDEAD
387#define IWL_ALIVE_STATUS_OK 0xCAFE
388
389#define IWL_ALIVE_FLG_RFKILL BIT(0)
390
391struct mvm_alive_resp {
392 __le16 status;
393 __le16 flags;
394 u8 ucode_minor;
395 u8 ucode_major;
396 __le16 id;
397 u8 api_minor;
398 u8 api_major;
399 u8 ver_subtype;
400 u8 ver_type;
401 u8 mac;
402 u8 opt;
403 __le16 reserved2;
404 __le32 timestamp;
405 __le32 error_event_table_ptr;
406 __le32 log_event_table_ptr;
407 __le32 cpu_register_ptr;
408 __le32 dbgm_config_ptr;
409 __le32 alive_counter_ptr;
410 __le32 scd_base_ptr;
411} __packed;
412
413
414enum {
415 FW_ERR_UNKNOWN_CMD = 0x0,
416 FW_ERR_INVALID_CMD_PARAM = 0x1,
417 FW_ERR_SERVICE = 0x2,
418 FW_ERR_ARC_MEMORY = 0x3,
419 FW_ERR_ARC_CODE = 0x4,
420 FW_ERR_WATCH_DOG = 0x5,
421 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
422 FW_ERR_WEP_KEY_SIZE = 0x11,
423 FW_ERR_OBSOLETE_FUNC = 0x12,
424 FW_ERR_UNEXPECTED = 0xFE,
425 FW_ERR_FATAL = 0xFF
426};
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437
438struct iwl_error_resp {
439 __le32 error_type;
440 u8 cmd_id;
441 u8 reserved1;
442 __le16 bad_cmd_seq_num;
443 __le32 error_service;
444 __le64 timestamp;
445} __packed;
446
447
448
449
450#define MAX_MACS_IN_BINDING (3)
451#define MAX_BINDINGS (4)
452#define AUX_BINDING_INDEX (3)
453#define MAX_PHYS (4)
454
455
456#define FW_CTXT_ID_POS (0)
457#define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS)
458#define FW_CTXT_COLOR_POS (8)
459#define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS)
460#define FW_CTXT_INVALID (0xffffffff)
461
462#define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\
463 (_color << FW_CTXT_COLOR_POS))
464
465
466enum {
467 FW_CTXT_ACTION_STUB = 0,
468 FW_CTXT_ACTION_ADD,
469 FW_CTXT_ACTION_MODIFY,
470 FW_CTXT_ACTION_REMOVE,
471 FW_CTXT_ACTION_NUM
472};
473
474
475
476
477enum iwl_time_event_type {
478
479 TE_BSS_STA_AGGRESSIVE_ASSOC,
480 TE_BSS_STA_ASSOC,
481 TE_BSS_EAP_DHCP_PROT,
482 TE_BSS_QUIET_PERIOD,
483
484
485 TE_P2P_DEVICE_DISCOVERABLE,
486 TE_P2P_DEVICE_LISTEN,
487 TE_P2P_DEVICE_ACTION_SCAN,
488 TE_P2P_DEVICE_FULL_SCAN,
489
490
491 TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
492 TE_P2P_CLIENT_ASSOC,
493 TE_P2P_CLIENT_QUIET_PERIOD,
494
495
496 TE_P2P_GO_ASSOC_PROT,
497 TE_P2P_GO_REPETITIVE_NOA,
498 TE_P2P_GO_CT_WINDOW,
499
500
501 TE_WIDI_TX_SYNC,
502
503 TE_MAX
504};
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522
523enum {
524 TE_V1_FRAG_NONE = 0,
525 TE_V1_FRAG_SINGLE = 1,
526 TE_V1_FRAG_DUAL = 2,
527 TE_V1_FRAG_ENDLESS = 0xffffffff
528};
529
530
531#define TE_V1_FRAG_MAX_MSK 0x0fffffff
532
533#define TE_V1_REPEAT_ENDLESS 0xffffffff
534
535#define TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
536
537
538enum {
539 TE_V1_INDEPENDENT = 0,
540 TE_V1_DEP_OTHER = BIT(0),
541 TE_V1_DEP_TSF = BIT(1),
542 TE_V1_EVENT_SOCIOPATHIC = BIT(2),
543};
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561
562enum {
563 TE_V1_NOTIF_NONE = 0,
564 TE_V1_NOTIF_HOST_EVENT_START = BIT(0),
565 TE_V1_NOTIF_HOST_EVENT_END = BIT(1),
566 TE_V1_NOTIF_INTERNAL_EVENT_START = BIT(2),
567 TE_V1_NOTIF_INTERNAL_EVENT_END = BIT(3),
568 TE_V1_NOTIF_HOST_FRAG_START = BIT(4),
569 TE_V1_NOTIF_HOST_FRAG_END = BIT(5),
570 TE_V1_NOTIF_INTERNAL_FRAG_START = BIT(6),
571 TE_V1_NOTIF_INTERNAL_FRAG_END = BIT(7),
572};
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599struct iwl_time_event_cmd_v1 {
600
601 __le32 id_and_color;
602 __le32 action;
603 __le32 id;
604
605 __le32 apply_time;
606 __le32 max_delay;
607 __le32 dep_policy;
608 __le32 depends_on;
609 __le32 is_present;
610 __le32 max_frags;
611 __le32 interval;
612 __le32 interval_reciprocal;
613 __le32 duration;
614 __le32 repeat;
615 __le32 notify;
616} __packed;
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633
634enum {
635 TE_V2_FRAG_NONE = 0,
636 TE_V2_FRAG_SINGLE = 1,
637 TE_V2_FRAG_DUAL = 2,
638 TE_V2_FRAG_MAX = 0xfe,
639 TE_V2_FRAG_ENDLESS = 0xff
640};
641
642
643#define TE_V2_REPEAT_ENDLESS 0xff
644
645#define TE_V2_REPEAT_MAX 0xfe
646
647#define TE_V2_PLACEMENT_POS 12
648#define TE_V2_ABSENCE_POS 15
649
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669
670enum {
671 TE_V2_DEFAULT_POLICY = 0x0,
672
673
674 TE_V2_NOTIF_HOST_EVENT_START = BIT(0),
675 TE_V2_NOTIF_HOST_EVENT_END = BIT(1),
676 TE_V2_NOTIF_INTERNAL_EVENT_START = BIT(2),
677 TE_V2_NOTIF_INTERNAL_EVENT_END = BIT(3),
678
679 TE_V2_NOTIF_HOST_FRAG_START = BIT(4),
680 TE_V2_NOTIF_HOST_FRAG_END = BIT(5),
681 TE_V2_NOTIF_INTERNAL_FRAG_START = BIT(6),
682 TE_V2_NOTIF_INTERNAL_FRAG_END = BIT(7),
683
684 TE_V2_NOTIF_MSK = 0xff,
685
686
687 TE_V2_DEP_OTHER = BIT(TE_V2_PLACEMENT_POS),
688 TE_V2_DEP_TSF = BIT(TE_V2_PLACEMENT_POS + 1),
689 TE_V2_EVENT_SOCIOPATHIC = BIT(TE_V2_PLACEMENT_POS + 2),
690
691
692 TE_V2_ABSENCE = BIT(TE_V2_ABSENCE_POS),
693};
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718
719struct iwl_time_event_cmd_v2 {
720
721 __le32 id_and_color;
722 __le32 action;
723 __le32 id;
724
725 __le32 apply_time;
726 __le32 max_delay;
727 __le32 depends_on;
728 __le32 interval;
729 __le32 duration;
730 u8 repeat;
731 u8 max_frags;
732 __le16 policy;
733} __packed;
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739
740
741
742struct iwl_time_event_resp {
743 __le32 status;
744 __le32 id;
745 __le32 unique_id;
746 __le32 id_and_color;
747} __packed;
748
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758
759struct iwl_time_event_notif {
760 __le32 timestamp;
761 __le32 session_id;
762 __le32 unique_id;
763 __le32 id_and_color;
764 __le32 action;
765 __le32 status;
766} __packed;
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778
779struct iwl_binding_cmd {
780
781 __le32 id_and_color;
782 __le32 action;
783
784 __le32 macs[MAX_MACS_IN_BINDING];
785 __le32 phy;
786} __packed;
787
788
789#define IWL_MVM_MAX_QUOTA 128
790
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797
798struct iwl_time_quota_data {
799 __le32 id_and_color;
800 __le32 quota;
801 __le32 max_duration;
802} __packed;
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808
809struct iwl_time_quota_cmd {
810 struct iwl_time_quota_data quotas[MAX_BINDINGS];
811} __packed;
812
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815
816
817#define PHY_BAND_5 (0)
818#define PHY_BAND_24 (1)
819
820
821#define PHY_VHT_CHANNEL_MODE20 (0x0)
822#define PHY_VHT_CHANNEL_MODE40 (0x1)
823#define PHY_VHT_CHANNEL_MODE80 (0x2)
824#define PHY_VHT_CHANNEL_MODE160 (0x3)
825
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837
838#define PHY_VHT_CTRL_POS_1_BELOW (0x0)
839#define PHY_VHT_CTRL_POS_2_BELOW (0x1)
840#define PHY_VHT_CTRL_POS_3_BELOW (0x2)
841#define PHY_VHT_CTRL_POS_4_BELOW (0x3)
842#define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
843#define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
844#define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
845#define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
846
847
848
849
850
851
852
853struct iwl_fw_channel_info {
854 u8 band;
855 u8 channel;
856 u8 width;
857 u8 ctrl_pos;
858} __packed;
859
860#define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
861#define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
862 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
863#define PHY_RX_CHAIN_VALID_POS (1)
864#define PHY_RX_CHAIN_VALID_MSK \
865 (0x7 << PHY_RX_CHAIN_VALID_POS)
866#define PHY_RX_CHAIN_FORCE_SEL_POS (4)
867#define PHY_RX_CHAIN_FORCE_SEL_MSK \
868 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
869#define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
870#define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
871 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
872#define PHY_RX_CHAIN_CNT_POS (10)
873#define PHY_RX_CHAIN_CNT_MSK \
874 (0x3 << PHY_RX_CHAIN_CNT_POS)
875#define PHY_RX_CHAIN_MIMO_CNT_POS (12)
876#define PHY_RX_CHAIN_MIMO_CNT_MSK \
877 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
878#define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
879#define PHY_RX_CHAIN_MIMO_FORCE_MSK \
880 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
881
882
883#define NUM_PHY_CTX 3
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899
900struct iwl_phy_context_cmd {
901
902 __le32 id_and_color;
903 __le32 action;
904
905 __le32 apply_time;
906 __le32 tx_param_color;
907 struct iwl_fw_channel_info ci;
908 __le32 txchain_info;
909 __le32 rxchain_info;
910 __le32 acquisition_data;
911 __le32 dsp_cfg_flags;
912} __packed;
913
914#define IWL_RX_INFO_PHY_CNT 8
915#define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
916#define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
917#define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
918#define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
919#define IWL_RX_INFO_ENERGY_ANT_A_POS 0
920#define IWL_RX_INFO_ENERGY_ANT_B_POS 8
921#define IWL_RX_INFO_ENERGY_ANT_C_POS 16
922
923#define IWL_RX_INFO_AGC_IDX 1
924#define IWL_RX_INFO_RSSI_AB_IDX 2
925#define IWL_OFDM_AGC_A_MSK 0x0000007f
926#define IWL_OFDM_AGC_A_POS 0
927#define IWL_OFDM_AGC_B_MSK 0x00003f80
928#define IWL_OFDM_AGC_B_POS 7
929#define IWL_OFDM_AGC_CODE_MSK 0x3fe00000
930#define IWL_OFDM_AGC_CODE_POS 20
931#define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff
932#define IWL_OFDM_RSSI_A_POS 0
933#define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00
934#define IWL_OFDM_RSSI_ALLBAND_A_POS 8
935#define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000
936#define IWL_OFDM_RSSI_B_POS 16
937#define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
938#define IWL_OFDM_RSSI_ALLBAND_B_POS 24
939
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961
962struct iwl_rx_phy_info {
963 u8 non_cfg_phy_cnt;
964 u8 cfg_phy_cnt;
965 u8 stat_id;
966 u8 reserved1;
967 __le32 system_timestamp;
968 __le64 timestamp;
969 __le32 beacon_time_stamp;
970 __le16 phy_flags;
971 __le16 channel;
972 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
973 __le32 rate_n_flags;
974 __le32 byte_count;
975 __le16 mac_active_msk;
976 __le16 frame_time;
977} __packed;
978
979struct iwl_rx_mpdu_res_start {
980 __le16 byte_count;
981 __le16 reserved;
982} __packed;
983
984
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988
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995
996enum iwl_rx_phy_flags {
997 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
998 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
999 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
1000 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
1001 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
1002 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
1003 RX_RES_PHY_FLAGS_AGG = BIT(7),
1004 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
1005 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
1006 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
1007};
1008
1009
1010
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1016
1017
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1020
1021
1022
1023
1024
1025
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1040
1041enum iwl_mvm_rx_status {
1042 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
1043 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
1044 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
1045 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
1046 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
1047 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
1048 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
1049 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
1050 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
1051 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
1052 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
1053 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
1054 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
1055 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
1056 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
1057 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
1058 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
1059 RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
1060 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
1061 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
1062 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
1063 RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
1064 RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
1065 RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
1066 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
1067 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
1068};
1069
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1075
1076
1077struct iwl_radio_version_notif {
1078 __le32 radio_flavor;
1079 __le32 radio_step;
1080 __le32 radio_dash;
1081} __packed;
1082
1083enum iwl_card_state_flags {
1084 CARD_ENABLED = 0x00,
1085 HW_CARD_DISABLED = 0x01,
1086 SW_CARD_DISABLED = 0x02,
1087 CT_KILL_CARD_DISABLED = 0x04,
1088 HALT_CARD_DISABLED = 0x08,
1089 CARD_DISABLED_MSK = 0x0f,
1090 CARD_IS_RX_ON = 0x10,
1091};
1092
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1097
1098struct iwl_card_state_notif {
1099 __le32 flags;
1100} __packed;
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1110
1111
1112struct iwl_missed_beacons_notif {
1113 __le32 mac_id;
1114 __le32 consec_missed_beacons_since_last_rx;
1115 __le32 consec_missed_beacons;
1116 __le32 num_expected_beacons;
1117 __le32 num_recvd_beacons;
1118} __packed;
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1126
1127struct iwl_set_calib_default_cmd {
1128 __le16 calib_index;
1129 __le16 length;
1130 u8 data[0];
1131} __packed;
1132
1133#define MAX_PORT_ID_NUM 2
1134
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1147
1148struct iwl_mcast_filter_cmd {
1149 u8 filter_own;
1150 u8 port_id;
1151 u8 count;
1152 u8 pass_all;
1153 u8 bssid[6];
1154 u8 reserved[2];
1155 u8 addr_list[0];
1156} __packed;
1157
1158struct mvm_statistics_dbg {
1159 __le32 burst_check;
1160 __le32 burst_count;
1161 __le32 wait_for_silence_timeout_cnt;
1162 __le32 reserved[3];
1163} __packed;
1164
1165struct mvm_statistics_div {
1166 __le32 tx_on_a;
1167 __le32 tx_on_b;
1168 __le32 exec_time;
1169 __le32 probe_time;
1170 __le32 rssi_ant;
1171 __le32 reserved2;
1172} __packed;
1173
1174struct mvm_statistics_general_common {
1175 __le32 temperature;
1176 __le32 temperature_m;
1177 struct mvm_statistics_dbg dbg;
1178 __le32 sleep_time;
1179 __le32 slots_out;
1180 __le32 slots_idle;
1181 __le32 ttl_timestamp;
1182 struct mvm_statistics_div div;
1183 __le32 rx_enable_counter;
1184
1185
1186
1187
1188
1189 __le32 num_of_sos_states;
1190} __packed;
1191
1192struct mvm_statistics_rx_non_phy {
1193 __le32 bogus_cts;
1194 __le32 bogus_ack;
1195 __le32 non_bssid_frames;
1196
1197 __le32 filtered_frames;
1198
1199 __le32 non_channel_beacons;
1200
1201 __le32 channel_beacons;
1202
1203 __le32 num_missed_bcon;
1204 __le32 adc_rx_saturation_time;
1205
1206 __le32 ina_detection_search_time;
1207
1208 __le32 beacon_silence_rssi_a;
1209 __le32 beacon_silence_rssi_b;
1210 __le32 beacon_silence_rssi_c;
1211 __le32 interference_data_flag;
1212
1213
1214 __le32 channel_load;
1215 __le32 dsp_false_alarms;
1216
1217 __le32 beacon_rssi_a;
1218 __le32 beacon_rssi_b;
1219 __le32 beacon_rssi_c;
1220 __le32 beacon_energy_a;
1221 __le32 beacon_energy_b;
1222 __le32 beacon_energy_c;
1223 __le32 num_bt_kills;
1224 __le32 mac_id;
1225 __le32 directed_data_mpdu;
1226} __packed;
1227
1228struct mvm_statistics_rx_phy {
1229 __le32 ina_cnt;
1230 __le32 fina_cnt;
1231 __le32 plcp_err;
1232 __le32 crc32_err;
1233 __le32 overrun_err;
1234 __le32 early_overrun_err;
1235 __le32 crc32_good;
1236 __le32 false_alarm_cnt;
1237 __le32 fina_sync_err_cnt;
1238 __le32 sfd_timeout;
1239 __le32 fina_timeout;
1240 __le32 unresponded_rts;
1241 __le32 rxe_frame_limit_overrun;
1242 __le32 sent_ack_cnt;
1243 __le32 sent_cts_cnt;
1244 __le32 sent_ba_rsp_cnt;
1245 __le32 dsp_self_kill;
1246 __le32 mh_format_err;
1247 __le32 re_acq_main_rssi_sum;
1248 __le32 reserved;
1249} __packed;
1250
1251struct mvm_statistics_rx_ht_phy {
1252 __le32 plcp_err;
1253 __le32 overrun_err;
1254 __le32 early_overrun_err;
1255 __le32 crc32_good;
1256 __le32 crc32_err;
1257 __le32 mh_format_err;
1258 __le32 agg_crc32_good;
1259 __le32 agg_mpdu_cnt;
1260 __le32 agg_cnt;
1261 __le32 unsupport_mcs;
1262} __packed;
1263
1264#define MAX_CHAINS 3
1265
1266struct mvm_statistics_tx_non_phy_agg {
1267 __le32 ba_timeout;
1268 __le32 ba_reschedule_frames;
1269 __le32 scd_query_agg_frame_cnt;
1270 __le32 scd_query_no_agg;
1271 __le32 scd_query_agg;
1272 __le32 scd_query_mismatch;
1273 __le32 frame_not_ready;
1274 __le32 underrun;
1275 __le32 bt_prio_kill;
1276 __le32 rx_ba_rsp_cnt;
1277 __s8 txpower[MAX_CHAINS];
1278 __s8 reserved;
1279 __le32 reserved2;
1280} __packed;
1281
1282struct mvm_statistics_tx_channel_width {
1283 __le32 ext_cca_narrow_ch20[1];
1284 __le32 ext_cca_narrow_ch40[2];
1285 __le32 ext_cca_narrow_ch80[3];
1286 __le32 ext_cca_narrow_ch160[4];
1287 __le32 last_tx_ch_width_indx;
1288 __le32 rx_detected_per_ch_width[4];
1289 __le32 success_per_ch_width[4];
1290 __le32 fail_per_ch_width[4];
1291};
1292
1293struct mvm_statistics_tx {
1294 __le32 preamble_cnt;
1295 __le32 rx_detected_cnt;
1296 __le32 bt_prio_defer_cnt;
1297 __le32 bt_prio_kill_cnt;
1298 __le32 few_bytes_cnt;
1299 __le32 cts_timeout;
1300 __le32 ack_timeout;
1301 __le32 expected_ack_cnt;
1302 __le32 actual_ack_cnt;
1303 __le32 dump_msdu_cnt;
1304 __le32 burst_abort_next_frame_mismatch_cnt;
1305 __le32 burst_abort_missing_next_frame_cnt;
1306 __le32 cts_timeout_collision;
1307 __le32 ack_or_ba_timeout_collision;
1308 struct mvm_statistics_tx_non_phy_agg agg;
1309 struct mvm_statistics_tx_channel_width channel_width;
1310} __packed;
1311
1312
1313struct mvm_statistics_bt_activity {
1314 __le32 hi_priority_tx_req_cnt;
1315 __le32 hi_priority_tx_denied_cnt;
1316 __le32 lo_priority_tx_req_cnt;
1317 __le32 lo_priority_tx_denied_cnt;
1318 __le32 hi_priority_rx_req_cnt;
1319 __le32 hi_priority_rx_denied_cnt;
1320 __le32 lo_priority_rx_req_cnt;
1321 __le32 lo_priority_rx_denied_cnt;
1322} __packed;
1323
1324struct mvm_statistics_general {
1325 struct mvm_statistics_general_common common;
1326 __le32 beacon_filtered;
1327 __le32 missed_beacons;
1328 __s8 beacon_filter_average_energy;
1329 __s8 beacon_filter_reason;
1330 __s8 beacon_filter_current_energy;
1331 __s8 beacon_filter_reserved;
1332 __le32 beacon_filter_delta_time;
1333 struct mvm_statistics_bt_activity bt_activity;
1334} __packed;
1335
1336struct mvm_statistics_rx {
1337 struct mvm_statistics_rx_phy ofdm;
1338 struct mvm_statistics_rx_phy cck;
1339 struct mvm_statistics_rx_non_phy general;
1340 struct mvm_statistics_rx_ht_phy ofdm_ht;
1341} __packed;
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1359struct iwl_notif_statistics {
1360 __le32 flag;
1361 struct mvm_statistics_rx rx;
1362 struct mvm_statistics_tx tx;
1363 struct mvm_statistics_general general;
1364} __packed;
1365
1366#endif
1367