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34#include <linux/delay.h>
35#include <linux/etherdevice.h>
36#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/eeprom_93cx6.h>
41
42#include "rt2x00.h"
43#include "rt2x00mmio.h"
44#include "rt2x00pci.h"
45#include "rt2800lib.h"
46#include "rt2800mmio.h"
47#include "rt2800.h"
48#include "rt2800pci.h"
49
50
51
52
53static bool modparam_nohwcrypt = false;
54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
57static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
58{
59 return modparam_nohwcrypt;
60}
61
62static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
63{
64 unsigned int i;
65 u32 reg;
66
67
68
69
70 if (rt2x00_is_soc(rt2x00dev))
71 return;
72
73 for (i = 0; i < 200; i++) {
74 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
75
76 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
79 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
80 break;
81
82 udelay(REGISTER_BUSY_DELAY);
83 }
84
85 if (i == 200)
86 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
87
88 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
89 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
90}
91
92static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
93{
94 struct rt2x00_dev *rt2x00dev = eeprom->data;
95 u32 reg;
96
97 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®);
98
99 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
100 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
101 eeprom->reg_data_clock =
102 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
103 eeprom->reg_chip_select =
104 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
105}
106
107static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
108{
109 struct rt2x00_dev *rt2x00dev = eeprom->data;
110 u32 reg = 0;
111
112 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
113 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
114 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
115 !!eeprom->reg_data_clock);
116 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
117 !!eeprom->reg_chip_select);
118
119 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
120}
121
122static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
123{
124 struct eeprom_93cx6 eeprom;
125 u32 reg;
126
127 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®);
128
129 eeprom.data = rt2x00dev;
130 eeprom.register_read = rt2800pci_eepromregister_read;
131 eeprom.register_write = rt2800pci_eepromregister_write;
132 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
133 {
134 case 0:
135 eeprom.width = PCI_EEPROM_WIDTH_93C46;
136 break;
137 case 1:
138 eeprom.width = PCI_EEPROM_WIDTH_93C66;
139 break;
140 default:
141 eeprom.width = PCI_EEPROM_WIDTH_93C86;
142 break;
143 }
144 eeprom.reg_data_in = 0;
145 eeprom.reg_data_out = 0;
146 eeprom.reg_data_clock = 0;
147 eeprom.reg_chip_select = 0;
148
149 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
150 EEPROM_SIZE / sizeof(u16));
151
152 return 0;
153}
154
155static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
156{
157 return rt2800_efuse_detect(rt2x00dev);
158}
159
160static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
161{
162 return rt2800_read_eeprom_efuse(rt2x00dev);
163}
164
165
166
167
168static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
169{
170
171
172
173 if (rt2x00_rt(rt2x00dev, RT3290))
174 return FIRMWARE_RT3290;
175 else
176 return FIRMWARE_RT2860;
177}
178
179static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
180 const u8 *data, const size_t len)
181{
182 u32 reg;
183
184
185
186
187 reg = 0;
188 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
189 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
190
191
192
193
194 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
195 data, len);
196
197 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
198 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
199
200 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
201 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
202
203 return 0;
204}
205
206
207
208
209static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
210{
211 int retval;
212
213 retval = rt2800mmio_enable_radio(rt2x00dev);
214 if (retval)
215 return retval;
216
217
218 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
219 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
220
221 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
222 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
223
224 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
225 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
226
227 return retval;
228}
229
230static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
231 enum dev_state state)
232{
233 if (state == STATE_AWAKE) {
234 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
235 0, 0x02);
236 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
237 } else if (state == STATE_SLEEP) {
238 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
239 0xffffffff);
240 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
241 0xffffffff);
242 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
243 0xff, 0x01);
244 }
245
246 return 0;
247}
248
249static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
250 enum dev_state state)
251{
252 int retval = 0;
253
254 switch (state) {
255 case STATE_RADIO_ON:
256 retval = rt2800pci_enable_radio(rt2x00dev);
257 break;
258 case STATE_RADIO_OFF:
259
260
261
262
263 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
264 break;
265 case STATE_RADIO_IRQ_ON:
266 case STATE_RADIO_IRQ_OFF:
267 rt2800mmio_toggle_irq(rt2x00dev, state);
268 break;
269 case STATE_DEEP_SLEEP:
270 case STATE_SLEEP:
271 case STATE_STANDBY:
272 case STATE_AWAKE:
273 retval = rt2800pci_set_state(rt2x00dev, state);
274 break;
275 default:
276 retval = -ENOTSUPP;
277 break;
278 }
279
280 if (unlikely(retval))
281 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
282 state, retval);
283
284 return retval;
285}
286
287
288
289
290static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
291{
292 int retval;
293
294 if (rt2800pci_efuse_detect(rt2x00dev))
295 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
296 else
297 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
298
299 return retval;
300}
301
302static const struct ieee80211_ops rt2800pci_mac80211_ops = {
303 .tx = rt2x00mac_tx,
304 .start = rt2x00mac_start,
305 .stop = rt2x00mac_stop,
306 .add_interface = rt2x00mac_add_interface,
307 .remove_interface = rt2x00mac_remove_interface,
308 .config = rt2x00mac_config,
309 .configure_filter = rt2x00mac_configure_filter,
310 .set_key = rt2x00mac_set_key,
311 .sw_scan_start = rt2x00mac_sw_scan_start,
312 .sw_scan_complete = rt2x00mac_sw_scan_complete,
313 .get_stats = rt2x00mac_get_stats,
314 .get_tkip_seq = rt2800_get_tkip_seq,
315 .set_rts_threshold = rt2800_set_rts_threshold,
316 .sta_add = rt2x00mac_sta_add,
317 .sta_remove = rt2x00mac_sta_remove,
318 .bss_info_changed = rt2x00mac_bss_info_changed,
319 .conf_tx = rt2800_conf_tx,
320 .get_tsf = rt2800_get_tsf,
321 .rfkill_poll = rt2x00mac_rfkill_poll,
322 .ampdu_action = rt2800_ampdu_action,
323 .flush = rt2x00mac_flush,
324 .get_survey = rt2800_get_survey,
325 .get_ringparam = rt2x00mac_get_ringparam,
326 .tx_frames_pending = rt2x00mac_tx_frames_pending,
327};
328
329static const struct rt2800_ops rt2800pci_rt2800_ops = {
330 .register_read = rt2x00mmio_register_read,
331 .register_read_lock = rt2x00mmio_register_read,
332 .register_write = rt2x00mmio_register_write,
333 .register_write_lock = rt2x00mmio_register_write,
334 .register_multiread = rt2x00mmio_register_multiread,
335 .register_multiwrite = rt2x00mmio_register_multiwrite,
336 .regbusy_read = rt2x00mmio_regbusy_read,
337 .read_eeprom = rt2800pci_read_eeprom,
338 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
339 .drv_write_firmware = rt2800pci_write_firmware,
340 .drv_init_registers = rt2800mmio_init_registers,
341 .drv_get_txwi = rt2800mmio_get_txwi,
342};
343
344static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
345 .irq_handler = rt2800mmio_interrupt,
346 .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
347 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
348 .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
349 .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
350 .autowake_tasklet = rt2800mmio_autowake_tasklet,
351 .probe_hw = rt2800_probe_hw,
352 .get_firmware_name = rt2800pci_get_firmware_name,
353 .check_firmware = rt2800_check_firmware,
354 .load_firmware = rt2800_load_firmware,
355 .initialize = rt2x00mmio_initialize,
356 .uninitialize = rt2x00mmio_uninitialize,
357 .get_entry_state = rt2800mmio_get_entry_state,
358 .clear_entry = rt2800mmio_clear_entry,
359 .set_device_state = rt2800pci_set_device_state,
360 .rfkill_poll = rt2800_rfkill_poll,
361 .link_stats = rt2800_link_stats,
362 .reset_tuner = rt2800_reset_tuner,
363 .link_tuner = rt2800_link_tuner,
364 .gain_calibration = rt2800_gain_calibration,
365 .vco_calibration = rt2800_vco_calibration,
366 .start_queue = rt2800mmio_start_queue,
367 .kick_queue = rt2800mmio_kick_queue,
368 .stop_queue = rt2800mmio_stop_queue,
369 .flush_queue = rt2x00mmio_flush_queue,
370 .write_tx_desc = rt2800mmio_write_tx_desc,
371 .write_tx_data = rt2800_write_tx_data,
372 .write_beacon = rt2800_write_beacon,
373 .clear_beacon = rt2800_clear_beacon,
374 .fill_rxdone = rt2800mmio_fill_rxdone,
375 .config_shared_key = rt2800_config_shared_key,
376 .config_pairwise_key = rt2800_config_pairwise_key,
377 .config_filter = rt2800_config_filter,
378 .config_intf = rt2800_config_intf,
379 .config_erp = rt2800_config_erp,
380 .config_ant = rt2800_config_ant,
381 .config = rt2800_config,
382 .sta_add = rt2800_sta_add,
383 .sta_remove = rt2800_sta_remove,
384};
385
386static const struct rt2x00_ops rt2800pci_ops = {
387 .name = KBUILD_MODNAME,
388 .drv_data_size = sizeof(struct rt2800_drv_data),
389 .max_ap_intf = 8,
390 .eeprom_size = EEPROM_SIZE,
391 .rf_size = RF_SIZE,
392 .tx_queues = NUM_TX_QUEUES,
393 .queue_init = rt2800mmio_queue_init,
394 .lib = &rt2800pci_rt2x00_ops,
395 .drv = &rt2800pci_rt2800_ops,
396 .hw = &rt2800pci_mac80211_ops,
397#ifdef CONFIG_RT2X00_LIB_DEBUGFS
398 .debugfs = &rt2800_rt2x00debug,
399#endif
400};
401
402
403
404
405static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
406 { PCI_DEVICE(0x1814, 0x0601) },
407 { PCI_DEVICE(0x1814, 0x0681) },
408 { PCI_DEVICE(0x1814, 0x0701) },
409 { PCI_DEVICE(0x1814, 0x0781) },
410 { PCI_DEVICE(0x1814, 0x3090) },
411 { PCI_DEVICE(0x1814, 0x3091) },
412 { PCI_DEVICE(0x1814, 0x3092) },
413 { PCI_DEVICE(0x1432, 0x7708) },
414 { PCI_DEVICE(0x1432, 0x7727) },
415 { PCI_DEVICE(0x1432, 0x7728) },
416 { PCI_DEVICE(0x1432, 0x7738) },
417 { PCI_DEVICE(0x1432, 0x7748) },
418 { PCI_DEVICE(0x1432, 0x7758) },
419 { PCI_DEVICE(0x1432, 0x7768) },
420 { PCI_DEVICE(0x1462, 0x891a) },
421 { PCI_DEVICE(0x1a3b, 0x1059) },
422#ifdef CONFIG_RT2800PCI_RT3290
423 { PCI_DEVICE(0x1814, 0x3290) },
424#endif
425#ifdef CONFIG_RT2800PCI_RT33XX
426 { PCI_DEVICE(0x1814, 0x3390) },
427#endif
428#ifdef CONFIG_RT2800PCI_RT35XX
429 { PCI_DEVICE(0x1432, 0x7711) },
430 { PCI_DEVICE(0x1432, 0x7722) },
431 { PCI_DEVICE(0x1814, 0x3060) },
432 { PCI_DEVICE(0x1814, 0x3062) },
433 { PCI_DEVICE(0x1814, 0x3562) },
434 { PCI_DEVICE(0x1814, 0x3592) },
435 { PCI_DEVICE(0x1814, 0x3593) },
436 { PCI_DEVICE(0x1814, 0x359f) },
437#endif
438#ifdef CONFIG_RT2800PCI_RT53XX
439 { PCI_DEVICE(0x1814, 0x5360) },
440 { PCI_DEVICE(0x1814, 0x5362) },
441 { PCI_DEVICE(0x1814, 0x5390) },
442 { PCI_DEVICE(0x1814, 0x5392) },
443 { PCI_DEVICE(0x1814, 0x539a) },
444 { PCI_DEVICE(0x1814, 0x539b) },
445 { PCI_DEVICE(0x1814, 0x539f) },
446#endif
447 { 0, }
448};
449
450MODULE_AUTHOR(DRV_PROJECT);
451MODULE_VERSION(DRV_VERSION);
452MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
453MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
454MODULE_FIRMWARE(FIRMWARE_RT2860);
455MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
456MODULE_LICENSE("GPL");
457
458static int rt2800pci_probe(struct pci_dev *pci_dev,
459 const struct pci_device_id *id)
460{
461 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
462}
463
464static struct pci_driver rt2800pci_driver = {
465 .name = KBUILD_MODNAME,
466 .id_table = rt2800pci_device_table,
467 .probe = rt2800pci_probe,
468 .remove = rt2x00pci_remove,
469 .suspend = rt2x00pci_suspend,
470 .resume = rt2x00pci_resume,
471};
472
473module_pci_driver(rt2800pci_driver);
474
