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30#ifndef __RTL92C_PHY_H__
31#define __RTL92C_PHY_H__
32
33
34#define MAX_TX_COUNT 4
35
36#define MAX_PRECMD_CNT 16
37#define MAX_RFDEPENDCMD_CNT 16
38#define MAX_POSTCMD_CNT 16
39
40#define MAX_DOZE_WAITING_TIMES_9x 64
41
42#define RT_CANNOT_IO(hw) false
43#define HIGHPOWER_RADIOA_ARRAYLEN 22
44
45#define IQK_ADDA_REG_NUM 16
46#define IQK_BB_REG_NUM 9
47#define MAX_TOLERANCE 5
48#define IQK_DELAY_TIME 10
49#define IDX_MAP 15
50
51#define APK_BB_REG_NUM 5
52#define APK_AFE_REG_NUM 16
53#define APK_CURVE_REG_NUM 4
54#define PATH_NUM 2
55
56#define LOOP_LIMIT 5
57#define MAX_STALL_TIME 50
58#define ANTENNADIVERSITYVALUE 0x80
59#define MAX_TXPWR_IDX_NMODE_92S 63
60#define RESET_CNT_LIMIT 3
61
62#define IQK_ADDA_REG_NUM 16
63#define IQK_MAC_REG_NUM 4
64
65#define RF6052_MAX_PATH 2
66
67#define CT_OFFSET_MAC_ADDR 0X16
68
69#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
70#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
71#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
72#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
73#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
74
75#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
76#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
77
78#define CT_OFFSET_CHANNEL_PLAH 0x75
79#define CT_OFFSET_THERMAL_METER 0x78
80#define CT_OFFSET_RF_OPTION 0x79
81#define CT_OFFSET_VERSION 0x7E
82#define CT_OFFSET_CUSTOMER_ID 0x7F
83
84#define RTL92C_MAX_PATH_NUM 2
85
86enum swchnlcmd_id {
87 CMDID_END,
88 CMDID_SET_TXPOWEROWER_LEVEL,
89 CMDID_BBREGWRITE10,
90 CMDID_WRITEPORT_ULONG,
91 CMDID_WRITEPORT_USHORT,
92 CMDID_WRITEPORT_UCHAR,
93 CMDID_RF_WRITEREG,
94};
95
96struct swchnlcmd {
97 enum swchnlcmd_id cmdid;
98 u32 para1;
99 u32 para2;
100 u32 msdelay;
101};
102
103enum hw90_block_e {
104 HW90_BLOCK_MAC = 0,
105 HW90_BLOCK_PHY0 = 1,
106 HW90_BLOCK_PHY1 = 2,
107 HW90_BLOCK_RF = 3,
108 HW90_BLOCK_MAXIMUM = 4,
109};
110
111enum baseband_config_type {
112 BASEBAND_CONFIG_PHY_REG = 0,
113 BASEBAND_CONFIG_AGC_TAB = 1,
114};
115
116enum ra_offset_area {
117 RA_OFFSET_LEGACY_OFDM1,
118 RA_OFFSET_LEGACY_OFDM2,
119 RA_OFFSET_HT_OFDM1,
120 RA_OFFSET_HT_OFDM2,
121 RA_OFFSET_HT_OFDM3,
122 RA_OFFSET_HT_OFDM4,
123 RA_OFFSET_HT_CCK,
124};
125
126enum antenna_path {
127 ANTENNA_NONE,
128 ANTENNA_D,
129 ANTENNA_C,
130 ANTENNA_CD,
131 ANTENNA_B,
132 ANTENNA_BD,
133 ANTENNA_BC,
134 ANTENNA_BCD,
135 ANTENNA_A,
136 ANTENNA_AD,
137 ANTENNA_AC,
138 ANTENNA_ACD,
139 ANTENNA_AB,
140 ANTENNA_ABD,
141 ANTENNA_ABC,
142 ANTENNA_ABCD
143};
144
145struct r_antenna_select_ofdm {
146 u32 r_tx_antenna:4;
147 u32 r_ant_l:4;
148 u32 r_ant_non_ht:4;
149 u32 r_ant_ht1:4;
150 u32 r_ant_ht2:4;
151 u32 r_ant_ht_s1:4;
152 u32 r_ant_non_ht_s1:4;
153 u32 ofdm_txsc:2;
154 u32 reserved:2;
155};
156
157struct r_antenna_select_cck {
158 u8 r_cckrx_enable_2:2;
159 u8 r_cckrx_enable:2;
160 u8 r_ccktx_enable:4;
161};
162
163
164struct efuse_contents {
165 u8 mac_addr[ETH_ALEN];
166 u8 cck_tx_power_idx[6];
167 u8 ht40_1s_tx_power_idx[6];
168 u8 ht40_2s_tx_power_idx_diff[3];
169 u8 ht20_tx_power_idx_diff[3];
170 u8 ofdm_tx_power_idx_diff[3];
171 u8 ht40_max_power_offset[3];
172 u8 ht20_max_power_offset[3];
173 u8 channel_plan;
174 u8 thermal_meter;
175 u8 rf_option[5];
176 u8 version;
177 u8 oem_id;
178 u8 regulatory;
179};
180
181struct tx_power_struct {
182 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
184 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
185 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
186 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
187 u8 legacy_ht_txpowerdiff;
188 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
189 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
190 u8 pwrgroup_cnt;
191 u32 mcs_original_offset[4][16];
192};
193
194enum _ANT_DIV_TYPE {
195 NO_ANTDIV = 0xFF,
196 CG_TRX_HW_ANTDIV = 0x01,
197 CGCS_RX_HW_ANTDIV = 0x02,
198 FIXED_HW_ANTDIV = 0x03,
199 CG_TRX_SMART_ANTDIV = 0x04,
200 CGCS_RX_SW_ANTDIV = 0x05,
201};
202
203u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw,
204 u32 regaddr, u32 bitmask);
205void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
206 u32 regaddr, u32 bitmask, u32 data);
207u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
208 enum radio_path rfpath, u32 regaddr,
209 u32 bitmask);
210void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
211 enum radio_path rfpath, u32 regaddr,
212 u32 bitmask, u32 data);
213bool rtl88e_phy_mac_config(struct ieee80211_hw *hw);
214bool rtl88e_phy_bb_config(struct ieee80211_hw *hw);
215bool rtl88e_phy_rf_config(struct ieee80211_hw *hw);
216void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
217void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw,
218 long *powerlevel);
219void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
220void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
221void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
222 enum nl80211_channel_type ch_type);
223void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
224u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
225void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
226void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
227void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
228bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
229 enum radio_path rfpath);
230bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
231bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
232 enum rf_pwrstate rfpwr_state);
233
234#endif
235
