LXR linux/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2013  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 * wlanfae <wlanfae@realtek.com>
  23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24 * Hsinchu 300, Taiwan.
  25 *
  26 * Larry Finger <Larry.Finger@lwfinger.net>
  27 *
  28 *****************************************************************************/
  29
  30#ifndef __RTL8723E_PWRSEQCMD_H__
  31#define __RTL8723E_PWRSEQCMD_H__
  32
  33#include "../wifi.h"
  34/*---------------------------------------------*/
  35/* The value of cmd: 4 bits */
  36/*---------------------------------------------*/
  37#define PWR_CMD_READ            0x00
  38#define PWR_CMD_WRITE           0x01
  39#define PWR_CMD_POLLING         0x02
  40#define PWR_CMD_DELAY           0x03
  41#define PWR_CMD_END             0x04
  42
  43/* define the base address of each block */
  44#define PWR_BASEADDR_MAC        0x00
  45#define PWR_BASEADDR_USB        0x01
  46#define PWR_BASEADDR_PCIE       0x02
  47#define PWR_BASEADDR_SDIO       0x03
  48
  49#define PWR_INTF_SDIO_MSK       BIT(0)
  50#define PWR_INTF_USB_MSK        BIT(1)
  51#define PWR_INTF_PCI_MSK        BIT(2)
  52#define PWR_INTF_ALL_MSK        (BIT(0)|BIT(1)|BIT(2)|BIT(3))
  53
  54#define PWR_FAB_TSMC_MSK        BIT(0)
  55#define PWR_FAB_UMC_MSK         BIT(1)
  56#define PWR_FAB_ALL_MSK         (BIT(0)|BIT(1)|BIT(2)|BIT(3))
  57
  58#define PWR_CUT_TESTCHIP_MSK    BIT(0)
  59#define PWR_CUT_A_MSK           BIT(1)
  60#define PWR_CUT_B_MSK           BIT(2)
  61#define PWR_CUT_C_MSK           BIT(3)
  62#define PWR_CUT_D_MSK           BIT(4)
  63#define PWR_CUT_E_MSK           BIT(5)
  64#define PWR_CUT_F_MSK           BIT(6)
  65#define PWR_CUT_G_MSK           BIT(7)
  66#define PWR_CUT_ALL_MSK         0xFF
  67
  68enum pwrseq_delay_unit {
  69        PWRSEQ_DELAY_US,
  70        PWRSEQ_DELAY_MS,
  71};
  72
  73struct wlan_pwr_cfg {
  74        u16 offset;
  75        u8 cut_msk;
  76        u8 fab_msk:4;
  77        u8 interface_msk:4;
  78        u8 base:4;
  79        u8 cmd:4;
  80        u8 msk;
  81        u8 value;
  82};
  83
  84#define GET_PWR_CFG_OFFSET(__PWR)       (__PWR.offset)
  85#define GET_PWR_CFG_CUT_MASK(__PWR)     (__PWR.cut_msk)
  86#define GET_PWR_CFG_FAB_MASK(__PWR)     (__PWR.fab_msk)
  87#define GET_PWR_CFG_INTF_MASK(__PWR)    (__PWR.interface_msk)
  88#define GET_PWR_CFG_BASE(__PWR)         (__PWR.base)
  89#define GET_PWR_CFG_CMD(__PWR)          (__PWR.cmd)
  90#define GET_PWR_CFG_MASK(__PWR)         (__PWR.msk)
  91#define GET_PWR_CFG_VALUE(__PWR)        (__PWR.value)
  92
  93bool rtl88_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
  94                                u8 fab_version, u8 interface_type,
  95                                struct wlan_pwr_cfg pwrcfgcmd[]);
  96
  97#endif
  98