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13#include <linux/gpio.h>
14#include <linux/interrupt.h>
15#include <linux/slab.h>
16#include <linux/export.h>
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_platform.h>
21#include <linux/of_address.h>
22#include <linux/of_gpio.h>
23#include <linux/platform_device.h>
24
25#include "pinctrl-lantiq.h"
26
27#include <lantiq_soc.h>
28
29
30#define LTQ_PADC_MUX(x) (x * 0x4)
31
32#define LTQ_PADC_PUEN 0x80
33
34#define LTQ_PADC_PDEN 0x84
35
36#define LTQ_PADC_SRC 0x88
37
38#define LTQ_PADC_DCC 0x8C
39
40#define LTQ_PADC_AVAIL 0xF0
41
42#define pad_r32(p, reg) ltq_r32(p + reg)
43#define pad_w32(p, val, reg) ltq_w32(val, p + reg)
44#define pad_w32_mask(c, clear, set, reg) \
45 pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
46
47#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
48
49#define PORTS 5
50#define PINS 32
51#define PORT(x) (x / PINS)
52#define PORT_PIN(x) (x % PINS)
53
54#define MFP_FALCON(a, f0, f1, f2, f3) \
55{ \
56 .name = #a, \
57 .pin = a, \
58 .func = { \
59 FALCON_MUX_##f0, \
60 FALCON_MUX_##f1, \
61 FALCON_MUX_##f2, \
62 FALCON_MUX_##f3, \
63 }, \
64}
65
66#define GRP_MUX(a, m, p) \
67{ \
68 .name = a, \
69 .mux = FALCON_MUX_##m, \
70 .pins = p, \
71 .npins = ARRAY_SIZE(p), \
72}
73
74enum falcon_mux {
75 FALCON_MUX_GPIO = 0,
76 FALCON_MUX_RST,
77 FALCON_MUX_NTR,
78 FALCON_MUX_PPS,
79 FALCON_MUX_MDIO,
80 FALCON_MUX_LED,
81 FALCON_MUX_SPI,
82 FALCON_MUX_ASC,
83 FALCON_MUX_I2C,
84 FALCON_MUX_HOSTIF,
85 FALCON_MUX_SLIC,
86 FALCON_MUX_JTAG,
87 FALCON_MUX_PCM,
88 FALCON_MUX_MII,
89 FALCON_MUX_PHY,
90 FALCON_MUX_NONE = 0xffff,
91};
92
93static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
94static int pad_count[PORTS];
95
96static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
97{
98 int base = bank * PINS;
99 int i;
100
101 for (i = 0; i < len; i++) {
102
103 char *name = kzalloc(6, GFP_KERNEL);
104 snprintf(name, 6, "io%d", base + i);
105 d[i].number = base + i;
106 d[i].name = name;
107 }
108 pad_count[bank] = len;
109}
110
111static struct ltq_mfp_pin falcon_mfp[] = {
112
113 MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
114 MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
115 MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
116 MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
117 MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
118 MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE),
119 MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
120 MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
121 MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
122 MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
123 MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
124 MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
125 MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
126 MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
127 MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
128 MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
129 MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
130 MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
131 MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
132 MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
133 MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
134 MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
135 MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
136 MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
137 MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
138 MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
139 MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
140 MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
141 MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
142 MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
143 MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
144 MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
145 MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
146 MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
147 MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
148 MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
149 MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
150 MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
151 MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
152 MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
153 MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
154 MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
155 MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
156 MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
157 MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
158 MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
159 MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
160 MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
161 MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
162 MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
163 MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
164 MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
165 MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
166 MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
167};
168
169static const unsigned pins_por[] = {GPIO0};
170static const unsigned pins_ntr[] = {GPIO4};
171static const unsigned pins_ntr8k[] = {GPIO5};
172static const unsigned pins_pps[] = {GPIO5};
173static const unsigned pins_hrst[] = {GPIO6};
174static const unsigned pins_mdio[] = {GPIO7, GPIO8};
175static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
176 GPIO12, GPIO13, GPIO14};
177static const unsigned pins_asc0[] = {GPIO32, GPIO33};
178static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
179static const unsigned pins_spi_cs0[] = {GPIO37};
180static const unsigned pins_spi_cs1[] = {GPIO38};
181static const unsigned pins_i2c[] = {GPIO39, GPIO40};
182static const unsigned pins_jtag[] = {GPIO41};
183static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
184static const unsigned pins_pcm[] = {GPIO44, GPIO45};
185static const unsigned pins_asc1[] = {GPIO44, GPIO45};
186
187static struct ltq_pin_group falcon_grps[] = {
188 GRP_MUX("por", RST, pins_por),
189 GRP_MUX("ntr", NTR, pins_ntr),
190 GRP_MUX("ntr8k", NTR, pins_ntr8k),
191 GRP_MUX("pps", PPS, pins_pps),
192 GRP_MUX("hrst", RST, pins_hrst),
193 GRP_MUX("mdio", MDIO, pins_mdio),
194 GRP_MUX("bootled", LED, pins_bled),
195 GRP_MUX("asc0", ASC, pins_asc0),
196 GRP_MUX("spi", SPI, pins_spi),
197 GRP_MUX("spi cs0", SPI, pins_spi_cs0),
198 GRP_MUX("spi cs1", SPI, pins_spi_cs1),
199 GRP_MUX("i2c", I2C, pins_i2c),
200 GRP_MUX("jtag", JTAG, pins_jtag),
201 GRP_MUX("slic", SLIC, pins_slic),
202 GRP_MUX("pcm", PCM, pins_pcm),
203 GRP_MUX("asc1", ASC, pins_asc1),
204};
205
206static const char * const ltq_rst_grps[] = {"por", "hrst"};
207static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
208static const char * const ltq_mdio_grps[] = {"mdio"};
209static const char * const ltq_bled_grps[] = {"bootled"};
210static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
211static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
212static const char * const ltq_i2c_grps[] = {"i2c"};
213static const char * const ltq_jtag_grps[] = {"jtag"};
214static const char * const ltq_slic_grps[] = {"slic"};
215static const char * const ltq_pcm_grps[] = {"pcm"};
216
217static struct ltq_pmx_func falcon_funcs[] = {
218 {"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
219 {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
220 {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
221 {"led", ARRAY_AND_SIZE(ltq_bled_grps)},
222 {"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
223 {"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
224 {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
225 {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
226 {"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
227 {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
228};
229
230
231
232
233
234static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
235 unsigned group, unsigned long *config)
236{
237 return -ENOTSUPP;
238}
239
240static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
241 unsigned group, unsigned long *configs,
242 unsigned num_configs)
243{
244 return -ENOTSUPP;
245}
246
247static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
248 unsigned pin, unsigned long *config)
249{
250 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
251 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
252 void __iomem *mem = info->membase[PORT(pin)];
253
254 switch (param) {
255 case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
256 *config = LTQ_PINCONF_PACK(param,
257 !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
258 break;
259
260 case LTQ_PINCONF_PARAM_SLEW_RATE:
261 *config = LTQ_PINCONF_PACK(param,
262 !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
263 break;
264
265 case LTQ_PINCONF_PARAM_PULL:
266 if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
267 *config = LTQ_PINCONF_PACK(param, 1);
268 else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
269 *config = LTQ_PINCONF_PACK(param, 2);
270 else
271 *config = LTQ_PINCONF_PACK(param, 0);
272
273 break;
274
275 default:
276 return -ENOTSUPP;
277 }
278
279 return 0;
280}
281
282static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
283 unsigned pin, unsigned long *configs,
284 unsigned num_configs)
285{
286 enum ltq_pinconf_param param;
287 int arg;
288 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
289 void __iomem *mem = info->membase[PORT(pin)];
290 u32 reg;
291 int i;
292
293 for (i = 0; i < num_configs; i++) {
294 param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
295 arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
296
297 switch (param) {
298 case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
299 reg = LTQ_PADC_DCC;
300 break;
301
302 case LTQ_PINCONF_PARAM_SLEW_RATE:
303 reg = LTQ_PADC_SRC;
304 break;
305
306 case LTQ_PINCONF_PARAM_PULL:
307 if (arg == 1)
308 reg = LTQ_PADC_PDEN;
309 else
310 reg = LTQ_PADC_PUEN;
311 break;
312
313 default:
314 pr_err("%s: Invalid config param %04x\n",
315 pinctrl_dev_get_name(pctrldev), param);
316 return -ENOTSUPP;
317 }
318
319 pad_w32(mem, BIT(PORT_PIN(pin)), reg);
320 if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
321 return -ENOTSUPP;
322 }
323
324 return 0;
325}
326
327static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
328 struct seq_file *s, unsigned offset)
329{
330 unsigned long config;
331 struct pin_desc *desc;
332
333 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
334 int port = PORT(offset);
335
336 seq_printf(s, " (port %d) mux %d -- ", port,
337 pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
338
339 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
340 if (!falcon_pinconf_get(pctrldev, offset, &config))
341 seq_printf(s, "pull %d ",
342 (int)LTQ_PINCONF_UNPACK_ARG(config));
343
344 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
345 if (!falcon_pinconf_get(pctrldev, offset, &config))
346 seq_printf(s, "drive-current %d ",
347 (int)LTQ_PINCONF_UNPACK_ARG(config));
348
349 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
350 if (!falcon_pinconf_get(pctrldev, offset, &config))
351 seq_printf(s, "slew-rate %d ",
352 (int)LTQ_PINCONF_UNPACK_ARG(config));
353
354 desc = pin_desc_get(pctrldev, offset);
355 if (desc) {
356 if (desc->gpio_owner)
357 seq_printf(s, " owner: %s", desc->gpio_owner);
358 } else {
359 seq_printf(s, " not registered");
360 }
361}
362
363static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
364 struct seq_file *s, unsigned selector)
365{
366}
367
368static const struct pinconf_ops falcon_pinconf_ops = {
369 .pin_config_get = falcon_pinconf_get,
370 .pin_config_set = falcon_pinconf_set,
371 .pin_config_group_get = falcon_pinconf_group_get,
372 .pin_config_group_set = falcon_pinconf_group_set,
373 .pin_config_dbg_show = falcon_pinconf_dbg_show,
374 .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
375};
376
377static struct pinctrl_desc falcon_pctrl_desc = {
378 .owner = THIS_MODULE,
379 .pins = falcon_pads,
380 .confops = &falcon_pinconf_ops,
381};
382
383static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
384 int mfp, int mux)
385{
386 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
387 int port = PORT(info->mfp[mfp].pin);
388
389 if ((port >= PORTS) || (!info->membase[port]))
390 return -ENODEV;
391
392 pad_w32(info->membase[port], mux,
393 LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
394 return 0;
395}
396
397static const struct ltq_cfg_param falcon_cfg_params[] = {
398 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
399 {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
400 {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
401};
402
403static struct ltq_pinmux_info falcon_info = {
404 .desc = &falcon_pctrl_desc,
405 .apply_mux = falcon_mux_apply,
406 .params = falcon_cfg_params,
407 .num_params = ARRAY_SIZE(falcon_cfg_params),
408};
409
410
411
412
413
414
415int pinctrl_falcon_get_range_size(int id)
416{
417 u32 avail;
418
419 if ((id >= PORTS) || (!falcon_info.membase[id]))
420 return -EINVAL;
421
422 avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
423
424 return fls(avail);
425}
426
427void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
428{
429 pinctrl_add_gpio_range(falcon_info.pctrl, range);
430}
431
432static int pinctrl_falcon_probe(struct platform_device *pdev)
433{
434 struct device_node *np;
435 int pad_count = 0;
436 int ret = 0;
437
438
439 for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
440 struct platform_device *ppdev = of_find_device_by_node(np);
441 const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
442 struct resource res;
443 u32 avail;
444 int pins;
445
446 if (!of_device_is_available(np))
447 continue;
448
449 if (!ppdev) {
450 dev_err(&pdev->dev, "failed to find pad pdev\n");
451 continue;
452 }
453 if (!bank || *bank >= PORTS)
454 continue;
455 if (of_address_to_resource(np, 0, &res))
456 continue;
457 falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
458 if (IS_ERR(falcon_info.clk[*bank])) {
459 dev_err(&ppdev->dev, "failed to get clock\n");
460 return PTR_ERR(falcon_info.clk[*bank]);
461 }
462 falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
463 &res);
464 if (IS_ERR(falcon_info.membase[*bank]))
465 return PTR_ERR(falcon_info.membase[*bank]);
466
467 avail = pad_r32(falcon_info.membase[*bank],
468 LTQ_PADC_AVAIL);
469 pins = fls(avail);
470 lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
471 pad_count += pins;
472 clk_enable(falcon_info.clk[*bank]);
473 dev_dbg(&pdev->dev, "found %s with %d pads\n",
474 res.name, pins);
475 }
476 dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
477 falcon_pctrl_desc.name = dev_name(&pdev->dev);
478 falcon_pctrl_desc.npins = pad_count;
479
480 falcon_info.mfp = falcon_mfp;
481 falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
482 falcon_info.grps = falcon_grps;
483 falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
484 falcon_info.funcs = falcon_funcs;
485 falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
486
487 ret = ltq_pinctrl_register(pdev, &falcon_info);
488 if (!ret)
489 dev_info(&pdev->dev, "Init done\n");
490 return ret;
491}
492
493static const struct of_device_id falcon_match[] = {
494 { .compatible = "lantiq,pinctrl-falcon" },
495 {},
496};
497MODULE_DEVICE_TABLE(of, falcon_match);
498
499static struct platform_driver pinctrl_falcon_driver = {
500 .probe = pinctrl_falcon_probe,
501 .driver = {
502 .name = "pinctrl-falcon",
503 .owner = THIS_MODULE,
504 .of_match_table = falcon_match,
505 },
506};
507
508int __init pinctrl_falcon_init(void)
509{
510 return platform_driver_register(&pinctrl_falcon_driver);
511}
512
513core_initcall_sync(pinctrl_falcon_init);
514
