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34#include "csio_hw.h"
35#include "csio_init.h"
36
37static int
38csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
39{
40 u32 mem_win_base;
41
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50
51
52 mem_win_base = MEMWIN_BASE;
53
54
55
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58
59 csio_wr_reg32(hw, mem_win_base | BIR(0) |
60 WINDOW(ilog2(MEMWIN_APERTURE) - 10),
61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
62 csio_rd_reg32(hw,
63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
64
65 return 0;
66}
67
68
69
70
71static void
72csio_t5_pcie_intr_handler(struct csio_hw *hw)
73{
74 static struct intr_info sysbus_intr_info[] = {
75 { RNPP, "RXNP array parity error", -1, 1 },
76 { RPCP, "RXPC array parity error", -1, 1 },
77 { RCIP, "RXCIF array parity error", -1, 1 },
78 { RCCP, "Rx completions control array parity error", -1, 1 },
79 { RFTP, "RXFT array parity error", -1, 1 },
80 { 0, NULL, 0, 0 }
81 };
82 static struct intr_info pcie_port_intr_info[] = {
83 { TPCP, "TXPC array parity error", -1, 1 },
84 { TNPP, "TXNP array parity error", -1, 1 },
85 { TFTP, "TXFT array parity error", -1, 1 },
86 { TCAP, "TXCA array parity error", -1, 1 },
87 { TCIP, "TXCIF array parity error", -1, 1 },
88 { RCAP, "RXCA array parity error", -1, 1 },
89 { OTDD, "outbound request TLP discarded", -1, 1 },
90 { RDPE, "Rx data parity error", -1, 1 },
91 { TDUE, "Tx uncorrectable data error", -1, 1 },
92 { 0, NULL, 0, 0 }
93 };
94
95 static struct intr_info pcie_intr_info[] = {
96 { MSTGRPPERR, "Master Response Read Queue parity error",
97 -1, 1 },
98 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
99 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
100 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
101 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
102 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
103 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
104 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
105 -1, 1 },
106 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
107 -1, 1 },
108 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
109 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
110 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
111 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
112 { DREQWRPERR, "PCI DMA channel write request parity error",
113 -1, 1 },
114 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
115 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
116 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
117 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
118 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
119 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
120 { FIDPERR, "PCI FID parity error", -1, 1 },
121 { VFIDPERR, "PCI INTx clear parity error", -1, 1 },
122 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
123 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
124 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
125 -1, 1 },
126 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
127 -1, 1 },
128 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
129 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
130 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
131 { READRSPERR, "Outbound read error", -1, 0 },
132 { 0, NULL, 0, 0 }
133 };
134
135 int fat;
136 fat = csio_handle_intr_status(hw,
137 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
138 sysbus_intr_info) +
139 csio_handle_intr_status(hw,
140 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
141 pcie_port_intr_info) +
142 csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
143 if (fat)
144 csio_hw_fatal_err(hw);
145}
146
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152
153
154static unsigned int
155csio_t5_flash_cfg_addr(struct csio_hw *hw)
156{
157 return FLASH_CFG_START;
158}
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171
172static int
173csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
174 uint64_t *ecc)
175{
176 int i;
177 uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
178 uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
179
180 mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD, idx);
181 mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR, idx);
182 mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN, idx);
183 mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
184 mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
185
186 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST)
187 return -EBUSY;
188 csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
189 csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
190 csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
191 csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
192 mc_bist_cmd_reg);
193 i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST,
194 0, 10, 1, NULL);
195 if (i)
196 return i;
197
198#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
199
200 for (i = 15; i >= 0; i--)
201 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
202 if (ecc)
203 *ecc = csio_rd_reg64(hw, MC_DATA(16));
204#undef MC_DATA
205 return 0;
206}
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219
220static int
221csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
222 uint64_t *ecc)
223{
224 int i;
225 uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
226 uint32_t edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
227
228
229
230
231#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
232#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
233
234 edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD, idx);
235 edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
236 edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
237 edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
238 edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
239#undef EDC_REG_T5
240#undef EDC_STRIDE_T5
241
242 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST)
243 return -EBUSY;
244 csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
245 csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
246 csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
247 csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
248 edc_bist_cmd_reg);
249 i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST,
250 0, 10, 1, NULL);
251 if (i)
252 return i;
253
254#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
255
256 for (i = 15; i >= 0; i--)
257 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
258 if (ecc)
259 *ecc = csio_rd_reg64(hw, EDC_DATA(16));
260#undef EDC_DATA
261 return 0;
262}
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280
281static int
282csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
283 u32 len, uint32_t *buf, int dir)
284{
285 u32 pos, start, offset, memoffset;
286 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
287
288
289
290
291 if ((addr & 0x3) || (len & 0x3))
292 return -EINVAL;
293
294
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298
299
300
301 edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR));
302 if (mtype != MEM_MC1)
303 memoffset = (mtype * (edc_size * 1024 * 1024));
304 else {
305 mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw,
306 MA_EXT_MEMORY_BAR));
307 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
308 }
309
310
311 addr = addr + memoffset;
312
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321
322 mem_reg = csio_rd_reg32(hw,
323 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
324 mem_aperture = 1 << (WINDOW(mem_reg) + 10);
325 mem_base = GET_PCIEOFST(mem_reg) << 10;
326
327 start = addr & ~(mem_aperture-1);
328 offset = addr - start;
329 win_pf = V_PFNUM(hw->pfn);
330
331 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
332 mem_reg, mem_aperture);
333 csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",
334 mem_base, memoffset);
335 csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n",
336 start, offset, win_pf);
337 csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",
338 mtype, addr, len);
339
340 for (pos = start; len > 0; pos += mem_aperture, offset = 0) {
341
342
343
344
345
346 csio_wr_reg32(hw, pos | win_pf,
347 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
348 csio_rd_reg32(hw,
349 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
350
351 while (offset < mem_aperture && len > 0) {
352 if (dir)
353 *buf++ = csio_rd_reg32(hw, mem_base + offset);
354 else
355 csio_wr_reg32(hw, *buf++, mem_base + offset);
356
357 offset += sizeof(__be32);
358 len -= sizeof(__be32);
359 }
360 }
361 return 0;
362}
363
364
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368
369
370
371static void
372csio_t5_dfs_create_ext_mem(struct csio_hw *hw)
373{
374 u32 size;
375 int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE);
376 if (i & EXT_MEM_ENABLE) {
377 size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR);
378 csio_add_debugfs_mem(hw, "mc0", MEM_MC0,
379 EXT_MEM_SIZE_GET(size));
380 }
381 if (i & EXT_MEM1_ENABLE) {
382 size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR);
383 csio_add_debugfs_mem(hw, "mc1", MEM_MC1,
384 EXT_MEM_SIZE_GET(size));
385 }
386}
387
388
389struct csio_hw_chip_ops t5_ops = {
390 .chip_set_mem_win = csio_t5_set_mem_win,
391 .chip_pcie_intr_handler = csio_t5_pcie_intr_handler,
392 .chip_flash_cfg_addr = csio_t5_flash_cfg_addr,
393 .chip_mc_read = csio_t5_mc_read,
394 .chip_edc_read = csio_t5_edc_read,
395 .chip_memory_rw = csio_t5_memory_rw,
396 .chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem,
397};
398