1/* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#ifndef __DWC2_CORE_H__ 38#define __DWC2_CORE_H__ 39 40#include <linux/usb/phy.h> 41#include "hw.h" 42 43#ifdef DWC2_LOG_WRITES 44static inline void do_write(u32 value, void *addr) 45{ 46 writel(value, addr); 47 pr_info("INFO:: wrote %08x to %p\n", value, addr); 48} 49 50#undef writel 51#define writel(v, a) do_write(v, a) 52#endif 53 54/* Maximum number of Endpoints/HostChannels */ 55#define MAX_EPS_CHANNELS 16 56 57struct dwc2_hsotg; 58struct dwc2_host_chan; 59 60/* Device States */ 61enum dwc2_lx_state { 62 DWC2_L0, /* On state */ 63 DWC2_L1, /* LPM sleep state */ 64 DWC2_L2, /* USB suspend state */ 65 DWC2_L3, /* Off state */ 66}; 67 68/** 69 * struct dwc2_core_params - Parameters for configuring the core 70 * 71 * @otg_cap: Specifies the OTG capabilities. 72 * 0 - HNP and SRP capable 73 * 1 - SRP Only capable 74 * 2 - No HNP/SRP capable (always available) 75 * Defaults to best available option (0, 1, then 2) 76 * @otg_ver: OTG version supported 77 * 0 - 1.3 (default) 78 * 1 - 2.0 79 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 80 * the data FIFOs. The driver will automatically detect the 81 * value for this parameter if none is specified. 82 * 0 - Slave (always available) 83 * 1 - DMA (default, if available) 84 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 85 * address DMA mode or descriptor DMA mode for accessing 86 * the data FIFOs. The driver will automatically detect the 87 * value for this if none is specified. 88 * 0 - Address DMA 89 * 1 - Descriptor DMA (default, if available) 90 * @speed: Specifies the maximum speed of operation in host and 91 * device mode. The actual speed depends on the speed of 92 * the attached device and the value of phy_type. 93 * 0 - High Speed 94 * (default when phy_type is UTMI+ or ULPI) 95 * 1 - Full Speed 96 * (default when phy_type is Full Speed) 97 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 98 * 1 - Allow dynamic FIFO sizing (default, if available) 99 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 100 * are enabled 101 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 102 * dynamic FIFO sizing is enabled 103 * 16 to 32768 104 * Actual maximum value is autodetected and also 105 * the default. 106 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 107 * in host mode when dynamic FIFO sizing is enabled 108 * 16 to 32768 109 * Actual maximum value is autodetected and also 110 * the default. 111 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 112 * host mode when dynamic FIFO sizing is enabled 113 * 16 to 32768 114 * Actual maximum value is autodetected and also 115 * the default. 116 * @max_transfer_size: The maximum transfer size supported, in bytes 117 * 2047 to 65,535 118 * Actual maximum value is autodetected and also 119 * the default. 120 * @max_packet_count: The maximum number of packets in a transfer 121 * 15 to 511 122 * Actual maximum value is autodetected and also 123 * the default. 124 * @host_channels: The number of host channel registers to use 125 * 1 to 16 126 * Actual maximum value is autodetected and also 127 * the default. 128 * @phy_type: Specifies the type of PHY interface to use. By default, 129 * the driver will automatically detect the phy_type. 130 * 0 - Full Speed Phy 131 * 1 - UTMI+ Phy 132 * 2 - ULPI Phy 133 * Defaults to best available option (2, 1, then 0) 134 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 135 * is applicable for a phy_type of UTMI+ or ULPI. (For a 136 * ULPI phy_type, this parameter indicates the data width 137 * between the MAC and the ULPI Wrapper.) Also, this 138 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 139 * parameter was set to "8 and 16 bits", meaning that the 140 * core has been configured to work at either data path 141 * width. 142 * 8 or 16 (default 16 if available) 143 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 144 * data rate. This parameter is only applicable if phy_type 145 * is ULPI. 146 * 0 - single data rate ULPI interface with 8 bit wide 147 * data bus (default) 148 * 1 - double data rate ULPI interface with 4 bit wide 149 * data bus 150 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 151 * external supply to drive the VBus 152 * 0 - Internal supply (default) 153 * 1 - External supply 154 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 155 * speed PHY. This parameter is only applicable if phy_type 156 * is FS. 157 * 0 - No (default) 158 * 1 - Yes 159 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 160 * 0 - No (default) 161 * 1 - Yes 162 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 163 * when attached to a Full Speed or Low Speed device in 164 * host mode. 165 * 0 - Don't support low power mode (default) 166 * 1 - Support low power mode 167 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 168 * when connected to a Low Speed device in host 169 * mode. This parameter is applicable only if 170 * host_support_fs_ls_low_power is enabled. 171 * 0 - 48 MHz 172 * (default when phy_type is UTMI+ or ULPI) 173 * 1 - 6 MHz 174 * (default when phy_type is Full Speed) 175 * @ts_dline: Enable Term Select Dline pulsing 176 * 0 - No (default) 177 * 1 - Yes 178 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 179 * 0 - No (default for core < 2.92a) 180 * 1 - Yes (default for core >= 2.92a) 181 * @ahbcfg: This field allows the default value of the GAHBCFG 182 * register to be overridden 183 * -1 - GAHBCFG value will be set to 0x06 184 * (INCR4, default) 185 * all others - GAHBCFG value will be overridden with 186 * this value 187 * Not all bits can be controlled like this, the 188 * bits defined by GAHBCFG_CTRL_MASK are controlled 189 * by the driver and are ignored in this 190 * configuration value. 191 * @uframe_sched: True to enable the microframe scheduler 192 * 193 * The following parameters may be specified when starting the module. These 194 * parameters define how the DWC_otg controller should be configured. A 195 * value of -1 (or any other out of range value) for any parameter means 196 * to read the value from hardware (if possible) or use the builtin 197 * default described above. 198 */ 199struct dwc2_core_params { 200 /* 201 * Don't add any non-int members here, this will break 202 * dwc2_set_all_params! 203 */ 204 int otg_cap; 205 int otg_ver; 206 int dma_enable; 207 int dma_desc_enable; 208 int speed; 209 int enable_dynamic_fifo; 210 int en_multiple_tx_fifo; 211 int host_rx_fifo_size; 212 int host_nperio_tx_fifo_size; 213 int host_perio_tx_fifo_size; 214 int max_transfer_size; 215 int max_packet_count; 216 int host_channels; 217 int phy_type; 218 int phy_utmi_width; 219 int phy_ulpi_ddr; 220 int phy_ulpi_ext_vbus; 221 int i2c_enable; 222 int ulpi_fs_ls; 223 int host_support_fs_ls_low_power; 224 int host_ls_low_power_phy_clk; 225 int ts_dline; 226 int reload_ctl; 227 int ahbcfg; 228 int uframe_sched; 229}; 230 231/** 232 * struct dwc2_hw_params - Autodetected parameters. 233 * 234 * These parameters are the various parameters read from hardware 235 * registers during initialization. They typically contain the best 236 * supported or maximum value that can be configured in the 237 * corresponding dwc2_core_params value. 238 * 239 * The values that are not in dwc2_core_params are documented below. 240 * 241 * @op_mode Mode of Operation 242 * 0 - HNP- and SRP-Capable OTG (Host & Device) 243 * 1 - SRP-Capable OTG (Host & Device) 244 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 245 * 3 - SRP-Capable Device 246 * 4 - Non-OTG Device 247 * 5 - SRP-Capable Host 248 * 6 - Non-OTG Host 249 * @arch Architecture 250 * 0 - Slave only 251 * 1 - External DMA 252 * 2 - Internal DMA 253 * @power_optimized Are power optimizations enabled? 254 * @num_dev_ep Number of device endpoints available 255 * @num_dev_perio_in_ep Number of device periodic IN endpoints 256 * avaialable 257 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 258 * Depth 259 * 0 to 30 260 * @host_perio_tx_q_depth 261 * Host Mode Periodic Request Queue Depth 262 * 2, 4 or 8 263 * @nperio_tx_q_depth 264 * Non-Periodic Request Queue Depth 265 * 2, 4 or 8 266 * @hs_phy_type High-speed PHY interface type 267 * 0 - High-speed interface not supported 268 * 1 - UTMI+ 269 * 2 - ULPI 270 * 3 - UTMI+ and ULPI 271 * @fs_phy_type Full-speed PHY interface type 272 * 0 - Full speed interface not supported 273 * 1 - Dedicated full speed interface 274 * 2 - FS pins shared with UTMI+ pins 275 * 3 - FS pins shared with ULPI pins 276 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 277 * @utmi_phy_data_width UTMI+ PHY data width 278 * 0 - 8 bits 279 * 1 - 16 bits 280 * 2 - 8 or 16 bits 281 * @snpsid: Value from SNPSID register 282 */ 283struct dwc2_hw_params { 284 unsigned op_mode:3; 285 unsigned arch:2; 286 unsigned dma_desc_enable:1; 287 unsigned enable_dynamic_fifo:1; 288 unsigned en_multiple_tx_fifo:1; 289 unsigned host_rx_fifo_size:16; 290 unsigned host_nperio_tx_fifo_size:16; 291 unsigned host_perio_tx_fifo_size:16; 292 unsigned nperio_tx_q_depth:3; 293 unsigned host_perio_tx_q_depth:3; 294 unsigned dev_token_q_depth:5; 295 unsigned max_transfer_size:26; 296 unsigned max_packet_count:11; 297 unsigned host_channels:5; 298 unsigned hs_phy_type:2; 299 unsigned fs_phy_type:2; 300 unsigned i2c_enable:1; 301 unsigned num_dev_ep:4; 302 unsigned num_dev_perio_in_ep:4; 303 unsigned total_fifo_size:16; 304 unsigned power_optimized:1; 305 unsigned utmi_phy_data_width:2; 306 u32 snpsid; 307}; 308 309/** 310 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 311 * and periodic schedules 312 * 313 * @dev: The struct device pointer 314 * @regs: Pointer to controller regs 315 * @core_params: Parameters that define how the core should be configured 316 * @hw_params: Parameters that were autodetected from the 317 * hardware registers 318 * @op_state: The operational State, during transitions (a_host=> 319 * a_peripheral and b_device=>b_host) this may not match 320 * the core, but allows the software to determine 321 * transitions 322 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 323 * transfer are in process of being queued 324 * @srp_success: Stores status of SRP request in the case of a FS PHY 325 * with an I2C interface 326 * @wq_otg: Workqueue object used for handling of some interrupts 327 * @wf_otg: Work object for handling Connector ID Status Change 328 * interrupt 329 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 330 * @lx_state: Lx state of connected device 331 * @flags: Flags for handling root port state changes 332 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 333 * Transfers associated with these QHs are not currently 334 * assigned to a host channel. 335 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 336 * Transfers associated with these QHs are currently 337 * assigned to a host channel. 338 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 339 * non-periodic schedule 340 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 341 * list of QHs for periodic transfers that are _not_ 342 * scheduled for the next frame. Each QH in the list has an 343 * interval counter that determines when it needs to be 344 * scheduled for execution. This scheduling mechanism 345 * allows only a simple calculation for periodic bandwidth 346 * used (i.e. must assume that all periodic transfers may 347 * need to execute in the same frame). However, it greatly 348 * simplifies scheduling and should be sufficient for the 349 * vast majority of OTG hosts, which need to connect to a 350 * small number of peripherals at one time. Items move from 351 * this list to periodic_sched_ready when the QH interval 352 * counter is 0 at SOF. 353 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 354 * the next frame, but have not yet been assigned to host 355 * channels. Items move from this list to 356 * periodic_sched_assigned as host channels become 357 * available during the current frame. 358 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 359 * frame that are assigned to host channels. Items move 360 * from this list to periodic_sched_queued as the 361 * transactions for the QH are queued to the DWC_otg 362 * controller. 363 * @periodic_sched_queued: List of periodic QHs that have been queued for 364 * execution. Items move from this list to either 365 * periodic_sched_inactive or periodic_sched_ready when the 366 * channel associated with the transfer is released. If the 367 * interval for the QH is 1, the item moves to 368 * periodic_sched_ready because it must be rescheduled for 369 * the next frame. Otherwise, the item moves to 370 * periodic_sched_inactive. 371 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 372 * This value is in microseconds per (micro)frame. The 373 * assumption is that all periodic transfers may occur in 374 * the same (micro)frame. 375 * @frame_usecs: Internal variable used by the microframe scheduler 376 * @frame_number: Frame number read from the core at SOF. The value ranges 377 * from 0 to HFNUM_MAX_FRNUM. 378 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 379 * SOF enable/disable. 380 * @free_hc_list: Free host channels in the controller. This is a list of 381 * struct dwc2_host_chan items. 382 * @periodic_channels: Number of host channels assigned to periodic transfers. 383 * Currently assuming that there is a dedicated host 384 * channel for each periodic transaction and at least one 385 * host channel is available for non-periodic transactions. 386 * @non_periodic_channels: Number of host channels assigned to non-periodic 387 * transfers 388 * @available_host_channels Number of host channels available for the microframe 389 * scheduler to use 390 * @hc_ptr_array: Array of pointers to the host channel descriptors. 391 * Allows accessing a host channel descriptor given the 392 * host channel number. This is useful in interrupt 393 * handlers. 394 * @status_buf: Buffer used for data received during the status phase of 395 * a control transfer. 396 * @status_buf_dma: DMA address for status_buf 397 * @start_work: Delayed work for handling host A-cable connection 398 * @reset_work: Delayed work for handling a port reset 399 * @lock: Spinlock that protects all the driver data structures 400 * @priv: Stores a pointer to the struct usb_hcd 401 * @otg_port: OTG port number 402 * @frame_list: Frame list 403 * @frame_list_dma: Frame list DMA address 404 */ 405struct dwc2_hsotg { 406 struct device *dev; 407 void __iomem *regs; 408 /** Params detected from hardware */ 409 struct dwc2_hw_params hw_params; 410 /** Params to actually use */ 411 struct dwc2_core_params *core_params; 412 enum usb_otg_state op_state; 413 414 unsigned int queuing_high_bandwidth:1; 415 unsigned int srp_success:1; 416 417 struct workqueue_struct *wq_otg; 418 struct work_struct wf_otg; 419 struct timer_list wkp_timer; 420 enum dwc2_lx_state lx_state; 421 422 union dwc2_hcd_internal_flags { 423 u32 d32; 424 struct { 425 unsigned port_connect_status_change:1; 426 unsigned port_connect_status:1; 427 unsigned port_reset_change:1; 428 unsigned port_enable_change:1; 429 unsigned port_suspend_change:1; 430 unsigned port_over_current_change:1; 431 unsigned port_l1_change:1; 432 unsigned reserved:26; 433 } b; 434 } flags; 435 436 struct list_head non_periodic_sched_inactive; 437 struct list_head non_periodic_sched_active; 438 struct list_head *non_periodic_qh_ptr; 439 struct list_head periodic_sched_inactive; 440 struct list_head periodic_sched_ready; 441 struct list_head periodic_sched_assigned; 442 struct list_head periodic_sched_queued; 443 u16 periodic_usecs; 444 u16 frame_usecs[8]; 445 u16 frame_number; 446 u16 periodic_qh_count; 447 448#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 449#define FRAME_NUM_ARRAY_SIZE 1000 450 u16 last_frame_num; 451 u16 *frame_num_array; 452 u16 *last_frame_num_array; 453 int frame_num_idx; 454 int dumped_frame_num_array; 455#endif 456 457 struct list_head free_hc_list; 458 int periodic_channels; 459 int non_periodic_channels; 460 int available_host_channels; 461 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 462 u8 *status_buf; 463 dma_addr_t status_buf_dma; 464#define DWC2_HCD_STATUS_BUF_SIZE 64 465 466 struct delayed_work start_work; 467 struct delayed_work reset_work; 468 spinlock_t lock; 469 void *priv; 470 u8 otg_port; 471 u32 *frame_list; 472 dma_addr_t frame_list_dma; 473 474 /* DWC OTG HW Release versions */ 475#define DWC2_CORE_REV_2_71a 0x4f54271a 476#define DWC2_CORE_REV_2_90a 0x4f54290a 477#define DWC2_CORE_REV_2_92a 0x4f54292a 478#define DWC2_CORE_REV_2_94a 0x4f54294a 479#define DWC2_CORE_REV_3_00a 0x4f54300a 480 481#ifdef DEBUG 482 u32 frrem_samples; 483 u64 frrem_accum; 484 485 u32 hfnum_7_samples_a; 486 u64 hfnum_7_frrem_accum_a; 487 u32 hfnum_0_samples_a; 488 u64 hfnum_0_frrem_accum_a; 489 u32 hfnum_other_samples_a; 490 u64 hfnum_other_frrem_accum_a; 491 492 u32 hfnum_7_samples_b; 493 u64 hfnum_7_frrem_accum_b; 494 u32 hfnum_0_samples_b; 495 u64 hfnum_0_frrem_accum_b; 496 u32 hfnum_other_samples_b; 497 u64 hfnum_other_frrem_accum_b; 498#endif 499}; 500 501/* Reasons for halting a host channel */ 502enum dwc2_halt_status { 503 DWC2_HC_XFER_NO_HALT_STATUS, 504 DWC2_HC_XFER_COMPLETE, 505 DWC2_HC_XFER_URB_COMPLETE, 506 DWC2_HC_XFER_ACK, 507 DWC2_HC_XFER_NAK, 508 DWC2_HC_XFER_NYET, 509 DWC2_HC_XFER_STALL, 510 DWC2_HC_XFER_XACT_ERR, 511 DWC2_HC_XFER_FRAME_OVERRUN, 512 DWC2_HC_XFER_BABBLE_ERR, 513 DWC2_HC_XFER_DATA_TOGGLE_ERR, 514 DWC2_HC_XFER_AHB_ERR, 515 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 516 DWC2_HC_XFER_URB_DEQUEUE, 517}; 518 519/* 520 * The following functions support initialization of the core driver component 521 * and the DWC_otg controller 522 */ 523extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 524 525/* 526 * Host core Functions. 527 * The following functions support managing the DWC_otg controller in host 528 * mode. 529 */ 530extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 531extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 532 enum dwc2_halt_status halt_status); 533extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 534 struct dwc2_host_chan *chan); 535extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 536 struct dwc2_host_chan *chan); 537extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 538 struct dwc2_host_chan *chan); 539extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 540 struct dwc2_host_chan *chan); 541extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 542 struct dwc2_host_chan *chan); 543extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 544extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 545 546extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 547extern int dwc2_check_core_status(struct dwc2_hsotg *hsotg); 548 549/* 550 * Common core Functions. 551 * The following functions support managing the DWC_otg controller in either 552 * device or host mode. 553 */ 554extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 555extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 556extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 557 558extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 559extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 560extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 561 562/* This function should be called on every hardware interrupt. */ 563extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 564 565/* OTG Core Parameters */ 566 567/* 568 * Specifies the OTG capabilities. The driver will automatically 569 * detect the value for this parameter if none is specified. 570 * 0 - HNP and SRP capable (default) 571 * 1 - SRP Only capable 572 * 2 - No HNP/SRP capable 573 */ 574extern int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 575#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 576#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 577#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 578 579/* 580 * Specifies whether to use slave or DMA mode for accessing the data 581 * FIFOs. The driver will automatically detect the value for this 582 * parameter if none is specified. 583 * 0 - Slave 584 * 1 - DMA (default, if available) 585 */ 586extern int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 587 588/* 589 * When DMA mode is enabled specifies whether to use 590 * address DMA or DMA Descritor mode for accessing the data 591 * FIFOs in device mode. The driver will automatically detect 592 * the value for this parameter if none is specified. 593 * 0 - address DMA 594 * 1 - DMA Descriptor(default, if available) 595 */ 596extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 597 598/* 599 * Specifies the maximum speed of operation in host and device mode. 600 * The actual speed depends on the speed of the attached device and 601 * the value of phy_type. The actual speed depends on the speed of the 602 * attached device. 603 * 0 - High Speed (default) 604 * 1 - Full Speed 605 */ 606extern int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 607#define DWC2_SPEED_PARAM_HIGH 0 608#define DWC2_SPEED_PARAM_FULL 1 609 610/* 611 * Specifies whether low power mode is supported when attached 612 * to a Full Speed or Low Speed device in host mode. 613 * 614 * 0 - Don't support low power mode (default) 615 * 1 - Support low power mode 616 */ 617extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 618 int val); 619 620/* 621 * Specifies the PHY clock rate in low power mode when connected to a 622 * Low Speed device in host mode. This parameter is applicable only if 623 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 624 * then defaults to 6 MHZ otherwise 48 MHZ. 625 * 626 * 0 - 48 MHz 627 * 1 - 6 MHz 628 */ 629extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 630 int val); 631#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 632#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 633 634/* 635 * 0 - Use cC FIFO size parameters 636 * 1 - Allow dynamic FIFO sizing (default) 637 */ 638extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 639 int val); 640 641/* 642 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 643 * FIFO sizing is enabled. 644 * 16 to 32768 (default 1024) 645 */ 646extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 647 648/* 649 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 650 * when Dynamic FIFO sizing is enabled in the core. 651 * 16 to 32768 (default 256) 652 */ 653extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 654 int val); 655 656/* 657 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 658 * FIFO sizing is enabled. 659 * 16 to 32768 (default 256) 660 */ 661extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 662 int val); 663 664/* 665 * The maximum transfer size supported in bytes. 666 * 2047 to 65,535 (default 65,535) 667 */ 668extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 669 670/* 671 * The maximum number of packets in a transfer. 672 * 15 to 511 (default 511) 673 */ 674extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 675 676/* 677 * The number of host channel registers to use. 678 * 1 to 16 (default 11) 679 * Note: The FPGA configuration supports a maximum of 11 host channels. 680 */ 681extern int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 682 683/* 684 * Specifies the type of PHY interface to use. By default, the driver 685 * will automatically detect the phy_type. 686 * 687 * 0 - Full Speed PHY 688 * 1 - UTMI+ (default) 689 * 2 - ULPI 690 */ 691extern int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 692#define DWC2_PHY_TYPE_PARAM_FS 0 693#define DWC2_PHY_TYPE_PARAM_UTMI 1 694#define DWC2_PHY_TYPE_PARAM_ULPI 2 695 696/* 697 * Specifies the UTMI+ Data Width. This parameter is 698 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 699 * PHY_TYPE, this parameter indicates the data width between 700 * the MAC and the ULPI Wrapper.) Also, this parameter is 701 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 702 * to "8 and 16 bits", meaning that the core has been 703 * configured to work at either data path width. 704 * 705 * 8 or 16 bits (default 16) 706 */ 707extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 708 709/* 710 * Specifies whether the ULPI operates at double or single 711 * data rate. This parameter is only applicable if PHY_TYPE is 712 * ULPI. 713 * 714 * 0 - single data rate ULPI interface with 8 bit wide data 715 * bus (default) 716 * 1 - double data rate ULPI interface with 4 bit wide data 717 * bus 718 */ 719extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 720 721/* 722 * Specifies whether to use the internal or external supply to 723 * drive the vbus with a ULPI phy. 724 */ 725extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 726#define DWC2_PHY_ULPI_INTERNAL_VBUS 0 727#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 728 729/* 730 * Specifies whether to use the I2Cinterface for full speed PHY. This 731 * parameter is only applicable if PHY_TYPE is FS. 732 * 0 - No (default) 733 * 1 - Yes 734 */ 735extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 736 737extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 738 739extern int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 740 741/* 742 * Specifies whether dedicated transmit FIFOs are 743 * enabled for non periodic IN endpoints in device mode 744 * 0 - No 745 * 1 - Yes 746 */ 747extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 748 int val); 749 750extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 751 752extern int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 753 754extern int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 755 756/* 757 * Dump core registers and SPRAM 758 */ 759extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 760extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 761extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 762 763/* 764 * Return OTG version - either 1.3 or 2.0 765 */ 766extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 767 768#endif /* __DWC2_CORE_H__ */ 769