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27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_s3c.h>
43#include <linux/delay.h>
44#include <linux/clk.h>
45#include <linux/cpufreq.h>
46#include <linux/of.h>
47
48#include <asm/irq.h>
49
50#ifdef CONFIG_SAMSUNG_CLOCK
51#include <plat/clock.h>
52#endif
53
54#include "samsung.h"
55
56
57
58#define S3C24XX_SERIAL_NAME "ttySAC"
59#define S3C24XX_SERIAL_MAJOR 204
60#define S3C24XX_SERIAL_MINOR 64
61
62
63
64#define tx_enabled(port) ((port)->unused[0])
65#define rx_enabled(port) ((port)->unused[1])
66
67
68#define RXSTAT_DUMMY_READ (0x10000000)
69
70static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71{
72 return container_of(port, struct s3c24xx_uart_port, port);
73}
74
75
76
77static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78{
79 return to_platform_device(port->dev)->name;
80}
81
82static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83{
84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
85}
86
87
88
89
90
91
92static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93{
94 return to_ourport(port)->info->type == PORT_S3C6400;
95}
96
97static void s3c24xx_serial_rx_enable(struct uart_port *port)
98{
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118}
119
120static void s3c24xx_serial_rx_disable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133}
134
135static void s3c24xx_serial_stop_tx(struct uart_port *port)
136{
137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
139 if (tx_enabled(port)) {
140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149}
150
151static void s3c24xx_serial_start_tx(struct uart_port *port)
152{
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
164 tx_enabled(port) = 1;
165 }
166}
167
168static void s3c24xx_serial_stop_rx(struct uart_port *port)
169{
170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
179 rx_enabled(port) = 0;
180 }
181}
182
183static void s3c24xx_serial_enable_ms(struct uart_port *port)
184{
185}
186
187static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188{
189 return to_ourport(port)->info;
190}
191
192static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193{
194 struct s3c24xx_uart_port *ourport;
195
196 if (port->dev == NULL)
197 return NULL;
198
199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
201}
202
203static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205{
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
209 return ourport->port.fifosize;
210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212}
213
214
215
216#define S3C2410_UERSTAT_PARITY (0x1000)
217
218static irqreturn_t
219s3c24xx_serial_rx_chars(int irq, void *dev_id)
220{
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
223 unsigned int ufcon, ch, flag, ufstat, uerstat;
224 unsigned long flags;
225 int max_count = 64;
226
227 spin_lock_irqsave(&port->lock, flags);
228
229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234 break;
235
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
238
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
241
242 if (rx_enabled(port)) {
243 if (!txe) {
244 rx_enabled(port) = 0;
245 continue;
246 }
247 } else {
248 if (txe) {
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 spin_unlock_irqrestore(&port->lock,
253 flags);
254 goto out;
255 }
256 continue;
257 }
258 }
259
260
261
262 flag = TTY_NORMAL;
263 port->icount.rx++;
264
265 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
266 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
267 ch, uerstat);
268
269
270 if (uerstat & S3C2410_UERSTAT_BREAK) {
271 dbg("break!\n");
272 port->icount.brk++;
273 if (uart_handle_break(port))
274 goto ignore_char;
275 }
276
277 if (uerstat & S3C2410_UERSTAT_FRAME)
278 port->icount.frame++;
279 if (uerstat & S3C2410_UERSTAT_OVERRUN)
280 port->icount.overrun++;
281
282 uerstat &= port->read_status_mask;
283
284 if (uerstat & S3C2410_UERSTAT_BREAK)
285 flag = TTY_BREAK;
286 else if (uerstat & S3C2410_UERSTAT_PARITY)
287 flag = TTY_PARITY;
288 else if (uerstat & (S3C2410_UERSTAT_FRAME |
289 S3C2410_UERSTAT_OVERRUN))
290 flag = TTY_FRAME;
291 }
292
293 if (uart_handle_sysrq_char(port, ch))
294 goto ignore_char;
295
296 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
297 ch, flag);
298
299 ignore_char:
300 continue;
301 }
302
303 spin_unlock_irqrestore(&port->lock, flags);
304 tty_flip_buffer_push(&port->state->port);
305
306 out:
307 return IRQ_HANDLED;
308}
309
310static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
311{
312 struct s3c24xx_uart_port *ourport = id;
313 struct uart_port *port = &ourport->port;
314 struct circ_buf *xmit = &port->state->xmit;
315 unsigned long flags;
316 int count = 256;
317
318 spin_lock_irqsave(&port->lock, flags);
319
320 if (port->x_char) {
321 wr_regb(port, S3C2410_UTXH, port->x_char);
322 port->icount.tx++;
323 port->x_char = 0;
324 goto out;
325 }
326
327
328
329
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
332 s3c24xx_serial_stop_tx(port);
333 goto out;
334 }
335
336
337
338 while (!uart_circ_empty(xmit) && count-- > 0) {
339 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
340 break;
341
342 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
344 port->icount.tx++;
345 }
346
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
348 spin_unlock(&port->lock);
349 uart_write_wakeup(port);
350 spin_lock(&port->lock);
351 }
352
353 if (uart_circ_empty(xmit))
354 s3c24xx_serial_stop_tx(port);
355
356 out:
357 spin_unlock_irqrestore(&port->lock, flags);
358 return IRQ_HANDLED;
359}
360
361
362static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
363{
364 struct s3c24xx_uart_port *ourport = id;
365 struct uart_port *port = &ourport->port;
366 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
367 irqreturn_t ret = IRQ_HANDLED;
368
369 if (pend & S3C64XX_UINTM_RXD_MSK) {
370 ret = s3c24xx_serial_rx_chars(irq, id);
371 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
372 }
373 if (pend & S3C64XX_UINTM_TXD_MSK) {
374 ret = s3c24xx_serial_tx_chars(irq, id);
375 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
376 }
377 return ret;
378}
379
380static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
381{
382 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
383 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
384 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
385
386 if (ufcon & S3C2410_UFCON_FIFOMODE) {
387 if ((ufstat & info->tx_fifomask) != 0 ||
388 (ufstat & info->tx_fifofull))
389 return 0;
390
391 return 1;
392 }
393
394 return s3c24xx_serial_txempty_nofifo(port);
395}
396
397
398static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
399{
400 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
401
402 if (umstat & S3C2410_UMSTAT_CTS)
403 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
404 else
405 return TIOCM_CAR | TIOCM_DSR;
406}
407
408static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
409{
410 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
411
412 if (mctrl & TIOCM_RTS)
413 umcon |= S3C2410_UMCOM_RTS_LOW;
414 else
415 umcon &= ~S3C2410_UMCOM_RTS_LOW;
416
417 wr_regl(port, S3C2410_UMCON, umcon);
418}
419
420static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
421{
422 unsigned long flags;
423 unsigned int ucon;
424
425 spin_lock_irqsave(&port->lock, flags);
426
427 ucon = rd_regl(port, S3C2410_UCON);
428
429 if (break_state)
430 ucon |= S3C2410_UCON_SBREAK;
431 else
432 ucon &= ~S3C2410_UCON_SBREAK;
433
434 wr_regl(port, S3C2410_UCON, ucon);
435
436 spin_unlock_irqrestore(&port->lock, flags);
437}
438
439static void s3c24xx_serial_shutdown(struct uart_port *port)
440{
441 struct s3c24xx_uart_port *ourport = to_ourport(port);
442
443 if (ourport->tx_claimed) {
444 if (!s3c24xx_serial_has_interrupt_mask(port))
445 free_irq(ourport->tx_irq, ourport);
446 tx_enabled(port) = 0;
447 ourport->tx_claimed = 0;
448 }
449
450 if (ourport->rx_claimed) {
451 if (!s3c24xx_serial_has_interrupt_mask(port))
452 free_irq(ourport->rx_irq, ourport);
453 ourport->rx_claimed = 0;
454 rx_enabled(port) = 0;
455 }
456
457
458 if (s3c24xx_serial_has_interrupt_mask(port)) {
459 free_irq(port->irq, ourport);
460
461 wr_regl(port, S3C64XX_UINTP, 0xf);
462 wr_regl(port, S3C64XX_UINTM, 0xf);
463 }
464}
465
466static int s3c24xx_serial_startup(struct uart_port *port)
467{
468 struct s3c24xx_uart_port *ourport = to_ourport(port);
469 int ret;
470
471 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
472 port->mapbase, port->membase);
473
474 rx_enabled(port) = 1;
475
476 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
477 s3c24xx_serial_portname(port), ourport);
478
479 if (ret != 0) {
480 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
481 return ret;
482 }
483
484 ourport->rx_claimed = 1;
485
486 dbg("requesting tx irq...\n");
487
488 tx_enabled(port) = 1;
489
490 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
491 s3c24xx_serial_portname(port), ourport);
492
493 if (ret) {
494 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
495 goto err;
496 }
497
498 ourport->tx_claimed = 1;
499
500 dbg("s3c24xx_serial_startup ok\n");
501
502
503
504
505 return ret;
506
507 err:
508 s3c24xx_serial_shutdown(port);
509 return ret;
510}
511
512static int s3c64xx_serial_startup(struct uart_port *port)
513{
514 struct s3c24xx_uart_port *ourport = to_ourport(port);
515 int ret;
516
517 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
518 port->mapbase, port->membase);
519
520 wr_regl(port, S3C64XX_UINTM, 0xf);
521
522 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
523 s3c24xx_serial_portname(port), ourport);
524 if (ret) {
525 dev_err(port->dev, "cannot get irq %d\n", port->irq);
526 return ret;
527 }
528
529
530 rx_enabled(port) = 1;
531 ourport->rx_claimed = 1;
532 tx_enabled(port) = 0;
533 ourport->tx_claimed = 1;
534
535
536 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
537 dbg("s3c64xx_serial_startup ok\n");
538 return ret;
539}
540
541
542
543static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
544 unsigned int old)
545{
546 struct s3c24xx_uart_port *ourport = to_ourport(port);
547
548 ourport->pm_level = level;
549
550 switch (level) {
551 case 3:
552 if (!IS_ERR(ourport->baudclk))
553 clk_disable_unprepare(ourport->baudclk);
554
555 clk_disable_unprepare(ourport->clk);
556 break;
557
558 case 0:
559 clk_prepare_enable(ourport->clk);
560
561 if (!IS_ERR(ourport->baudclk))
562 clk_prepare_enable(ourport->baudclk);
563
564 break;
565 default:
566 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
567 }
568}
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583#define MAX_CLK_NAME_LENGTH 15
584
585static inline int s3c24xx_serial_getsource(struct uart_port *port)
586{
587 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
588 unsigned int ucon;
589
590 if (info->num_clks == 1)
591 return 0;
592
593 ucon = rd_regl(port, S3C2410_UCON);
594 ucon &= info->clksel_mask;
595 return ucon >> info->clksel_shift;
596}
597
598static void s3c24xx_serial_setsource(struct uart_port *port,
599 unsigned int clk_sel)
600{
601 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
602 unsigned int ucon;
603
604 if (info->num_clks == 1)
605 return;
606
607 ucon = rd_regl(port, S3C2410_UCON);
608 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
609 return;
610
611 ucon &= ~info->clksel_mask;
612 ucon |= clk_sel << info->clksel_shift;
613 wr_regl(port, S3C2410_UCON, ucon);
614}
615
616static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
617 unsigned int req_baud, struct clk **best_clk,
618 unsigned int *clk_num)
619{
620 struct s3c24xx_uart_info *info = ourport->info;
621 struct clk *clk;
622 unsigned long rate;
623 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
624 char clkname[MAX_CLK_NAME_LENGTH];
625 int calc_deviation, deviation = (1 << 30) - 1;
626
627 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
628 ourport->info->def_clk_sel;
629 for (cnt = 0; cnt < info->num_clks; cnt++) {
630 if (!(clk_sel & (1 << cnt)))
631 continue;
632
633 sprintf(clkname, "clk_uart_baud%d", cnt);
634 clk = clk_get(ourport->port.dev, clkname);
635 if (IS_ERR(clk))
636 continue;
637
638 rate = clk_get_rate(clk);
639 if (!rate)
640 continue;
641
642 if (ourport->info->has_divslot) {
643 unsigned long div = rate / req_baud;
644
645
646
647
648
649
650
651
652
653 quot = div / 16;
654 baud = rate / div;
655 } else {
656 quot = (rate + (8 * req_baud)) / (16 * req_baud);
657 baud = rate / (quot * 16);
658 }
659 quot--;
660
661 calc_deviation = req_baud - baud;
662 if (calc_deviation < 0)
663 calc_deviation = -calc_deviation;
664
665 if (calc_deviation < deviation) {
666 *best_clk = clk;
667 best_quot = quot;
668 *clk_num = cnt;
669 deviation = calc_deviation;
670 }
671 }
672
673 return best_quot;
674}
675
676
677
678
679
680
681static u16 udivslot_table[16] = {
682 [0] = 0x0000,
683 [1] = 0x0080,
684 [2] = 0x0808,
685 [3] = 0x0888,
686 [4] = 0x2222,
687 [5] = 0x4924,
688 [6] = 0x4A52,
689 [7] = 0x54AA,
690 [8] = 0x5555,
691 [9] = 0xD555,
692 [10] = 0xD5D5,
693 [11] = 0xDDD5,
694 [12] = 0xDDDD,
695 [13] = 0xDFDD,
696 [14] = 0xDFDF,
697 [15] = 0xFFDF,
698};
699
700static void s3c24xx_serial_set_termios(struct uart_port *port,
701 struct ktermios *termios,
702 struct ktermios *old)
703{
704 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
705 struct s3c24xx_uart_port *ourport = to_ourport(port);
706 struct clk *clk = ERR_PTR(-EINVAL);
707 unsigned long flags;
708 unsigned int baud, quot, clk_sel = 0;
709 unsigned int ulcon;
710 unsigned int umcon;
711 unsigned int udivslot = 0;
712
713
714
715
716 termios->c_cflag &= ~(HUPCL | CMSPAR);
717 termios->c_cflag |= CLOCAL;
718
719
720
721
722
723 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
724 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
725 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
726 quot = port->custom_divisor;
727 if (IS_ERR(clk))
728 return;
729
730
731
732 if (ourport->baudclk != clk) {
733 s3c24xx_serial_setsource(port, clk_sel);
734
735 if (!IS_ERR(ourport->baudclk)) {
736 clk_disable_unprepare(ourport->baudclk);
737 ourport->baudclk = ERR_PTR(-EINVAL);
738 }
739
740 clk_prepare_enable(clk);
741
742 ourport->baudclk = clk;
743 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
744 }
745
746 if (ourport->info->has_divslot) {
747 unsigned int div = ourport->baudclk_rate / baud;
748
749 if (cfg->has_fracval) {
750 udivslot = (div & 15);
751 dbg("fracval = %04x\n", udivslot);
752 } else {
753 udivslot = udivslot_table[div & 15];
754 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
755 }
756 }
757
758 switch (termios->c_cflag & CSIZE) {
759 case CS5:
760 dbg("config: 5bits/char\n");
761 ulcon = S3C2410_LCON_CS5;
762 break;
763 case CS6:
764 dbg("config: 6bits/char\n");
765 ulcon = S3C2410_LCON_CS6;
766 break;
767 case CS7:
768 dbg("config: 7bits/char\n");
769 ulcon = S3C2410_LCON_CS7;
770 break;
771 case CS8:
772 default:
773 dbg("config: 8bits/char\n");
774 ulcon = S3C2410_LCON_CS8;
775 break;
776 }
777
778
779 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
780
781 if (termios->c_cflag & CSTOPB)
782 ulcon |= S3C2410_LCON_STOPB;
783
784 if (termios->c_cflag & PARENB) {
785 if (termios->c_cflag & PARODD)
786 ulcon |= S3C2410_LCON_PODD;
787 else
788 ulcon |= S3C2410_LCON_PEVEN;
789 } else {
790 ulcon |= S3C2410_LCON_PNONE;
791 }
792
793 spin_lock_irqsave(&port->lock, flags);
794
795 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
796 ulcon, quot, udivslot);
797
798 wr_regl(port, S3C2410_ULCON, ulcon);
799 wr_regl(port, S3C2410_UBRDIV, quot);
800
801 umcon = rd_regl(port, S3C2410_UMCON);
802 if (termios->c_cflag & CRTSCTS) {
803 umcon |= S3C2410_UMCOM_AFC;
804
805 umcon &= ~S3C2412_UMCON_AFC_8;
806 } else {
807 umcon &= ~S3C2410_UMCOM_AFC;
808 }
809 wr_regl(port, S3C2410_UMCON, umcon);
810
811 if (ourport->info->has_divslot)
812 wr_regl(port, S3C2443_DIVSLOT, udivslot);
813
814 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
815 rd_regl(port, S3C2410_ULCON),
816 rd_regl(port, S3C2410_UCON),
817 rd_regl(port, S3C2410_UFCON));
818
819
820
821
822 uart_update_timeout(port, termios->c_cflag, baud);
823
824
825
826
827 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
828 if (termios->c_iflag & INPCK)
829 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
830
831
832
833
834 port->ignore_status_mask = 0;
835 if (termios->c_iflag & IGNPAR)
836 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
837 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
838 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
839
840
841
842
843 if ((termios->c_cflag & CREAD) == 0)
844 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
845
846 spin_unlock_irqrestore(&port->lock, flags);
847}
848
849static const char *s3c24xx_serial_type(struct uart_port *port)
850{
851 switch (port->type) {
852 case PORT_S3C2410:
853 return "S3C2410";
854 case PORT_S3C2440:
855 return "S3C2440";
856 case PORT_S3C2412:
857 return "S3C2412";
858 case PORT_S3C6400:
859 return "S3C6400/10";
860 default:
861 return NULL;
862 }
863}
864
865#define MAP_SIZE (0x100)
866
867static void s3c24xx_serial_release_port(struct uart_port *port)
868{
869 release_mem_region(port->mapbase, MAP_SIZE);
870}
871
872static int s3c24xx_serial_request_port(struct uart_port *port)
873{
874 const char *name = s3c24xx_serial_portname(port);
875 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
876}
877
878static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
879{
880 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
881
882 if (flags & UART_CONFIG_TYPE &&
883 s3c24xx_serial_request_port(port) == 0)
884 port->type = info->type;
885}
886
887
888
889
890static int
891s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
892{
893 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
894
895 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
896 return -EINVAL;
897
898 return 0;
899}
900
901
902#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
903
904static struct console s3c24xx_serial_console;
905
906static int __init s3c24xx_serial_console_init(void)
907{
908 register_console(&s3c24xx_serial_console);
909 return 0;
910}
911console_initcall(s3c24xx_serial_console_init);
912
913#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
914#else
915#define S3C24XX_SERIAL_CONSOLE NULL
916#endif
917
918#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
919static int s3c24xx_serial_get_poll_char(struct uart_port *port);
920static void s3c24xx_serial_put_poll_char(struct uart_port *port,
921 unsigned char c);
922#endif
923
924static struct uart_ops s3c24xx_serial_ops = {
925 .pm = s3c24xx_serial_pm,
926 .tx_empty = s3c24xx_serial_tx_empty,
927 .get_mctrl = s3c24xx_serial_get_mctrl,
928 .set_mctrl = s3c24xx_serial_set_mctrl,
929 .stop_tx = s3c24xx_serial_stop_tx,
930 .start_tx = s3c24xx_serial_start_tx,
931 .stop_rx = s3c24xx_serial_stop_rx,
932 .enable_ms = s3c24xx_serial_enable_ms,
933 .break_ctl = s3c24xx_serial_break_ctl,
934 .startup = s3c24xx_serial_startup,
935 .shutdown = s3c24xx_serial_shutdown,
936 .set_termios = s3c24xx_serial_set_termios,
937 .type = s3c24xx_serial_type,
938 .release_port = s3c24xx_serial_release_port,
939 .request_port = s3c24xx_serial_request_port,
940 .config_port = s3c24xx_serial_config_port,
941 .verify_port = s3c24xx_serial_verify_port,
942#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
943 .poll_get_char = s3c24xx_serial_get_poll_char,
944 .poll_put_char = s3c24xx_serial_put_poll_char,
945#endif
946};
947
948static struct uart_driver s3c24xx_uart_drv = {
949 .owner = THIS_MODULE,
950 .driver_name = "s3c2410_serial",
951 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
952 .cons = S3C24XX_SERIAL_CONSOLE,
953 .dev_name = S3C24XX_SERIAL_NAME,
954 .major = S3C24XX_SERIAL_MAJOR,
955 .minor = S3C24XX_SERIAL_MINOR,
956};
957
958static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
959 [0] = {
960 .port = {
961 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
962 .iotype = UPIO_MEM,
963 .uartclk = 0,
964 .fifosize = 16,
965 .ops = &s3c24xx_serial_ops,
966 .flags = UPF_BOOT_AUTOCONF,
967 .line = 0,
968 }
969 },
970 [1] = {
971 .port = {
972 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
973 .iotype = UPIO_MEM,
974 .uartclk = 0,
975 .fifosize = 16,
976 .ops = &s3c24xx_serial_ops,
977 .flags = UPF_BOOT_AUTOCONF,
978 .line = 1,
979 }
980 },
981#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
982
983 [2] = {
984 .port = {
985 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
986 .iotype = UPIO_MEM,
987 .uartclk = 0,
988 .fifosize = 16,
989 .ops = &s3c24xx_serial_ops,
990 .flags = UPF_BOOT_AUTOCONF,
991 .line = 2,
992 }
993 },
994#endif
995#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
996 [3] = {
997 .port = {
998 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
999 .iotype = UPIO_MEM,
1000 .uartclk = 0,
1001 .fifosize = 16,
1002 .ops = &s3c24xx_serial_ops,
1003 .flags = UPF_BOOT_AUTOCONF,
1004 .line = 3,
1005 }
1006 }
1007#endif
1008};
1009
1010
1011
1012
1013
1014
1015static void s3c24xx_serial_resetport(struct uart_port *port,
1016 struct s3c2410_uartcfg *cfg)
1017{
1018 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1019 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1020 unsigned int ucon_mask;
1021
1022 ucon_mask = info->clksel_mask;
1023 if (info->type == PORT_S3C2440)
1024 ucon_mask |= S3C2440_UCON0_DIVMASK;
1025
1026 ucon &= ucon_mask;
1027 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1028
1029
1030 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1031 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1032
1033
1034 udelay(1);
1035}
1036
1037
1038#ifdef CONFIG_CPU_FREQ
1039
1040static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1041 unsigned long val, void *data)
1042{
1043 struct s3c24xx_uart_port *port;
1044 struct uart_port *uport;
1045
1046 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1047 uport = &port->port;
1048
1049
1050
1051 if (port->pm_level != 0)
1052 return 0;
1053
1054
1055
1056
1057
1058
1059 if (IS_ERR(port->baudclk))
1060 goto exit;
1061
1062 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1063 goto exit;
1064
1065 if (val == CPUFREQ_PRECHANGE) {
1066
1067
1068
1069 } else if (val == CPUFREQ_POSTCHANGE) {
1070 struct ktermios *termios;
1071 struct tty_struct *tty;
1072
1073 if (uport->state == NULL)
1074 goto exit;
1075
1076 tty = uport->state->port.tty;
1077
1078 if (tty == NULL)
1079 goto exit;
1080
1081 termios = &tty->termios;
1082
1083 if (termios == NULL) {
1084 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1085 goto exit;
1086 }
1087
1088 s3c24xx_serial_set_termios(uport, termios, NULL);
1089 }
1090
1091 exit:
1092 return 0;
1093}
1094
1095static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1096{
1097 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1098
1099 return cpufreq_register_notifier(&port->freq_transition,
1100 CPUFREQ_TRANSITION_NOTIFIER);
1101}
1102
1103static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1104{
1105 cpufreq_unregister_notifier(&port->freq_transition,
1106 CPUFREQ_TRANSITION_NOTIFIER);
1107}
1108
1109#else
1110static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1111{
1112 return 0;
1113}
1114
1115static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1116{
1117}
1118#endif
1119
1120
1121
1122
1123
1124
1125static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1126 struct platform_device *platdev)
1127{
1128 struct uart_port *port = &ourport->port;
1129 struct s3c2410_uartcfg *cfg = ourport->cfg;
1130 struct resource *res;
1131 int ret;
1132
1133 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1134
1135 if (platdev == NULL)
1136 return -ENODEV;
1137
1138 if (port->mapbase != 0)
1139 return 0;
1140
1141
1142 port->dev = &platdev->dev;
1143
1144
1145 if (s3c24xx_serial_has_interrupt_mask(port))
1146 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1147
1148 port->uartclk = 1;
1149
1150 if (cfg->uart_flags & UPF_CONS_FLOW) {
1151 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1152 port->flags |= UPF_CONS_FLOW;
1153 }
1154
1155
1156
1157 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1158 if (res == NULL) {
1159 dev_err(port->dev, "failed to find memory resource for uart\n");
1160 return -EINVAL;
1161 }
1162
1163 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1164
1165 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1166 if (!port->membase) {
1167 dev_err(port->dev, "failed to remap controller address\n");
1168 return -EBUSY;
1169 }
1170
1171 port->mapbase = res->start;
1172 ret = platform_get_irq(platdev, 0);
1173 if (ret < 0)
1174 port->irq = 0;
1175 else {
1176 port->irq = ret;
1177 ourport->rx_irq = ret;
1178 ourport->tx_irq = ret + 1;
1179 }
1180
1181 ret = platform_get_irq(platdev, 1);
1182 if (ret > 0)
1183 ourport->tx_irq = ret;
1184
1185 ourport->clk = clk_get(&platdev->dev, "uart");
1186 if (IS_ERR(ourport->clk)) {
1187 pr_err("%s: Controller clock not found\n",
1188 dev_name(&platdev->dev));
1189 return PTR_ERR(ourport->clk);
1190 }
1191
1192 ret = clk_prepare_enable(ourport->clk);
1193 if (ret) {
1194 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1195 clk_put(ourport->clk);
1196 return ret;
1197 }
1198
1199
1200 if (s3c24xx_serial_has_interrupt_mask(port)) {
1201 wr_regl(port, S3C64XX_UINTM, 0xf);
1202 wr_regl(port, S3C64XX_UINTP, 0xf);
1203 wr_regl(port, S3C64XX_UINTSP, 0xf);
1204 }
1205
1206 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1207 port->mapbase, port->membase, port->irq,
1208 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1209
1210
1211 s3c24xx_serial_resetport(port, cfg);
1212 clk_disable_unprepare(ourport->clk);
1213 return 0;
1214}
1215
1216#ifdef CONFIG_SAMSUNG_CLOCK
1217static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1218 struct device_attribute *attr,
1219 char *buf)
1220{
1221 struct uart_port *port = s3c24xx_dev_to_port(dev);
1222 struct s3c24xx_uart_port *ourport = to_ourport(port);
1223
1224 if (IS_ERR(ourport->baudclk))
1225 return -EINVAL;
1226
1227 return snprintf(buf, PAGE_SIZE, "* %s\n",
1228 ourport->baudclk->name ?: "(null)");
1229}
1230
1231static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1232#endif
1233
1234
1235
1236static const struct of_device_id s3c24xx_uart_dt_match[];
1237static int probe_index;
1238
1239static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1240 struct platform_device *pdev)
1241{
1242#ifdef CONFIG_OF
1243 if (pdev->dev.of_node) {
1244 const struct of_device_id *match;
1245 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1246 return (struct s3c24xx_serial_drv_data *)match->data;
1247 }
1248#endif
1249 return (struct s3c24xx_serial_drv_data *)
1250 platform_get_device_id(pdev)->driver_data;
1251}
1252
1253static int s3c24xx_serial_probe(struct platform_device *pdev)
1254{
1255 struct s3c24xx_uart_port *ourport;
1256 int ret;
1257
1258 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1259
1260 ourport = &s3c24xx_serial_ports[probe_index];
1261
1262 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1263 if (!ourport->drv_data) {
1264 dev_err(&pdev->dev, "could not find driver data\n");
1265 return -ENODEV;
1266 }
1267
1268 ourport->baudclk = ERR_PTR(-EINVAL);
1269 ourport->info = ourport->drv_data->info;
1270 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1271 dev_get_platdata(&pdev->dev) :
1272 ourport->drv_data->def_cfg;
1273
1274 ourport->port.fifosize = (ourport->info->fifosize) ?
1275 ourport->info->fifosize :
1276 ourport->drv_data->fifosize[probe_index];
1277
1278 probe_index++;
1279
1280 dbg("%s: initialising port %p...\n", __func__, ourport);
1281
1282 ret = s3c24xx_serial_init_port(ourport, pdev);
1283 if (ret < 0)
1284 goto probe_err;
1285
1286 dbg("%s: adding port\n", __func__);
1287 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1288 platform_set_drvdata(pdev, &ourport->port);
1289
1290#ifdef CONFIG_SAMSUNG_CLOCK
1291 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1292 if (ret < 0)
1293 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1294#endif
1295
1296 ret = s3c24xx_serial_cpufreq_register(ourport);
1297 if (ret < 0)
1298 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1299
1300 return 0;
1301
1302 probe_err:
1303 return ret;
1304}
1305
1306static int s3c24xx_serial_remove(struct platform_device *dev)
1307{
1308 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1309
1310 if (port) {
1311 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1312#ifdef CONFIG_SAMSUNG_CLOCK
1313 device_remove_file(&dev->dev, &dev_attr_clock_source);
1314#endif
1315 uart_remove_one_port(&s3c24xx_uart_drv, port);
1316 }
1317
1318 return 0;
1319}
1320
1321
1322#ifdef CONFIG_PM_SLEEP
1323static int s3c24xx_serial_suspend(struct device *dev)
1324{
1325 struct uart_port *port = s3c24xx_dev_to_port(dev);
1326
1327 if (port)
1328 uart_suspend_port(&s3c24xx_uart_drv, port);
1329
1330 return 0;
1331}
1332
1333static int s3c24xx_serial_resume(struct device *dev)
1334{
1335 struct uart_port *port = s3c24xx_dev_to_port(dev);
1336 struct s3c24xx_uart_port *ourport = to_ourport(port);
1337
1338 if (port) {
1339 clk_prepare_enable(ourport->clk);
1340 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1341 clk_disable_unprepare(ourport->clk);
1342
1343 uart_resume_port(&s3c24xx_uart_drv, port);
1344 }
1345
1346 return 0;
1347}
1348
1349static int s3c24xx_serial_resume_noirq(struct device *dev)
1350{
1351 struct uart_port *port = s3c24xx_dev_to_port(dev);
1352
1353 if (port) {
1354
1355 if (s3c24xx_serial_has_interrupt_mask(port)) {
1356 unsigned int uintm = 0xf;
1357 if (tx_enabled(port))
1358 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1359 if (rx_enabled(port))
1360 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1361 wr_regl(port, S3C64XX_UINTM, uintm);
1362 }
1363 }
1364
1365 return 0;
1366}
1367
1368static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1369 .suspend = s3c24xx_serial_suspend,
1370 .resume = s3c24xx_serial_resume,
1371 .resume_noirq = s3c24xx_serial_resume_noirq,
1372};
1373#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1374
1375#else
1376
1377#define SERIAL_SAMSUNG_PM_OPS NULL
1378#endif
1379
1380
1381
1382#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1383
1384static struct uart_port *cons_uart;
1385
1386static int
1387s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1388{
1389 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1390 unsigned long ufstat, utrstat;
1391
1392 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1393
1394
1395 ufstat = rd_regl(port, S3C2410_UFSTAT);
1396 return (ufstat & info->tx_fifofull) ? 0 : 1;
1397 }
1398
1399
1400
1401 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1402 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1403}
1404
1405static bool
1406s3c24xx_port_configured(unsigned int ucon)
1407{
1408
1409 return (ucon & 0xf) != 0;
1410}
1411
1412#ifdef CONFIG_CONSOLE_POLL
1413
1414
1415
1416
1417
1418static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1419{
1420 struct s3c24xx_uart_port *ourport = to_ourport(port);
1421 unsigned int ufstat;
1422
1423 ufstat = rd_regl(port, S3C2410_UFSTAT);
1424 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1425 return NO_POLL_CHAR;
1426
1427 return rd_regb(port, S3C2410_URXH);
1428}
1429
1430static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1431 unsigned char c)
1432{
1433 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1434 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1435
1436
1437 if (!s3c24xx_port_configured(ucon))
1438 return;
1439
1440 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1441 cpu_relax();
1442 wr_regb(cons_uart, S3C2410_UTXH, c);
1443}
1444
1445#endif
1446
1447static void
1448s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1449{
1450 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1451 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1452
1453
1454 if (!s3c24xx_port_configured(ucon))
1455 return;
1456
1457 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1458 barrier();
1459 wr_regb(cons_uart, S3C2410_UTXH, ch);
1460}
1461
1462static void
1463s3c24xx_serial_console_write(struct console *co, const char *s,
1464 unsigned int count)
1465{
1466 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1467}
1468
1469static void __init
1470s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1471 int *parity, int *bits)
1472{
1473 struct clk *clk;
1474 unsigned int ulcon;
1475 unsigned int ucon;
1476 unsigned int ubrdiv;
1477 unsigned long rate;
1478 unsigned int clk_sel;
1479 char clk_name[MAX_CLK_NAME_LENGTH];
1480
1481 ulcon = rd_regl(port, S3C2410_ULCON);
1482 ucon = rd_regl(port, S3C2410_UCON);
1483 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1484
1485 dbg("s3c24xx_serial_get_options: port=%p\n"
1486 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1487 port, ulcon, ucon, ubrdiv);
1488
1489 if (s3c24xx_port_configured(ucon)) {
1490 switch (ulcon & S3C2410_LCON_CSMASK) {
1491 case S3C2410_LCON_CS5:
1492 *bits = 5;
1493 break;
1494 case S3C2410_LCON_CS6:
1495 *bits = 6;
1496 break;
1497 case S3C2410_LCON_CS7:
1498 *bits = 7;
1499 break;
1500 default:
1501 case S3C2410_LCON_CS8:
1502 *bits = 8;
1503 break;
1504 }
1505
1506 switch (ulcon & S3C2410_LCON_PMASK) {
1507 case S3C2410_LCON_PEVEN:
1508 *parity = 'e';
1509 break;
1510
1511 case S3C2410_LCON_PODD:
1512 *parity = 'o';
1513 break;
1514
1515 case S3C2410_LCON_PNONE:
1516 default:
1517 *parity = 'n';
1518 }
1519
1520
1521
1522 clk_sel = s3c24xx_serial_getsource(port);
1523 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1524
1525 clk = clk_get(port->dev, clk_name);
1526 if (!IS_ERR(clk))
1527 rate = clk_get_rate(clk);
1528 else
1529 rate = 1;
1530
1531 *baud = rate / (16 * (ubrdiv + 1));
1532 dbg("calculated baud %d\n", *baud);
1533 }
1534
1535}
1536
1537static int __init
1538s3c24xx_serial_console_setup(struct console *co, char *options)
1539{
1540 struct uart_port *port;
1541 int baud = 9600;
1542 int bits = 8;
1543 int parity = 'n';
1544 int flow = 'n';
1545
1546 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1547 co, co->index, options);
1548
1549
1550
1551 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1552 co->index = 0;
1553
1554 port = &s3c24xx_serial_ports[co->index].port;
1555
1556
1557
1558 if (port->mapbase == 0x0)
1559 return -ENODEV;
1560
1561 cons_uart = port;
1562
1563 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1564
1565
1566
1567
1568
1569
1570 if (options)
1571 uart_parse_options(options, &baud, &parity, &bits, &flow);
1572 else
1573 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1574
1575 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1576
1577 return uart_set_options(port, co, baud, parity, bits, flow);
1578}
1579
1580static struct console s3c24xx_serial_console = {
1581 .name = S3C24XX_SERIAL_NAME,
1582 .device = uart_console_device,
1583 .flags = CON_PRINTBUFFER,
1584 .index = -1,
1585 .write = s3c24xx_serial_console_write,
1586 .setup = s3c24xx_serial_console_setup,
1587 .data = &s3c24xx_uart_drv,
1588};
1589#endif
1590
1591#ifdef CONFIG_CPU_S3C2410
1592static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1593 .info = &(struct s3c24xx_uart_info) {
1594 .name = "Samsung S3C2410 UART",
1595 .type = PORT_S3C2410,
1596 .fifosize = 16,
1597 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1598 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1599 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1600 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1601 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1602 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1603 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1604 .num_clks = 2,
1605 .clksel_mask = S3C2410_UCON_CLKMASK,
1606 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1607 },
1608 .def_cfg = &(struct s3c2410_uartcfg) {
1609 .ucon = S3C2410_UCON_DEFAULT,
1610 .ufcon = S3C2410_UFCON_DEFAULT,
1611 },
1612};
1613#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1614#else
1615#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1616#endif
1617
1618#ifdef CONFIG_CPU_S3C2412
1619static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1620 .info = &(struct s3c24xx_uart_info) {
1621 .name = "Samsung S3C2412 UART",
1622 .type = PORT_S3C2412,
1623 .fifosize = 64,
1624 .has_divslot = 1,
1625 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1626 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1627 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1628 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1629 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1630 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1631 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1632 .num_clks = 4,
1633 .clksel_mask = S3C2412_UCON_CLKMASK,
1634 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1635 },
1636 .def_cfg = &(struct s3c2410_uartcfg) {
1637 .ucon = S3C2410_UCON_DEFAULT,
1638 .ufcon = S3C2410_UFCON_DEFAULT,
1639 },
1640};
1641#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1642#else
1643#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1644#endif
1645
1646#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1647 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1648static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1649 .info = &(struct s3c24xx_uart_info) {
1650 .name = "Samsung S3C2440 UART",
1651 .type = PORT_S3C2440,
1652 .fifosize = 64,
1653 .has_divslot = 1,
1654 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1655 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1656 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1657 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1658 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1659 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1660 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1661 .num_clks = 4,
1662 .clksel_mask = S3C2412_UCON_CLKMASK,
1663 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1664 },
1665 .def_cfg = &(struct s3c2410_uartcfg) {
1666 .ucon = S3C2410_UCON_DEFAULT,
1667 .ufcon = S3C2410_UFCON_DEFAULT,
1668 },
1669};
1670#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1671#else
1672#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1673#endif
1674
1675#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1676 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1677 defined(CONFIG_CPU_S5PC100)
1678static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1679 .info = &(struct s3c24xx_uart_info) {
1680 .name = "Samsung S3C6400 UART",
1681 .type = PORT_S3C6400,
1682 .fifosize = 64,
1683 .has_divslot = 1,
1684 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1685 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1686 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1687 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1688 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1689 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1690 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1691 .num_clks = 4,
1692 .clksel_mask = S3C6400_UCON_CLKMASK,
1693 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1694 },
1695 .def_cfg = &(struct s3c2410_uartcfg) {
1696 .ucon = S3C2410_UCON_DEFAULT,
1697 .ufcon = S3C2410_UFCON_DEFAULT,
1698 },
1699};
1700#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1701#else
1702#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1703#endif
1704
1705#ifdef CONFIG_CPU_S5PV210
1706static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1707 .info = &(struct s3c24xx_uart_info) {
1708 .name = "Samsung S5PV210 UART",
1709 .type = PORT_S3C6400,
1710 .has_divslot = 1,
1711 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1712 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1713 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1714 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1715 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1716 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1717 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1718 .num_clks = 2,
1719 .clksel_mask = S5PV210_UCON_CLKMASK,
1720 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1721 },
1722 .def_cfg = &(struct s3c2410_uartcfg) {
1723 .ucon = S5PV210_UCON_DEFAULT,
1724 .ufcon = S5PV210_UFCON_DEFAULT,
1725 },
1726 .fifosize = { 256, 64, 16, 16 },
1727};
1728#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1729#else
1730#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1731#endif
1732
1733#if defined(CONFIG_ARCH_EXYNOS)
1734static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1735 .info = &(struct s3c24xx_uart_info) {
1736 .name = "Samsung Exynos4 UART",
1737 .type = PORT_S3C6400,
1738 .has_divslot = 1,
1739 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1740 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1741 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1742 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1743 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1744 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1745 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1746 .num_clks = 1,
1747 .clksel_mask = 0,
1748 .clksel_shift = 0,
1749 },
1750 .def_cfg = &(struct s3c2410_uartcfg) {
1751 .ucon = S5PV210_UCON_DEFAULT,
1752 .ufcon = S5PV210_UFCON_DEFAULT,
1753 .has_fracval = 1,
1754 },
1755 .fifosize = { 256, 64, 16, 16 },
1756};
1757#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1758#else
1759#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1760#endif
1761
1762static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1763 {
1764 .name = "s3c2410-uart",
1765 .driver_data = S3C2410_SERIAL_DRV_DATA,
1766 }, {
1767 .name = "s3c2412-uart",
1768 .driver_data = S3C2412_SERIAL_DRV_DATA,
1769 }, {
1770 .name = "s3c2440-uart",
1771 .driver_data = S3C2440_SERIAL_DRV_DATA,
1772 }, {
1773 .name = "s3c6400-uart",
1774 .driver_data = S3C6400_SERIAL_DRV_DATA,
1775 }, {
1776 .name = "s5pv210-uart",
1777 .driver_data = S5PV210_SERIAL_DRV_DATA,
1778 }, {
1779 .name = "exynos4210-uart",
1780 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1781 },
1782 { },
1783};
1784MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1785
1786#ifdef CONFIG_OF
1787static const struct of_device_id s3c24xx_uart_dt_match[] = {
1788 { .compatible = "samsung,s3c2410-uart",
1789 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1790 { .compatible = "samsung,s3c2412-uart",
1791 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1792 { .compatible = "samsung,s3c2440-uart",
1793 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1794 { .compatible = "samsung,s3c6400-uart",
1795 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1796 { .compatible = "samsung,s5pv210-uart",
1797 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1798 { .compatible = "samsung,exynos4210-uart",
1799 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1800 {},
1801};
1802MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1803#endif
1804
1805static struct platform_driver samsung_serial_driver = {
1806 .probe = s3c24xx_serial_probe,
1807 .remove = s3c24xx_serial_remove,
1808 .id_table = s3c24xx_serial_driver_ids,
1809 .driver = {
1810 .name = "samsung-uart",
1811 .owner = THIS_MODULE,
1812 .pm = SERIAL_SAMSUNG_PM_OPS,
1813 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1814 },
1815};
1816
1817
1818
1819static int __init s3c24xx_serial_modinit(void)
1820{
1821 int ret;
1822
1823 ret = uart_register_driver(&s3c24xx_uart_drv);
1824 if (ret < 0) {
1825 pr_err("Failed to register Samsung UART driver\n");
1826 return ret;
1827 }
1828
1829 ret = platform_driver_register(&samsung_serial_driver);
1830 if (ret < 0) {
1831 pr_err("Failed to register platform driver\n");
1832 uart_unregister_driver(&s3c24xx_uart_drv);
1833 }
1834
1835 return ret;
1836}
1837
1838static void __exit s3c24xx_serial_modexit(void)
1839{
1840 platform_driver_unregister(&samsung_serial_driver);
1841 uart_unregister_driver(&s3c24xx_uart_drv);
1842}
1843
1844module_init(s3c24xx_serial_modinit);
1845module_exit(s3c24xx_serial_modexit);
1846
1847MODULE_ALIAS("platform:samsung-uart");
1848MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1849MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1850MODULE_LICENSE("GPL v2");
1851
