1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54#if defined(__i386__)
55# define BREAKPOINT() asm(" int $3");
56#else
57# define BREAKPOINT() { }
58#endif
59
60#define MAX_ISA_DEVICES 10
61#define MAX_PCI_DEVICES 10
62#define MAX_TOTAL_DEVICES 20
63
64#include <linux/module.h>
65#include <linux/errno.h>
66#include <linux/signal.h>
67#include <linux/sched.h>
68#include <linux/timer.h>
69#include <linux/interrupt.h>
70#include <linux/pci.h>
71#include <linux/tty.h>
72#include <linux/tty_flip.h>
73#include <linux/serial.h>
74#include <linux/major.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
78#include <linux/ioport.h>
79#include <linux/mm.h>
80#include <linux/seq_file.h>
81#include <linux/slab.h>
82#include <linux/delay.h>
83#include <linux/netdevice.h>
84#include <linux/vmalloc.h>
85#include <linux/init.h>
86#include <linux/ioctl.h>
87#include <linux/synclink.h>
88
89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/dma.h>
92#include <linux/bitops.h>
93#include <asm/types.h>
94#include <linux/termios.h>
95#include <linux/workqueue.h>
96#include <linux/hdlc.h>
97#include <linux/dma-mapping.h>
98
99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100#define SYNCLINK_GENERIC_HDLC 1
101#else
102#define SYNCLINK_GENERIC_HDLC 0
103#endif
104
105#define GET_USER(error,value,addr) error = get_user(value,addr)
106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107#define PUT_USER(error,value,addr) error = put_user(value,addr)
108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110#include <asm/uaccess.h>
111
112#define RCLRVALUE 0xffff
113
114static MGSL_PARAMS default_params = {
115 MGSL_MODE_HDLC,
116 0,
117 HDLC_FLAG_UNDERRUN_ABORT15,
118 HDLC_ENCODING_NRZI_SPACE,
119 0,
120 0xff,
121 HDLC_CRC_16_CCITT,
122 HDLC_PREAMBLE_LENGTH_8BITS,
123 HDLC_PREAMBLE_PATTERN_NONE,
124 9600,
125 8,
126 1,
127 ASYNC_PARITY_NONE
128};
129
130#define SHARED_MEM_ADDRESS_SIZE 0x40000
131#define BUFFERLISTSIZE 4096
132#define DMABUFFERSIZE 4096
133#define MAXRXFRAMES 7
134
135typedef struct _DMABUFFERENTRY
136{
137 u32 phys_addr;
138 volatile u16 count;
139 volatile u16 status;
140 volatile u16 rcc;
141 u16 reserved;
142 u32 link;
143 char *virt_addr;
144 u32 phys_entry;
145 dma_addr_t dma_addr;
146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148
149
150#define BH_RECEIVE 1
151#define BH_TRANSMIT 2
152#define BH_STATUS 4
153
154#define IO_PIN_SHUTDOWN_LIMIT 100
155
156struct _input_signal_events {
157 int ri_up;
158 int ri_down;
159 int dsr_up;
160 int dsr_down;
161 int dcd_up;
162 int dcd_down;
163 int cts_up;
164 int cts_down;
165};
166
167
168#define MAX_TX_HOLDING_BUFFERS 5
169struct tx_holding_buffer {
170 int buffer_size;
171 unsigned char * buffer;
172};
173
174
175
176
177
178
179struct mgsl_struct {
180 int magic;
181 struct tty_port port;
182 int line;
183 int hw_version;
184
185 struct mgsl_icount icount;
186
187 int timeout;
188 int x_char;
189 u16 read_status_mask;
190 u16 ignore_status_mask;
191 unsigned char *xmit_buf;
192 int xmit_head;
193 int xmit_tail;
194 int xmit_cnt;
195
196 wait_queue_head_t status_event_wait_q;
197 wait_queue_head_t event_wait_q;
198 struct timer_list tx_timer;
199 struct mgsl_struct *next_device;
200
201 spinlock_t irq_spinlock;
202 struct work_struct task;
203
204 u32 EventMask;
205 u32 RecordedEvents;
206
207 u32 max_frame_size;
208
209 u32 pending_bh;
210
211 bool bh_running;
212 int isr_overflow;
213 bool bh_requested;
214
215 int dcd_chkcount;
216 int cts_chkcount;
217 int dsr_chkcount;
218 int ri_chkcount;
219
220 char *buffer_list;
221 u32 buffer_list_phys;
222 dma_addr_t buffer_list_dma_addr;
223
224 unsigned int rx_buffer_count;
225 DMABUFFERENTRY *rx_buffer_list;
226 unsigned int current_rx_buffer;
227
228 int num_tx_dma_buffers;
229 int tx_dma_buffers_used;
230 unsigned int tx_buffer_count;
231 DMABUFFERENTRY *tx_buffer_list;
232 int start_tx_dma_buffer;
233 int current_tx_buffer;
234
235 unsigned char *intermediate_rxbuffer;
236
237 int num_tx_holding_buffers;
238 int get_tx_holding_index;
239 int put_tx_holding_index;
240 int tx_holding_count;
241 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
243 bool rx_enabled;
244 bool rx_overflow;
245 bool rx_rcc_underrun;
246
247 bool tx_enabled;
248 bool tx_active;
249 u32 idle_mode;
250
251 u16 cmr_value;
252 u16 tcsr_value;
253
254 char device_name[25];
255
256 unsigned int bus_type;
257 unsigned char bus;
258 unsigned char function;
259
260 unsigned int io_base;
261 unsigned int io_addr_size;
262 bool io_addr_requested;
263
264 unsigned int irq_level;
265 unsigned long irq_flags;
266 bool irq_requested;
267
268 unsigned int dma_level;
269 bool dma_requested;
270
271 u16 mbre_bit;
272 u16 loopback_bits;
273 u16 usc_idle_mode;
274
275 MGSL_PARAMS params;
276
277 unsigned char serial_signals;
278
279 bool irq_occurred;
280 unsigned int init_error;
281 int fDiagnosticsmode;
282
283 u32 last_mem_alloc;
284 unsigned char* memory_base;
285 u32 phys_memory_base;
286 bool shared_mem_requested;
287
288 unsigned char* lcr_base;
289 u32 phys_lcr_base;
290 u32 lcr_offset;
291 bool lcr_mem_requested;
292
293 u32 misc_ctrl_value;
294 char *flag_buf;
295 bool drop_rts_on_tx_done;
296
297 bool loopmode_insert_requested;
298 bool loopmode_send_done_requested;
299
300 struct _input_signal_events input_signal_events;
301
302
303 int netcount;
304 spinlock_t netlock;
305
306#if SYNCLINK_GENERIC_HDLC
307 struct net_device *netdev;
308#endif
309};
310
311#define MGSL_MAGIC 0x5401
312
313
314
315
316#ifndef SERIAL_XMIT_SIZE
317#define SERIAL_XMIT_SIZE 4096
318#endif
319
320
321
322
323
324
325
326#define DCPIN 2
327#define SDPIN 4
328
329#define DCAR 0
330#define CCAR SDPIN
331#define DATAREG DCPIN + SDPIN
332#define MSBONLY 0x41
333#define LSBONLY 0x40
334
335
336
337
338
339
340#define CMR 0x02
341#define CCSR 0x04
342#define CCR 0x06
343#define PSR 0x08
344#define PCR 0x0a
345#define TMDR 0x0c
346#define TMCR 0x0e
347#define CMCR 0x10
348#define HCR 0x12
349#define IVR 0x14
350#define IOCR 0x16
351#define ICR 0x18
352#define DCCR 0x1a
353#define MISR 0x1c
354#define SICR 0x1e
355#define RDR 0x20
356#define RMR 0x22
357#define RCSR 0x24
358#define RICR 0x26
359#define RSR 0x28
360#define RCLR 0x2a
361#define RCCR 0x2c
362#define TC0R 0x2e
363#define TDR 0x30
364#define TMR 0x32
365#define TCSR 0x34
366#define TICR 0x36
367#define TSR 0x38
368#define TCLR 0x3a
369#define TCCR 0x3c
370#define TC1R 0x3e
371
372
373
374
375
376
377#define DCR 0x06
378#define DACR 0x08
379#define BDCR 0x12
380#define DIVR 0x14
381#define DICR 0x18
382#define CDIR 0x1a
383#define SDIR 0x1c
384
385#define TDMR 0x02
386#define TDIAR 0x1e
387#define TBCR 0x2a
388#define TARL 0x2c
389#define TARU 0x2e
390#define NTBCR 0x3a
391#define NTARL 0x3c
392#define NTARU 0x3e
393
394#define RDMR 0x82
395#define RDIAR 0x9e
396#define RBCR 0xaa
397#define RARL 0xac
398#define RARU 0xae
399#define NRBCR 0xba
400#define NRARL 0xbc
401#define NRARU 0xbe
402
403
404
405
406
407
408#define MODEMSTATUS_DTR 0x80
409#define MODEMSTATUS_DSR 0x40
410#define MODEMSTATUS_RTS 0x20
411#define MODEMSTATUS_CTS 0x10
412#define MODEMSTATUS_RI 0x04
413#define MODEMSTATUS_DCD 0x01
414
415
416
417
418
419
420#define RTCmd_Null 0x0000
421#define RTCmd_ResetHighestIus 0x1000
422#define RTCmd_TriggerChannelLoadDma 0x2000
423#define RTCmd_TriggerRxDma 0x2800
424#define RTCmd_TriggerTxDma 0x3000
425#define RTCmd_TriggerRxAndTxDma 0x3800
426#define RTCmd_PurgeRxFifo 0x4800
427#define RTCmd_PurgeTxFifo 0x5000
428#define RTCmd_PurgeRxAndTxFifo 0x5800
429#define RTCmd_LoadRcc 0x6800
430#define RTCmd_LoadTcc 0x7000
431#define RTCmd_LoadRccAndTcc 0x7800
432#define RTCmd_LoadTC0 0x8800
433#define RTCmd_LoadTC1 0x9000
434#define RTCmd_LoadTC0AndTC1 0x9800
435#define RTCmd_SerialDataLSBFirst 0xa000
436#define RTCmd_SerialDataMSBFirst 0xa800
437#define RTCmd_SelectBigEndian 0xb000
438#define RTCmd_SelectLittleEndian 0xb800
439
440
441
442
443
444
445#define DmaCmd_Null 0x0000
446#define DmaCmd_ResetTxChannel 0x1000
447#define DmaCmd_ResetRxChannel 0x1200
448#define DmaCmd_StartTxChannel 0x2000
449#define DmaCmd_StartRxChannel 0x2200
450#define DmaCmd_ContinueTxChannel 0x3000
451#define DmaCmd_ContinueRxChannel 0x3200
452#define DmaCmd_PauseTxChannel 0x4000
453#define DmaCmd_PauseRxChannel 0x4200
454#define DmaCmd_AbortTxChannel 0x5000
455#define DmaCmd_AbortRxChannel 0x5200
456#define DmaCmd_InitTxChannel 0x7000
457#define DmaCmd_InitRxChannel 0x7200
458#define DmaCmd_ResetHighestDmaIus 0x8000
459#define DmaCmd_ResetAllChannels 0x9000
460#define DmaCmd_StartAllChannels 0xa000
461#define DmaCmd_ContinueAllChannels 0xb000
462#define DmaCmd_PauseAllChannels 0xc000
463#define DmaCmd_AbortAllChannels 0xd000
464#define DmaCmd_InitAllChannels 0xf000
465
466#define TCmd_Null 0x0000
467#define TCmd_ClearTxCRC 0x2000
468#define TCmd_SelectTicrTtsaData 0x4000
469#define TCmd_SelectTicrTxFifostatus 0x5000
470#define TCmd_SelectTicrIntLevel 0x6000
471#define TCmd_SelectTicrdma_level 0x7000
472#define TCmd_SendFrame 0x8000
473#define TCmd_SendAbort 0x9000
474#define TCmd_EnableDleInsertion 0xc000
475#define TCmd_DisableDleInsertion 0xd000
476#define TCmd_ClearEofEom 0xe000
477#define TCmd_SetEofEom 0xf000
478
479#define RCmd_Null 0x0000
480#define RCmd_ClearRxCRC 0x2000
481#define RCmd_EnterHuntmode 0x3000
482#define RCmd_SelectRicrRtsaData 0x4000
483#define RCmd_SelectRicrRxFifostatus 0x5000
484#define RCmd_SelectRicrIntLevel 0x6000
485#define RCmd_SelectRicrdma_level 0x7000
486
487
488
489
490
491#define RECEIVE_STATUS BIT5
492#define RECEIVE_DATA BIT4
493#define TRANSMIT_STATUS BIT3
494#define TRANSMIT_DATA BIT2
495#define IO_PIN BIT1
496#define MISC BIT0
497
498
499
500
501
502
503#define RXSTATUS_SHORT_FRAME BIT8
504#define RXSTATUS_CODE_VIOLATION BIT8
505#define RXSTATUS_EXITED_HUNT BIT7
506#define RXSTATUS_IDLE_RECEIVED BIT6
507#define RXSTATUS_BREAK_RECEIVED BIT5
508#define RXSTATUS_ABORT_RECEIVED BIT5
509#define RXSTATUS_RXBOUND BIT4
510#define RXSTATUS_CRC_ERROR BIT3
511#define RXSTATUS_FRAMING_ERROR BIT3
512#define RXSTATUS_ABORT BIT2
513#define RXSTATUS_PARITY_ERROR BIT2
514#define RXSTATUS_OVERRUN BIT1
515#define RXSTATUS_DATA_AVAILABLE BIT0
516#define RXSTATUS_ALL 0x01f6
517#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
518
519
520
521
522
523#define IDLEMODE_FLAGS 0x0000
524#define IDLEMODE_ALT_ONE_ZERO 0x0100
525#define IDLEMODE_ZERO 0x0200
526#define IDLEMODE_ONE 0x0300
527#define IDLEMODE_ALT_MARK_SPACE 0x0500
528#define IDLEMODE_SPACE 0x0600
529#define IDLEMODE_MARK 0x0700
530#define IDLEMODE_MASK 0x0700
531
532
533
534
535#define IUSC_SL1660 0x4d44
536#define IUSC_PRE_SL1660 0x4553
537
538
539
540
541
542#define TCSR_PRESERVE 0x0F00
543
544#define TCSR_UNDERWAIT BIT11
545#define TXSTATUS_PREAMBLE_SENT BIT7
546#define TXSTATUS_IDLE_SENT BIT6
547#define TXSTATUS_ABORT_SENT BIT5
548#define TXSTATUS_EOF_SENT BIT4
549#define TXSTATUS_EOM_SENT BIT4
550#define TXSTATUS_CRC_SENT BIT3
551#define TXSTATUS_ALL_SENT BIT2
552#define TXSTATUS_UNDERRUN BIT1
553#define TXSTATUS_FIFO_EMPTY BIT0
554#define TXSTATUS_ALL 0x00fa
555#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
556
557
558#define MISCSTATUS_RXC_LATCHED BIT15
559#define MISCSTATUS_RXC BIT14
560#define MISCSTATUS_TXC_LATCHED BIT13
561#define MISCSTATUS_TXC BIT12
562#define MISCSTATUS_RI_LATCHED BIT11
563#define MISCSTATUS_RI BIT10
564#define MISCSTATUS_DSR_LATCHED BIT9
565#define MISCSTATUS_DSR BIT8
566#define MISCSTATUS_DCD_LATCHED BIT7
567#define MISCSTATUS_DCD BIT6
568#define MISCSTATUS_CTS_LATCHED BIT5
569#define MISCSTATUS_CTS BIT4
570#define MISCSTATUS_RCC_UNDERRUN BIT3
571#define MISCSTATUS_DPLL_NO_SYNC BIT2
572#define MISCSTATUS_BRG1_ZERO BIT1
573#define MISCSTATUS_BRG0_ZERO BIT0
574
575#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
577
578#define SICR_RXC_ACTIVE BIT15
579#define SICR_RXC_INACTIVE BIT14
580#define SICR_RXC (BIT15|BIT14)
581#define SICR_TXC_ACTIVE BIT13
582#define SICR_TXC_INACTIVE BIT12
583#define SICR_TXC (BIT13|BIT12)
584#define SICR_RI_ACTIVE BIT11
585#define SICR_RI_INACTIVE BIT10
586#define SICR_RI (BIT11|BIT10)
587#define SICR_DSR_ACTIVE BIT9
588#define SICR_DSR_INACTIVE BIT8
589#define SICR_DSR (BIT9|BIT8)
590#define SICR_DCD_ACTIVE BIT7
591#define SICR_DCD_INACTIVE BIT6
592#define SICR_DCD (BIT7|BIT6)
593#define SICR_CTS_ACTIVE BIT5
594#define SICR_CTS_INACTIVE BIT4
595#define SICR_CTS (BIT5|BIT4)
596#define SICR_RCC_UNDERFLOW BIT3
597#define SICR_DPLL_NO_SYNC BIT2
598#define SICR_BRG1_ZERO BIT1
599#define SICR_BRG0_ZERO BIT0
600
601void usc_DisableMasterIrqBit( struct mgsl_struct *info );
602void usc_EnableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
604void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
606
607#define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
609
610#define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
612
613#define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
615
616#define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
618
619#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
620
621
622
623
624
625
626#define TXSTATUS_PREAMBLE_SENT BIT7
627#define TXSTATUS_IDLE_SENT BIT6
628#define TXSTATUS_ABORT_SENT BIT5
629#define TXSTATUS_EOF BIT4
630#define TXSTATUS_CRC_SENT BIT3
631#define TXSTATUS_ALL_SENT BIT2
632#define TXSTATUS_UNDERRUN BIT1
633#define TXSTATUS_FIFO_EMPTY BIT0
634
635#define DICR_MASTER BIT15
636#define DICR_TRANSMIT BIT0
637#define DICR_RECEIVE BIT1
638
639#define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
641
642#define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
644
645#define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
647
648#define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
650
651
652
653
654
655#define DISABLE_UNCONDITIONAL 0
656#define DISABLE_END_OF_FRAME 1
657#define ENABLE_UNCONDITIONAL 2
658#define ENABLE_AUTO_CTS 3
659#define ENABLE_AUTO_DCD 3
660#define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662#define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
664
665static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
666static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
667static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
668
669static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
670static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
671static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
672void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
674
675#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
677
678#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
679
680static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
681static void usc_start_receiver( struct mgsl_struct *info );
682static void usc_stop_receiver( struct mgsl_struct *info );
683
684static void usc_start_transmitter( struct mgsl_struct *info );
685static void usc_stop_transmitter( struct mgsl_struct *info );
686static void usc_set_txidle( struct mgsl_struct *info );
687static void usc_load_txfifo( struct mgsl_struct *info );
688
689static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
690static void usc_enable_loopback( struct mgsl_struct *info, int enable );
691
692static void usc_get_serial_signals( struct mgsl_struct *info );
693static void usc_set_serial_signals( struct mgsl_struct *info );
694
695static void usc_reset( struct mgsl_struct *info );
696
697static void usc_set_sync_mode( struct mgsl_struct *info );
698static void usc_set_sdlc_mode( struct mgsl_struct *info );
699static void usc_set_async_mode( struct mgsl_struct *info );
700static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
701
702static void usc_loopback_frame( struct mgsl_struct *info );
703
704static void mgsl_tx_timeout(unsigned long context);
705
706
707static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
708static void usc_loopmode_insert_request( struct mgsl_struct * info );
709static int usc_loopmode_active( struct mgsl_struct * info);
710static void usc_loopmode_send_done( struct mgsl_struct * info );
711
712static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
713
714#if SYNCLINK_GENERIC_HDLC
715#define dev_to_port(D) (dev_to_hdlc(D)->priv)
716static void hdlcdev_tx_done(struct mgsl_struct *info);
717static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
718static int hdlcdev_init(struct mgsl_struct *info);
719static void hdlcdev_exit(struct mgsl_struct *info);
720#endif
721
722
723
724
725
726
727#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
728(0x00400020 + \
729((WrHold) << 30) + \
730((WrDly) << 28) + \
731((RdDly) << 26) + \
732((Nwdd) << 20) + \
733((Nwad) << 15) + \
734((Nxda) << 13) + \
735((Nrdd) << 11) + \
736((Nrad) << 6) )
737
738static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
739
740
741
742
743static bool mgsl_register_test( struct mgsl_struct *info );
744static bool mgsl_irq_test( struct mgsl_struct *info );
745static bool mgsl_dma_test( struct mgsl_struct *info );
746static bool mgsl_memory_test( struct mgsl_struct *info );
747static int mgsl_adapter_test( struct mgsl_struct *info );
748
749
750
751
752static int mgsl_claim_resources(struct mgsl_struct *info);
753static void mgsl_release_resources(struct mgsl_struct *info);
754static void mgsl_add_device(struct mgsl_struct *info);
755static struct mgsl_struct* mgsl_allocate_device(void);
756
757
758
759
760static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
761static bool mgsl_get_rx_frame( struct mgsl_struct *info );
762static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
763static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
764static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
765static int num_free_tx_dma_buffers(struct mgsl_struct *info);
766static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
767static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
768
769
770
771
772static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
773static void mgsl_free_dma_buffers(struct mgsl_struct *info);
774static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
775static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
777static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
778static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
779static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
781static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
782static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
783static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
784
785
786
787
788static void mgsl_bh_handler(struct work_struct *work);
789static void mgsl_bh_receive(struct mgsl_struct *info);
790static void mgsl_bh_transmit(struct mgsl_struct *info);
791static void mgsl_bh_status(struct mgsl_struct *info);
792
793
794
795
796static void mgsl_isr_null( struct mgsl_struct *info );
797static void mgsl_isr_transmit_data( struct mgsl_struct *info );
798static void mgsl_isr_receive_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_status( struct mgsl_struct *info );
800static void mgsl_isr_transmit_status( struct mgsl_struct *info );
801static void mgsl_isr_io_pin( struct mgsl_struct *info );
802static void mgsl_isr_misc( struct mgsl_struct *info );
803static void mgsl_isr_receive_dma( struct mgsl_struct *info );
804static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
805
806typedef void (*isr_dispatch_func)(struct mgsl_struct *);
807
808static isr_dispatch_func UscIsrTable[7] =
809{
810 mgsl_isr_null,
811 mgsl_isr_misc,
812 mgsl_isr_io_pin,
813 mgsl_isr_transmit_data,
814 mgsl_isr_transmit_status,
815 mgsl_isr_receive_data,
816 mgsl_isr_receive_status
817};
818
819
820
821
822static int tiocmget(struct tty_struct *tty);
823static int tiocmset(struct tty_struct *tty,
824 unsigned int set, unsigned int clear);
825static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
826 __user *user_icount);
827static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
828static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
829static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
830static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
831static int mgsl_txenable(struct mgsl_struct * info, int enable);
832static int mgsl_txabort(struct mgsl_struct * info);
833static int mgsl_rxenable(struct mgsl_struct * info, int enable);
834static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
835static int mgsl_loopmode_send_done( struct mgsl_struct * info );
836
837
838static bool pci_registered;
839
840
841
842
843static struct mgsl_struct *mgsl_device_list;
844static int mgsl_device_count;
845
846
847
848
849
850
851static bool break_on_load;
852
853
854
855
856
857static int ttymajor;
858
859
860
861
862static int io[MAX_ISA_DEVICES];
863static int irq[MAX_ISA_DEVICES];
864static int dma[MAX_ISA_DEVICES];
865static int debug_level;
866static int maxframe[MAX_TOTAL_DEVICES];
867static int txdmabufs[MAX_TOTAL_DEVICES];
868static int txholdbufs[MAX_TOTAL_DEVICES];
869
870module_param(break_on_load, bool, 0);
871module_param(ttymajor, int, 0);
872module_param_array(io, int, NULL, 0);
873module_param_array(irq, int, NULL, 0);
874module_param_array(dma, int, NULL, 0);
875module_param(debug_level, int, 0);
876module_param_array(maxframe, int, NULL, 0);
877module_param_array(txdmabufs, int, NULL, 0);
878module_param_array(txholdbufs, int, NULL, 0);
879
880static char *driver_name = "SyncLink serial driver";
881static char *driver_version = "$Revision: 4.38 $";
882
883static int synclink_init_one (struct pci_dev *dev,
884 const struct pci_device_id *ent);
885static void synclink_remove_one (struct pci_dev *dev);
886
887static struct pci_device_id synclink_pci_tbl[] = {
888 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
889 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
890 { 0, },
891};
892MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
893
894MODULE_LICENSE("GPL");
895
896static struct pci_driver synclink_pci_driver = {
897 .name = "synclink",
898 .id_table = synclink_pci_tbl,
899 .probe = synclink_init_one,
900 .remove = synclink_remove_one,
901};
902
903static struct tty_driver *serial_driver;
904
905
906#define WAKEUP_CHARS 256
907
908
909static void mgsl_change_params(struct mgsl_struct *info);
910static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
911
912
913
914
915
916
917
918static void* mgsl_get_text_ptr(void)
919{
920 return mgsl_get_text_ptr;
921}
922
923static inline int mgsl_paranoia_check(struct mgsl_struct *info,
924 char *name, const char *routine)
925{
926#ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic =
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo =
930 "Warning: null mgsl_struct for (%s) in %s\n";
931
932 if (!info) {
933 printk(badinfo, name, routine);
934 return 1;
935 }
936 if (info->magic != MGSL_MAGIC) {
937 printk(badmagic, name, routine);
938 return 1;
939 }
940#else
941 if (!info)
942 return 1;
943#endif
944 return 0;
945}
946
947
948
949
950
951
952
953
954
955
956static void ldisc_receive_buf(struct tty_struct *tty,
957 const __u8 *data, char *flags, int count)
958{
959 struct tty_ldisc *ld;
960 if (!tty)
961 return;
962 ld = tty_ldisc_ref(tty);
963 if (ld) {
964 if (ld->ops->receive_buf)
965 ld->ops->receive_buf(tty, data, flags, count);
966 tty_ldisc_deref(ld);
967 }
968}
969
970
971
972
973
974
975static void mgsl_stop(struct tty_struct *tty)
976{
977 struct mgsl_struct *info = tty->driver_data;
978 unsigned long flags;
979
980 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
981 return;
982
983 if ( debug_level >= DEBUG_LEVEL_INFO )
984 printk("mgsl_stop(%s)\n",info->device_name);
985
986 spin_lock_irqsave(&info->irq_spinlock,flags);
987 if (info->tx_enabled)
988 usc_stop_transmitter(info);
989 spin_unlock_irqrestore(&info->irq_spinlock,flags);
990
991}
992
993
994
995
996
997
998static void mgsl_start(struct tty_struct *tty)
999{
1000 struct mgsl_struct *info = tty->driver_data;
1001 unsigned long flags;
1002
1003 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004 return;
1005
1006 if ( debug_level >= DEBUG_LEVEL_INFO )
1007 printk("mgsl_start(%s)\n",info->device_name);
1008
1009 spin_lock_irqsave(&info->irq_spinlock,flags);
1010 if (!info->tx_enabled)
1011 usc_start_transmitter(info);
1012 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013
1014}
1015
1016
1017
1018
1019
1020
1021
1022
1023static int mgsl_bh_action(struct mgsl_struct *info)
1024{
1025 unsigned long flags;
1026 int rc = 0;
1027
1028 spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030 if (info->pending_bh & BH_RECEIVE) {
1031 info->pending_bh &= ~BH_RECEIVE;
1032 rc = BH_RECEIVE;
1033 } else if (info->pending_bh & BH_TRANSMIT) {
1034 info->pending_bh &= ~BH_TRANSMIT;
1035 rc = BH_TRANSMIT;
1036 } else if (info->pending_bh & BH_STATUS) {
1037 info->pending_bh &= ~BH_STATUS;
1038 rc = BH_STATUS;
1039 }
1040
1041 if (!rc) {
1042
1043 info->bh_running = false;
1044 info->bh_requested = false;
1045 }
1046
1047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048
1049 return rc;
1050}
1051
1052
1053
1054
1055static void mgsl_bh_handler(struct work_struct *work)
1056{
1057 struct mgsl_struct *info =
1058 container_of(work, struct mgsl_struct, task);
1059 int action;
1060
1061 if ( debug_level >= DEBUG_LEVEL_BH )
1062 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063 __FILE__,__LINE__,info->device_name);
1064
1065 info->bh_running = true;
1066
1067 while((action = mgsl_bh_action(info)) != 0) {
1068
1069
1070 if ( debug_level >= DEBUG_LEVEL_BH )
1071 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072 __FILE__,__LINE__,action);
1073
1074 switch (action) {
1075
1076 case BH_RECEIVE:
1077 mgsl_bh_receive(info);
1078 break;
1079 case BH_TRANSMIT:
1080 mgsl_bh_transmit(info);
1081 break;
1082 case BH_STATUS:
1083 mgsl_bh_status(info);
1084 break;
1085 default:
1086
1087 printk("Unknown work item ID=%08X!\n", action);
1088 break;
1089 }
1090 }
1091
1092 if ( debug_level >= DEBUG_LEVEL_BH )
1093 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094 __FILE__,__LINE__,info->device_name);
1095}
1096
1097static void mgsl_bh_receive(struct mgsl_struct *info)
1098{
1099 bool (*get_rx_frame)(struct mgsl_struct *info) =
1100 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1101
1102 if ( debug_level >= DEBUG_LEVEL_BH )
1103 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104 __FILE__,__LINE__,info->device_name);
1105
1106 do
1107 {
1108 if (info->rx_rcc_underrun) {
1109 unsigned long flags;
1110 spin_lock_irqsave(&info->irq_spinlock,flags);
1111 usc_start_receiver(info);
1112 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1113 return;
1114 }
1115 } while(get_rx_frame(info));
1116}
1117
1118static void mgsl_bh_transmit(struct mgsl_struct *info)
1119{
1120 struct tty_struct *tty = info->port.tty;
1121 unsigned long flags;
1122
1123 if ( debug_level >= DEBUG_LEVEL_BH )
1124 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125 __FILE__,__LINE__,info->device_name);
1126
1127 if (tty)
1128 tty_wakeup(tty);
1129
1130
1131
1132
1133 spin_lock_irqsave(&info->irq_spinlock,flags);
1134 if ( !info->tx_active && info->loopmode_send_done_requested )
1135 usc_loopmode_send_done( info );
1136 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1137}
1138
1139static void mgsl_bh_status(struct mgsl_struct *info)
1140{
1141 if ( debug_level >= DEBUG_LEVEL_BH )
1142 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143 __FILE__,__LINE__,info->device_name);
1144
1145 info->ri_chkcount = 0;
1146 info->dsr_chkcount = 0;
1147 info->dcd_chkcount = 0;
1148 info->cts_chkcount = 0;
1149}
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160static void mgsl_isr_receive_status( struct mgsl_struct *info )
1161{
1162 u16 status = usc_InReg( info, RCSR );
1163
1164 if ( debug_level >= DEBUG_LEVEL_ISR )
1165 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166 __FILE__,__LINE__,status);
1167
1168 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1169 info->loopmode_insert_requested &&
1170 usc_loopmode_active(info) )
1171 {
1172 ++info->icount.rxabort;
1173 info->loopmode_insert_requested = false;
1174
1175
1176 info->cmr_value &= ~BIT13;
1177 usc_OutReg(info, CMR, info->cmr_value);
1178
1179
1180 usc_OutReg(info, RICR,
1181 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1182 }
1183
1184 if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
1185 if (status & RXSTATUS_EXITED_HUNT)
1186 info->icount.exithunt++;
1187 if (status & RXSTATUS_IDLE_RECEIVED)
1188 info->icount.rxidle++;
1189 wake_up_interruptible(&info->event_wait_q);
1190 }
1191
1192 if (status & RXSTATUS_OVERRUN){
1193 info->icount.rxover++;
1194 usc_process_rxoverrun_sync( info );
1195 }
1196
1197 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1198 usc_UnlatchRxstatusBits( info, status );
1199
1200}
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1213{
1214 u16 status = usc_InReg( info, TCSR );
1215
1216 if ( debug_level >= DEBUG_LEVEL_ISR )
1217 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218 __FILE__,__LINE__,status);
1219
1220 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1221 usc_UnlatchTxstatusBits( info, status );
1222
1223 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1224 {
1225
1226
1227
1228
1229
1230 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1231 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1232 }
1233
1234 if ( status & TXSTATUS_EOF_SENT )
1235 info->icount.txok++;
1236 else if ( status & TXSTATUS_UNDERRUN )
1237 info->icount.txunder++;
1238 else if ( status & TXSTATUS_ABORT_SENT )
1239 info->icount.txabort++;
1240 else
1241 info->icount.txunder++;
1242
1243 info->tx_active = false;
1244 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1245 del_timer(&info->tx_timer);
1246
1247 if ( info->drop_rts_on_tx_done ) {
1248 usc_get_serial_signals( info );
1249 if ( info->serial_signals & SerialSignal_RTS ) {
1250 info->serial_signals &= ~SerialSignal_RTS;
1251 usc_set_serial_signals( info );
1252 }
1253 info->drop_rts_on_tx_done = false;
1254 }
1255
1256#if SYNCLINK_GENERIC_HDLC
1257 if (info->netcount)
1258 hdlcdev_tx_done(info);
1259 else
1260#endif
1261 {
1262 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1263 usc_stop_transmitter(info);
1264 return;
1265 }
1266 info->pending_bh |= BH_TRANSMIT;
1267 }
1268
1269}
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279static void mgsl_isr_io_pin( struct mgsl_struct *info )
1280{
1281 struct mgsl_icount *icount;
1282 u16 status = usc_InReg( info, MISR );
1283
1284 if ( debug_level >= DEBUG_LEVEL_ISR )
1285 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286 __FILE__,__LINE__,status);
1287
1288 usc_ClearIrqPendingBits( info, IO_PIN );
1289 usc_UnlatchIostatusBits( info, status );
1290
1291 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1292 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1293 icount = &info->icount;
1294
1295 if (status & MISCSTATUS_RI_LATCHED) {
1296 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1297 usc_DisablestatusIrqs(info,SICR_RI);
1298 icount->rng++;
1299 if ( status & MISCSTATUS_RI )
1300 info->input_signal_events.ri_up++;
1301 else
1302 info->input_signal_events.ri_down++;
1303 }
1304 if (status & MISCSTATUS_DSR_LATCHED) {
1305 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1306 usc_DisablestatusIrqs(info,SICR_DSR);
1307 icount->dsr++;
1308 if ( status & MISCSTATUS_DSR )
1309 info->input_signal_events.dsr_up++;
1310 else
1311 info->input_signal_events.dsr_down++;
1312 }
1313 if (status & MISCSTATUS_DCD_LATCHED) {
1314 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1315 usc_DisablestatusIrqs(info,SICR_DCD);
1316 icount->dcd++;
1317 if (status & MISCSTATUS_DCD) {
1318 info->input_signal_events.dcd_up++;
1319 } else
1320 info->input_signal_events.dcd_down++;
1321#if SYNCLINK_GENERIC_HDLC
1322 if (info->netcount) {
1323 if (status & MISCSTATUS_DCD)
1324 netif_carrier_on(info->netdev);
1325 else
1326 netif_carrier_off(info->netdev);
1327 }
1328#endif
1329 }
1330 if (status & MISCSTATUS_CTS_LATCHED)
1331 {
1332 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1333 usc_DisablestatusIrqs(info,SICR_CTS);
1334 icount->cts++;
1335 if ( status & MISCSTATUS_CTS )
1336 info->input_signal_events.cts_up++;
1337 else
1338 info->input_signal_events.cts_down++;
1339 }
1340 wake_up_interruptible(&info->status_event_wait_q);
1341 wake_up_interruptible(&info->event_wait_q);
1342
1343 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1344 (status & MISCSTATUS_DCD_LATCHED) ) {
1345 if ( debug_level >= DEBUG_LEVEL_ISR )
1346 printk("%s CD now %s...", info->device_name,
1347 (status & MISCSTATUS_DCD) ? "on" : "off");
1348 if (status & MISCSTATUS_DCD)
1349 wake_up_interruptible(&info->port.open_wait);
1350 else {
1351 if ( debug_level >= DEBUG_LEVEL_ISR )
1352 printk("doing serial hangup...");
1353 if (info->port.tty)
1354 tty_hangup(info->port.tty);
1355 }
1356 }
1357
1358 if (tty_port_cts_enabled(&info->port) &&
1359 (status & MISCSTATUS_CTS_LATCHED) ) {
1360 if (info->port.tty->hw_stopped) {
1361 if (status & MISCSTATUS_CTS) {
1362 if ( debug_level >= DEBUG_LEVEL_ISR )
1363 printk("CTS tx start...");
1364 if (info->port.tty)
1365 info->port.tty->hw_stopped = 0;
1366 usc_start_transmitter(info);
1367 info->pending_bh |= BH_TRANSMIT;
1368 return;
1369 }
1370 } else {
1371 if (!(status & MISCSTATUS_CTS)) {
1372 if ( debug_level >= DEBUG_LEVEL_ISR )
1373 printk("CTS tx stop...");
1374 if (info->port.tty)
1375 info->port.tty->hw_stopped = 1;
1376 usc_stop_transmitter(info);
1377 }
1378 }
1379 }
1380 }
1381
1382 info->pending_bh |= BH_STATUS;
1383
1384
1385 if ( status & MISCSTATUS_TXC_LATCHED ){
1386 usc_OutReg( info, SICR,
1387 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1388 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1389 info->irq_occurred = true;
1390 }
1391
1392}
1393
1394
1395
1396
1397
1398
1399
1400
1401static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1402{
1403 if ( debug_level >= DEBUG_LEVEL_ISR )
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__,__LINE__,info->xmit_cnt);
1406
1407 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1408
1409 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1410 usc_stop_transmitter(info);
1411 return;
1412 }
1413
1414 if ( info->xmit_cnt )
1415 usc_load_txfifo( info );
1416 else
1417 info->tx_active = false;
1418
1419 if (info->xmit_cnt < WAKEUP_CHARS)
1420 info->pending_bh |= BH_TRANSMIT;
1421
1422}
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433static void mgsl_isr_receive_data( struct mgsl_struct *info )
1434{
1435 int Fifocount;
1436 u16 status;
1437 int work = 0;
1438 unsigned char DataByte;
1439 struct mgsl_icount *icount = &info->icount;
1440
1441 if ( debug_level >= DEBUG_LEVEL_ISR )
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1443 __FILE__,__LINE__);
1444
1445 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1446
1447
1448 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1449
1450
1451
1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1453
1454
1455
1456 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1457 int flag;
1458
1459
1460 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1461 info->io_base + CCAR );
1462 DataByte = inb( info->io_base + CCAR );
1463
1464
1465 status = usc_InReg(info, RCSR);
1466 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1467 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
1468 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1469
1470 icount->rx++;
1471
1472 flag = 0;
1473 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1474 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
1475 printk("rxerr=%04X\n",status);
1476
1477 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1478 status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
1479 icount->brk++;
1480 } else if (status & RXSTATUS_PARITY_ERROR)
1481 icount->parity++;
1482 else if (status & RXSTATUS_FRAMING_ERROR)
1483 icount->frame++;
1484 else if (status & RXSTATUS_OVERRUN) {
1485
1486
1487 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1488 icount->overrun++;
1489 }
1490
1491
1492 if (status & info->ignore_status_mask)
1493 continue;
1494
1495 status &= info->read_status_mask;
1496
1497 if (status & RXSTATUS_BREAK_RECEIVED) {
1498 flag = TTY_BREAK;
1499 if (info->port.flags & ASYNC_SAK)
1500 do_SAK(info->port.tty);
1501 } else if (status & RXSTATUS_PARITY_ERROR)
1502 flag = TTY_PARITY;
1503 else if (status & RXSTATUS_FRAMING_ERROR)
1504 flag = TTY_FRAME;
1505 }
1506 tty_insert_flip_char(&info->port, DataByte, flag);
1507 if (status & RXSTATUS_OVERRUN) {
1508
1509
1510
1511
1512 work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
1513 }
1514 }
1515
1516 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__,__LINE__,icount->rx,icount->brk,
1519 icount->parity,icount->frame,icount->overrun);
1520 }
1521
1522 if(work)
1523 tty_flip_buffer_push(&info->port);
1524}
1525
1526
1527
1528
1529
1530
1531
1532
1533static void mgsl_isr_misc( struct mgsl_struct *info )
1534{
1535 u16 status = usc_InReg( info, MISR );
1536
1537 if ( debug_level >= DEBUG_LEVEL_ISR )
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__,__LINE__,status);
1540
1541 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1542 (info->params.mode == MGSL_MODE_HDLC)) {
1543
1544
1545 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1546 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1547 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1548 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1549 usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
1550
1551
1552 info->pending_bh |= BH_RECEIVE;
1553 info->rx_rcc_underrun = true;
1554 }
1555
1556 usc_ClearIrqPendingBits( info, MISC );
1557 usc_UnlatchMiscstatusBits( info, status );
1558
1559}
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569static void mgsl_isr_null( struct mgsl_struct *info )
1570{
1571
1572}
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1594{
1595 u16 status;
1596
1597
1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
1599
1600
1601
1602 status = usc_InDmaReg( info, RDMR );
1603
1604 if ( debug_level >= DEBUG_LEVEL_ISR )
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__,__LINE__,info->device_name,status);
1607
1608 info->pending_bh |= BH_RECEIVE;
1609
1610 if ( status & BIT3 ) {
1611 info->rx_overflow = true;
1612 info->icount.buf_overrun++;
1613 }
1614
1615}
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1638{
1639 u16 status;
1640
1641
1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
1643
1644
1645
1646
1647 status = usc_InDmaReg( info, TDMR );
1648
1649 if ( debug_level >= DEBUG_LEVEL_ISR )
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__,__LINE__,info->device_name,status);
1652
1653 if ( status & BIT2 ) {
1654 --info->tx_dma_buffers_used;
1655
1656
1657
1658
1659 if ( load_next_tx_holding_buffer(info) ) {
1660
1661
1662
1663 info->pending_bh |= BH_TRANSMIT;
1664 }
1665 }
1666
1667}
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1681{
1682 struct mgsl_struct *info = dev_id;
1683 u16 UscVector;
1684 u16 DmaVector;
1685
1686 if ( debug_level >= DEBUG_LEVEL_ISR )
1687 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__, __LINE__, info->irq_level);
1689
1690 spin_lock(&info->irq_spinlock);
1691
1692 for(;;) {
1693
1694 UscVector = usc_InReg(info, IVR) >> 9;
1695 DmaVector = usc_InDmaReg(info, DIVR);
1696
1697 if ( debug_level >= DEBUG_LEVEL_ISR )
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1700
1701 if ( !UscVector && !DmaVector )
1702 break;
1703
1704
1705 if ( UscVector )
1706 (*UscIsrTable[UscVector])(info);
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1708 mgsl_isr_transmit_dma(info);
1709 else
1710 mgsl_isr_receive_dma(info);
1711
1712 if ( info->isr_overflow ) {
1713 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__, __LINE__, info->device_name, info->irq_level);
1715 usc_DisableMasterIrqBit(info);
1716 usc_DisableDmaInterrupts(info,DICR_MASTER);
1717 break;
1718 }
1719 }
1720
1721
1722
1723
1724
1725 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1726 if ( debug_level >= DEBUG_LEVEL_ISR )
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__,__LINE__,info->device_name);
1729 schedule_work(&info->task);
1730 info->bh_requested = true;
1731 }
1732
1733 spin_unlock(&info->irq_spinlock);
1734
1735 if ( debug_level >= DEBUG_LEVEL_ISR )
1736 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__, __LINE__, info->irq_level);
1738
1739 return IRQ_HANDLED;
1740}
1741
1742
1743
1744
1745
1746
1747
1748
1749static int startup(struct mgsl_struct * info)
1750{
1751 int retval = 0;
1752
1753 if ( debug_level >= DEBUG_LEVEL_INFO )
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1755
1756 if (info->port.flags & ASYNC_INITIALIZED)
1757 return 0;
1758
1759 if (!info->xmit_buf) {
1760
1761 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1762 if (!info->xmit_buf) {
1763 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__,__LINE__,info->device_name);
1765 return -ENOMEM;
1766 }
1767 }
1768
1769 info->pending_bh = 0;
1770
1771 memset(&info->icount, 0, sizeof(info->icount));
1772
1773 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1774
1775
1776 retval = mgsl_claim_resources(info);
1777
1778
1779 if ( !retval )
1780 retval = mgsl_adapter_test(info);
1781
1782 if ( retval ) {
1783 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1784 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1785 mgsl_release_resources(info);
1786 return retval;
1787 }
1788
1789
1790 mgsl_change_params(info);
1791
1792 if (info->port.tty)
1793 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1794
1795 info->port.flags |= ASYNC_INITIALIZED;
1796
1797 return 0;
1798
1799}
1800
1801
1802
1803
1804
1805
1806
1807
1808static void shutdown(struct mgsl_struct * info)
1809{
1810 unsigned long flags;
1811
1812 if (!(info->port.flags & ASYNC_INITIALIZED))
1813 return;
1814
1815 if (debug_level >= DEBUG_LEVEL_INFO)
1816 printk("%s(%d):mgsl_shutdown(%s)\n",
1817 __FILE__,__LINE__, info->device_name );
1818
1819
1820
1821 wake_up_interruptible(&info->status_event_wait_q);
1822 wake_up_interruptible(&info->event_wait_q);
1823
1824 del_timer_sync(&info->tx_timer);
1825
1826 if (info->xmit_buf) {
1827 free_page((unsigned long) info->xmit_buf);
1828 info->xmit_buf = NULL;
1829 }
1830
1831 spin_lock_irqsave(&info->irq_spinlock,flags);
1832 usc_DisableMasterIrqBit(info);
1833 usc_stop_receiver(info);
1834 usc_stop_transmitter(info);
1835 usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
1836 TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
1837 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1838
1839
1840
1841
1842 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1843
1844
1845
1846
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1848
1849 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1850 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1851 usc_set_serial_signals(info);
1852 }
1853
1854 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1855
1856 mgsl_release_resources(info);
1857
1858 if (info->port.tty)
1859 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1860
1861 info->port.flags &= ~ASYNC_INITIALIZED;
1862
1863}
1864
1865static void mgsl_program_hw(struct mgsl_struct *info)
1866{
1867 unsigned long flags;
1868
1869 spin_lock_irqsave(&info->irq_spinlock,flags);
1870
1871 usc_stop_receiver(info);
1872 usc_stop_transmitter(info);
1873 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1874
1875 if (info->params.mode == MGSL_MODE_HDLC ||
1876 info->params.mode == MGSL_MODE_RAW ||
1877 info->netcount)
1878 usc_set_sync_mode(info);
1879 else
1880 usc_set_async_mode(info);
1881
1882 usc_set_serial_signals(info);
1883
1884 info->dcd_chkcount = 0;
1885 info->cts_chkcount = 0;
1886 info->ri_chkcount = 0;
1887 info->dsr_chkcount = 0;
1888
1889 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1890 usc_EnableInterrupts(info, IO_PIN);
1891 usc_get_serial_signals(info);
1892
1893 if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1894 usc_start_receiver(info);
1895
1896 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1897}
1898
1899
1900
1901static void mgsl_change_params(struct mgsl_struct *info)
1902{
1903 unsigned cflag;
1904 int bits_per_char;
1905
1906 if (!info->port.tty)
1907 return;
1908
1909 if (debug_level >= DEBUG_LEVEL_INFO)
1910 printk("%s(%d):mgsl_change_params(%s)\n",
1911 __FILE__,__LINE__, info->device_name );
1912
1913 cflag = info->port.tty->termios.c_cflag;
1914
1915
1916
1917 if (cflag & CBAUD)
1918 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1919 else
1920 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1921
1922
1923
1924 switch (cflag & CSIZE) {
1925 case CS5: info->params.data_bits = 5; break;
1926 case CS6: info->params.data_bits = 6; break;
1927 case CS7: info->params.data_bits = 7; break;
1928 case CS8: info->params.data_bits = 8; break;
1929
1930 default: info->params.data_bits = 7; break;
1931 }
1932
1933 if (cflag & CSTOPB)
1934 info->params.stop_bits = 2;
1935 else
1936 info->params.stop_bits = 1;
1937
1938 info->params.parity = ASYNC_PARITY_NONE;
1939 if (cflag & PARENB) {
1940 if (cflag & PARODD)
1941 info->params.parity = ASYNC_PARITY_ODD;
1942 else
1943 info->params.parity = ASYNC_PARITY_EVEN;
1944#ifdef CMSPAR
1945 if (cflag & CMSPAR)
1946 info->params.parity = ASYNC_PARITY_SPACE;
1947#endif
1948 }
1949
1950
1951
1952
1953 bits_per_char = info->params.data_bits +
1954 info->params.stop_bits + 1;
1955
1956
1957
1958
1959
1960 if (info->params.data_rate <= 460800)
1961 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1962
1963 if ( info->params.data_rate ) {
1964 info->timeout = (32*HZ*bits_per_char) /
1965 info->params.data_rate;
1966 }
1967 info->timeout += HZ/50;
1968
1969 if (cflag & CRTSCTS)
1970 info->port.flags |= ASYNC_CTS_FLOW;
1971 else
1972 info->port.flags &= ~ASYNC_CTS_FLOW;
1973
1974 if (cflag & CLOCAL)
1975 info->port.flags &= ~ASYNC_CHECK_CD;
1976 else
1977 info->port.flags |= ASYNC_CHECK_CD;
1978
1979
1980
1981 info->read_status_mask = RXSTATUS_OVERRUN;
1982 if (I_INPCK(info->port.tty))
1983 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1984 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1985 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1986
1987 if (I_IGNPAR(info->port.tty))
1988 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1989 if (I_IGNBRK(info->port.tty)) {
1990 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1991
1992
1993
1994 if (I_IGNPAR(info->port.tty))
1995 info->ignore_status_mask |= RXSTATUS_OVERRUN;
1996 }
1997
1998 mgsl_program_hw(info);
1999
2000}
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2012{
2013 struct mgsl_struct *info = tty->driver_data;
2014 unsigned long flags;
2015 int ret = 0;
2016
2017 if (debug_level >= DEBUG_LEVEL_INFO) {
2018 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2019 __FILE__, __LINE__, ch, info->device_name);
2020 }
2021
2022 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2023 return 0;
2024
2025 if (!info->xmit_buf)
2026 return 0;
2027
2028 spin_lock_irqsave(&info->irq_spinlock, flags);
2029
2030 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2031 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2032 info->xmit_buf[info->xmit_head++] = ch;
2033 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2034 info->xmit_cnt++;
2035 ret = 1;
2036 }
2037 }
2038 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2039 return ret;
2040
2041}
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051static void mgsl_flush_chars(struct tty_struct *tty)
2052{
2053 struct mgsl_struct *info = tty->driver_data;
2054 unsigned long flags;
2055
2056 if ( debug_level >= DEBUG_LEVEL_INFO )
2057 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2058 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2059
2060 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2061 return;
2062
2063 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2064 !info->xmit_buf)
2065 return;
2066
2067 if ( debug_level >= DEBUG_LEVEL_INFO )
2068 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2069 __FILE__,__LINE__,info->device_name );
2070
2071 spin_lock_irqsave(&info->irq_spinlock,flags);
2072
2073 if (!info->tx_active) {
2074 if ( (info->params.mode == MGSL_MODE_HDLC ||
2075 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2076
2077
2078
2079 mgsl_load_tx_dma_buffer(info,
2080 info->xmit_buf,info->xmit_cnt);
2081 }
2082 usc_start_transmitter(info);
2083 }
2084
2085 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2086
2087}
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101static int mgsl_write(struct tty_struct * tty,
2102 const unsigned char *buf, int count)
2103{
2104 int c, ret = 0;
2105 struct mgsl_struct *info = tty->driver_data;
2106 unsigned long flags;
2107
2108 if ( debug_level >= DEBUG_LEVEL_INFO )
2109 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2110 __FILE__,__LINE__,info->device_name,count);
2111
2112 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2113 goto cleanup;
2114
2115 if (!info->xmit_buf)
2116 goto cleanup;
2117
2118 if ( info->params.mode == MGSL_MODE_HDLC ||
2119 info->params.mode == MGSL_MODE_RAW ) {
2120
2121 if (info->tx_active) {
2122
2123 if ( info->params.mode == MGSL_MODE_HDLC ) {
2124 ret = 0;
2125 goto cleanup;
2126 }
2127
2128
2129
2130
2131
2132 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2133
2134 ret = 0;
2135 goto cleanup;
2136 }
2137
2138
2139 ret = count;
2140 save_tx_buffer_request(info,buf,count);
2141
2142
2143
2144
2145 spin_lock_irqsave(&info->irq_spinlock,flags);
2146 load_next_tx_holding_buffer(info);
2147 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2148 goto cleanup;
2149 }
2150
2151
2152
2153
2154
2155 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2156 !usc_loopmode_active(info) )
2157 {
2158 ret = 0;
2159 goto cleanup;
2160 }
2161
2162 if ( info->xmit_cnt ) {
2163
2164
2165 ret = 0;
2166
2167
2168
2169 mgsl_load_tx_dma_buffer(info,
2170 info->xmit_buf,info->xmit_cnt);
2171 if ( debug_level >= DEBUG_LEVEL_INFO )
2172 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2173 __FILE__,__LINE__,info->device_name);
2174 } else {
2175 if ( debug_level >= DEBUG_LEVEL_INFO )
2176 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2177 __FILE__,__LINE__,info->device_name);
2178 ret = count;
2179 info->xmit_cnt = count;
2180 mgsl_load_tx_dma_buffer(info,buf,count);
2181 }
2182 } else {
2183 while (1) {
2184 spin_lock_irqsave(&info->irq_spinlock,flags);
2185 c = min_t(int, count,
2186 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2187 SERIAL_XMIT_SIZE - info->xmit_head));
2188 if (c <= 0) {
2189 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2190 break;
2191 }
2192 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2193 info->xmit_head = ((info->xmit_head + c) &
2194 (SERIAL_XMIT_SIZE-1));
2195 info->xmit_cnt += c;
2196 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2197 buf += c;
2198 count -= c;
2199 ret += c;
2200 }
2201 }
2202
2203 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2204 spin_lock_irqsave(&info->irq_spinlock,flags);
2205 if (!info->tx_active)
2206 usc_start_transmitter(info);
2207 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2208 }
2209cleanup:
2210 if ( debug_level >= DEBUG_LEVEL_INFO )
2211 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2212 __FILE__,__LINE__,info->device_name,ret);
2213
2214 return ret;
2215
2216}
2217
2218
2219
2220
2221
2222
2223
2224
2225static int mgsl_write_room(struct tty_struct *tty)
2226{
2227 struct mgsl_struct *info = tty->driver_data;
2228 int ret;
2229
2230 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2231 return 0;
2232 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2233 if (ret < 0)
2234 ret = 0;
2235
2236 if (debug_level >= DEBUG_LEVEL_INFO)
2237 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2238 __FILE__,__LINE__, info->device_name,ret );
2239
2240 if ( info->params.mode == MGSL_MODE_HDLC ||
2241 info->params.mode == MGSL_MODE_RAW ) {
2242
2243 if ( info->tx_active )
2244 return 0;
2245 else
2246 return HDLC_MAX_FRAME_SIZE;
2247 }
2248
2249 return ret;
2250
2251}
2252
2253
2254
2255
2256
2257
2258
2259
2260static int mgsl_chars_in_buffer(struct tty_struct *tty)
2261{
2262 struct mgsl_struct *info = tty->driver_data;
2263
2264 if (debug_level >= DEBUG_LEVEL_INFO)
2265 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2266 __FILE__,__LINE__, info->device_name );
2267
2268 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2269 return 0;
2270
2271 if (debug_level >= DEBUG_LEVEL_INFO)
2272 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2273 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2274
2275 if ( info->params.mode == MGSL_MODE_HDLC ||
2276 info->params.mode == MGSL_MODE_RAW ) {
2277
2278 if ( info->tx_active )
2279 return info->max_frame_size;
2280 else
2281 return 0;
2282 }
2283
2284 return info->xmit_cnt;
2285}
2286
2287
2288
2289
2290
2291
2292
2293
2294static void mgsl_flush_buffer(struct tty_struct *tty)
2295{
2296 struct mgsl_struct *info = tty->driver_data;
2297 unsigned long flags;
2298
2299 if (debug_level >= DEBUG_LEVEL_INFO)
2300 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2301 __FILE__,__LINE__, info->device_name );
2302
2303 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2304 return;
2305
2306 spin_lock_irqsave(&info->irq_spinlock,flags);
2307 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2308 del_timer(&info->tx_timer);
2309 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2310
2311 tty_wakeup(tty);
2312}
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2323{
2324 struct mgsl_struct *info = tty->driver_data;
2325 unsigned long flags;
2326
2327 if (debug_level >= DEBUG_LEVEL_INFO)
2328 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2329 __FILE__,__LINE__, info->device_name, ch );
2330
2331 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2332 return;
2333
2334 info->x_char = ch;
2335 if (ch) {
2336
2337 spin_lock_irqsave(&info->irq_spinlock,flags);
2338 if (!info->tx_enabled)
2339 usc_start_transmitter(info);
2340 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2341 }
2342}
2343
2344
2345
2346
2347
2348
2349
2350
2351static void mgsl_throttle(struct tty_struct * tty)
2352{
2353 struct mgsl_struct *info = tty->driver_data;
2354 unsigned long flags;
2355
2356 if (debug_level >= DEBUG_LEVEL_INFO)
2357 printk("%s(%d):mgsl_throttle(%s) entry\n",
2358 __FILE__,__LINE__, info->device_name );
2359
2360 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2361 return;
2362
2363 if (I_IXOFF(tty))
2364 mgsl_send_xchar(tty, STOP_CHAR(tty));
2365
2366 if (tty->termios.c_cflag & CRTSCTS) {
2367 spin_lock_irqsave(&info->irq_spinlock,flags);
2368 info->serial_signals &= ~SerialSignal_RTS;
2369 usc_set_serial_signals(info);
2370 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2371 }
2372}
2373
2374
2375
2376
2377
2378
2379
2380
2381static void mgsl_unthrottle(struct tty_struct * tty)
2382{
2383 struct mgsl_struct *info = tty->driver_data;
2384 unsigned long flags;
2385
2386 if (debug_level >= DEBUG_LEVEL_INFO)
2387 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2388 __FILE__,__LINE__, info->device_name );
2389
2390 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2391 return;
2392
2393 if (I_IXOFF(tty)) {
2394 if (info->x_char)
2395 info->x_char = 0;
2396 else
2397 mgsl_send_xchar(tty, START_CHAR(tty));
2398 }
2399
2400 if (tty->termios.c_cflag & CRTSCTS) {
2401 spin_lock_irqsave(&info->irq_spinlock,flags);
2402 info->serial_signals |= SerialSignal_RTS;
2403 usc_set_serial_signals(info);
2404 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2405 }
2406
2407}
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2419{
2420 int err;
2421
2422 if (debug_level >= DEBUG_LEVEL_INFO)
2423 printk("%s(%d):mgsl_get_params(%s)\n",
2424 __FILE__,__LINE__, info->device_name);
2425
2426 if (!user_icount) {
2427 memset(&info->icount, 0, sizeof(info->icount));
2428 } else {
2429 mutex_lock(&info->port.mutex);
2430 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2431 mutex_unlock(&info->port.mutex);
2432 if (err)
2433 return -EFAULT;
2434 }
2435
2436 return 0;
2437
2438}
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2450{
2451 int err;
2452 if (debug_level >= DEBUG_LEVEL_INFO)
2453 printk("%s(%d):mgsl_get_params(%s)\n",
2454 __FILE__,__LINE__, info->device_name);
2455
2456 mutex_lock(&info->port.mutex);
2457 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2458 mutex_unlock(&info->port.mutex);
2459 if (err) {
2460 if ( debug_level >= DEBUG_LEVEL_INFO )
2461 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2462 __FILE__,__LINE__,info->device_name);
2463 return -EFAULT;
2464 }
2465
2466 return 0;
2467
2468}
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2482{
2483 unsigned long flags;
2484 MGSL_PARAMS tmp_params;
2485 int err;
2486
2487 if (debug_level >= DEBUG_LEVEL_INFO)
2488 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2489 info->device_name );
2490 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2491 if (err) {
2492 if ( debug_level >= DEBUG_LEVEL_INFO )
2493 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2494 __FILE__,__LINE__,info->device_name);
2495 return -EFAULT;
2496 }
2497
2498 mutex_lock(&info->port.mutex);
2499 spin_lock_irqsave(&info->irq_spinlock,flags);
2500 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2501 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2502
2503 mgsl_change_params(info);
2504 mutex_unlock(&info->port.mutex);
2505
2506 return 0;
2507
2508}
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2520{
2521 int err;
2522
2523 if (debug_level >= DEBUG_LEVEL_INFO)
2524 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2525 __FILE__,__LINE__, info->device_name, info->idle_mode);
2526
2527 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2528 if (err) {
2529 if ( debug_level >= DEBUG_LEVEL_INFO )
2530 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2531 __FILE__,__LINE__,info->device_name);
2532 return -EFAULT;
2533 }
2534
2535 return 0;
2536
2537}
2538
2539
2540
2541
2542
2543
2544
2545
2546static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2547{
2548 unsigned long flags;
2549
2550 if (debug_level >= DEBUG_LEVEL_INFO)
2551 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2552 info->device_name, idle_mode );
2553
2554 spin_lock_irqsave(&info->irq_spinlock,flags);
2555 info->idle_mode = idle_mode;
2556 usc_set_txidle( info );
2557 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2558 return 0;
2559
2560}
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573static int mgsl_txenable(struct mgsl_struct * info, int enable)
2574{
2575 unsigned long flags;
2576
2577 if (debug_level >= DEBUG_LEVEL_INFO)
2578 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2579 info->device_name, enable);
2580
2581 spin_lock_irqsave(&info->irq_spinlock,flags);
2582 if ( enable ) {
2583 if ( !info->tx_enabled ) {
2584
2585 usc_start_transmitter(info);
2586
2587
2588
2589
2590
2591
2592
2593 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2594 usc_loopmode_insert_request( info );
2595 }
2596 } else {
2597 if ( info->tx_enabled )
2598 usc_stop_transmitter(info);
2599 }
2600 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2601 return 0;
2602
2603}
2604
2605
2606
2607
2608
2609
2610static int mgsl_txabort(struct mgsl_struct * info)
2611{
2612 unsigned long flags;
2613
2614 if (debug_level >= DEBUG_LEVEL_INFO)
2615 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2616 info->device_name);
2617
2618 spin_lock_irqsave(&info->irq_spinlock,flags);
2619 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2620 {
2621 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2622 usc_loopmode_cancel_transmit( info );
2623 else
2624 usc_TCmd(info,TCmd_SendAbort);
2625 }
2626 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2627 return 0;
2628
2629}
2630
2631
2632
2633
2634
2635
2636
2637static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2638{
2639 unsigned long flags;
2640
2641 if (debug_level >= DEBUG_LEVEL_INFO)
2642 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2643 info->device_name, enable);
2644
2645 spin_lock_irqsave(&info->irq_spinlock,flags);
2646 if ( enable ) {
2647 if ( !info->rx_enabled )
2648 usc_start_receiver(info);
2649 } else {
2650 if ( info->rx_enabled )
2651 usc_stop_receiver(info);
2652 }
2653 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2654 return 0;
2655
2656}
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2667{
2668 unsigned long flags;
2669 int s;
2670 int rc=0;
2671 struct mgsl_icount cprev, cnow;
2672 int events;
2673 int mask;
2674 struct _input_signal_events oldsigs, newsigs;
2675 DECLARE_WAITQUEUE(wait, current);
2676
2677 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2678 if (rc) {
2679 return -EFAULT;
2680 }
2681
2682 if (debug_level >= DEBUG_LEVEL_INFO)
2683 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2684 info->device_name, mask);
2685
2686 spin_lock_irqsave(&info->irq_spinlock,flags);
2687
2688
2689 usc_get_serial_signals(info);
2690 s = info->serial_signals;
2691 events = mask &
2692 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2693 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2694 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2695 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2696 if (events) {
2697 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2698 goto exit;
2699 }
2700
2701
2702 cprev = info->icount;
2703 oldsigs = info->input_signal_events;
2704
2705
2706 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2707 u16 oldreg = usc_InReg(info,RICR);
2708 u16 newreg = oldreg +
2709 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2710 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2711 if (oldreg != newreg)
2712 usc_OutReg(info, RICR, newreg);
2713 }
2714
2715 set_current_state(TASK_INTERRUPTIBLE);
2716 add_wait_queue(&info->event_wait_q, &wait);
2717
2718 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2719
2720
2721 for(;;) {
2722 schedule();
2723 if (signal_pending(current)) {
2724 rc = -ERESTARTSYS;
2725 break;
2726 }
2727
2728
2729 spin_lock_irqsave(&info->irq_spinlock,flags);
2730 cnow = info->icount;
2731 newsigs = info->input_signal_events;
2732 set_current_state(TASK_INTERRUPTIBLE);
2733 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2734
2735
2736 if (newsigs.dsr_up == oldsigs.dsr_up &&
2737 newsigs.dsr_down == oldsigs.dsr_down &&
2738 newsigs.dcd_up == oldsigs.dcd_up &&
2739 newsigs.dcd_down == oldsigs.dcd_down &&
2740 newsigs.cts_up == oldsigs.cts_up &&
2741 newsigs.cts_down == oldsigs.cts_down &&
2742 newsigs.ri_up == oldsigs.ri_up &&
2743 newsigs.ri_down == oldsigs.ri_down &&
2744 cnow.exithunt == cprev.exithunt &&
2745 cnow.rxidle == cprev.rxidle) {
2746 rc = -EIO;
2747 break;
2748 }
2749
2750 events = mask &
2751 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2752 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2753 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2754 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2755 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2756 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2757 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2758 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2759 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2760 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2761 if (events)
2762 break;
2763
2764 cprev = cnow;
2765 oldsigs = newsigs;
2766 }
2767
2768 remove_wait_queue(&info->event_wait_q, &wait);
2769 set_current_state(TASK_RUNNING);
2770
2771 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2772 spin_lock_irqsave(&info->irq_spinlock,flags);
2773 if (!waitqueue_active(&info->event_wait_q)) {
2774
2775 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2776 ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
2777 }
2778 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2779 }
2780exit:
2781 if ( rc == 0 )
2782 PUT_USER(rc, events, mask_ptr);
2783
2784 return rc;
2785
2786}
2787
2788static int modem_input_wait(struct mgsl_struct *info,int arg)
2789{
2790 unsigned long flags;
2791 int rc;
2792 struct mgsl_icount cprev, cnow;
2793 DECLARE_WAITQUEUE(wait, current);
2794
2795
2796 spin_lock_irqsave(&info->irq_spinlock,flags);
2797 cprev = info->icount;
2798 add_wait_queue(&info->status_event_wait_q, &wait);
2799 set_current_state(TASK_INTERRUPTIBLE);
2800 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2801
2802 for(;;) {
2803 schedule();
2804 if (signal_pending(current)) {
2805 rc = -ERESTARTSYS;
2806 break;
2807 }
2808
2809
2810 spin_lock_irqsave(&info->irq_spinlock,flags);
2811 cnow = info->icount;
2812 set_current_state(TASK_INTERRUPTIBLE);
2813 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2814
2815
2816 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2817 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2818 rc = -EIO;
2819 break;
2820 }
2821
2822
2823 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2824 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2825 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2826 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2827 rc = 0;
2828 break;
2829 }
2830
2831 cprev = cnow;
2832 }
2833 remove_wait_queue(&info->status_event_wait_q, &wait);
2834 set_current_state(TASK_RUNNING);
2835 return rc;
2836}
2837
2838
2839
2840static int tiocmget(struct tty_struct *tty)
2841{
2842 struct mgsl_struct *info = tty->driver_data;
2843 unsigned int result;
2844 unsigned long flags;
2845
2846 spin_lock_irqsave(&info->irq_spinlock,flags);
2847 usc_get_serial_signals(info);
2848 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2849
2850 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2851 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2852 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2853 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2854 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2855 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2856
2857 if (debug_level >= DEBUG_LEVEL_INFO)
2858 printk("%s(%d):%s tiocmget() value=%08X\n",
2859 __FILE__,__LINE__, info->device_name, result );
2860 return result;
2861}
2862
2863
2864
2865static int tiocmset(struct tty_struct *tty,
2866 unsigned int set, unsigned int clear)
2867{
2868 struct mgsl_struct *info = tty->driver_data;
2869 unsigned long flags;
2870
2871 if (debug_level >= DEBUG_LEVEL_INFO)
2872 printk("%s(%d):%s tiocmset(%x,%x)\n",
2873 __FILE__,__LINE__,info->device_name, set, clear);
2874
2875 if (set & TIOCM_RTS)
2876 info->serial_signals |= SerialSignal_RTS;
2877 if (set & TIOCM_DTR)
2878 info->serial_signals |= SerialSignal_DTR;
2879 if (clear & TIOCM_RTS)
2880 info->serial_signals &= ~SerialSignal_RTS;
2881 if (clear & TIOCM_DTR)
2882 info->serial_signals &= ~SerialSignal_DTR;
2883
2884 spin_lock_irqsave(&info->irq_spinlock,flags);
2885 usc_set_serial_signals(info);
2886 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2887
2888 return 0;
2889}
2890
2891
2892
2893
2894
2895
2896
2897static int mgsl_break(struct tty_struct *tty, int break_state)
2898{
2899 struct mgsl_struct * info = tty->driver_data;
2900 unsigned long flags;
2901
2902 if (debug_level >= DEBUG_LEVEL_INFO)
2903 printk("%s(%d):mgsl_break(%s,%d)\n",
2904 __FILE__,__LINE__, info->device_name, break_state);
2905
2906 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2907 return -EINVAL;
2908
2909 spin_lock_irqsave(&info->irq_spinlock,flags);
2910 if (break_state == -1)
2911 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2912 else
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2914 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2915 return 0;
2916
2917}
2918
2919
2920
2921
2922
2923
2924
2925static int msgl_get_icount(struct tty_struct *tty,
2926 struct serial_icounter_struct *icount)
2927
2928{
2929 struct mgsl_struct * info = tty->driver_data;
2930 struct mgsl_icount cnow;
2931 unsigned long flags;
2932
2933 spin_lock_irqsave(&info->irq_spinlock,flags);
2934 cnow = info->icount;
2935 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2936
2937 icount->cts = cnow.cts;
2938 icount->dsr = cnow.dsr;
2939 icount->rng = cnow.rng;
2940 icount->dcd = cnow.dcd;
2941 icount->rx = cnow.rx;
2942 icount->tx = cnow.tx;
2943 icount->frame = cnow.frame;
2944 icount->overrun = cnow.overrun;
2945 icount->parity = cnow.parity;
2946 icount->brk = cnow.brk;
2947 icount->buf_overrun = cnow.buf_overrun;
2948 return 0;
2949}
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961static int mgsl_ioctl(struct tty_struct *tty,
2962 unsigned int cmd, unsigned long arg)
2963{
2964 struct mgsl_struct * info = tty->driver_data;
2965
2966 if (debug_level >= DEBUG_LEVEL_INFO)
2967 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2968 info->device_name, cmd );
2969
2970 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2971 return -ENODEV;
2972
2973 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2974 (cmd != TIOCMIWAIT)) {
2975 if (tty->flags & (1 << TTY_IO_ERROR))
2976 return -EIO;
2977 }
2978
2979 return mgsl_ioctl_common(info, cmd, arg);
2980}
2981
2982static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2983{
2984 void __user *argp = (void __user *)arg;
2985
2986 switch (cmd) {
2987 case MGSL_IOCGPARAMS:
2988 return mgsl_get_params(info, argp);
2989 case MGSL_IOCSPARAMS:
2990 return mgsl_set_params(info, argp);
2991 case MGSL_IOCGTXIDLE:
2992 return mgsl_get_txidle(info, argp);
2993 case MGSL_IOCSTXIDLE:
2994 return mgsl_set_txidle(info,(int)arg);
2995 case MGSL_IOCTXENABLE:
2996 return mgsl_txenable(info,(int)arg);
2997 case MGSL_IOCRXENABLE:
2998 return mgsl_rxenable(info,(int)arg);
2999 case MGSL_IOCTXABORT:
3000 return mgsl_txabort(info);
3001 case MGSL_IOCGSTATS:
3002 return mgsl_get_stats(info, argp);
3003 case MGSL_IOCWAITEVENT:
3004 return mgsl_wait_event(info, argp);
3005 case MGSL_IOCLOOPTXDONE:
3006 return mgsl_loopmode_send_done(info);
3007
3008
3009
3010 case TIOCMIWAIT:
3011 return modem_input_wait(info,(int)arg);
3012
3013 default:
3014 return -ENOIOCTLCMD;
3015 }
3016 return 0;
3017}
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3031{
3032 struct mgsl_struct *info = tty->driver_data;
3033 unsigned long flags;
3034
3035 if (debug_level >= DEBUG_LEVEL_INFO)
3036 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3037 tty->driver->name );
3038
3039 mgsl_change_params(info);
3040
3041
3042 if (old_termios->c_cflag & CBAUD &&
3043 !(tty->termios.c_cflag & CBAUD)) {
3044 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3045 spin_lock_irqsave(&info->irq_spinlock,flags);
3046 usc_set_serial_signals(info);
3047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3048 }
3049
3050
3051 if (!(old_termios->c_cflag & CBAUD) &&
3052 tty->termios.c_cflag & CBAUD) {
3053 info->serial_signals |= SerialSignal_DTR;
3054 if (!(tty->termios.c_cflag & CRTSCTS) ||
3055 !test_bit(TTY_THROTTLED, &tty->flags)) {
3056 info->serial_signals |= SerialSignal_RTS;
3057 }
3058 spin_lock_irqsave(&info->irq_spinlock,flags);
3059 usc_set_serial_signals(info);
3060 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3061 }
3062
3063
3064 if (old_termios->c_cflag & CRTSCTS &&
3065 !(tty->termios.c_cflag & CRTSCTS)) {
3066 tty->hw_stopped = 0;
3067 mgsl_start(tty);
3068 }
3069
3070}
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084static void mgsl_close(struct tty_struct *tty, struct file * filp)
3085{
3086 struct mgsl_struct * info = tty->driver_data;
3087
3088 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3089 return;
3090
3091 if (debug_level >= DEBUG_LEVEL_INFO)
3092 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3093 __FILE__,__LINE__, info->device_name, info->port.count);
3094
3095 if (tty_port_close_start(&info->port, tty, filp) == 0)
3096 goto cleanup;
3097
3098 mutex_lock(&info->port.mutex);
3099 if (info->port.flags & ASYNC_INITIALIZED)
3100 mgsl_wait_until_sent(tty, info->timeout);
3101 mgsl_flush_buffer(tty);
3102 tty_ldisc_flush(tty);
3103 shutdown(info);
3104 mutex_unlock(&info->port.mutex);
3105
3106 tty_port_close_end(&info->port, tty);
3107 info->port.tty = NULL;
3108cleanup:
3109 if (debug_level >= DEBUG_LEVEL_INFO)
3110 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3111 tty->driver->name, info->port.count);
3112
3113}
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3127{
3128 struct mgsl_struct * info = tty->driver_data;
3129 unsigned long orig_jiffies, char_time;
3130
3131 if (!info )
3132 return;
3133
3134 if (debug_level >= DEBUG_LEVEL_INFO)
3135 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3136 __FILE__,__LINE__, info->device_name );
3137
3138 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3139 return;
3140
3141 if (!(info->port.flags & ASYNC_INITIALIZED))
3142 goto exit;
3143
3144 orig_jiffies = jiffies;
3145
3146
3147
3148
3149
3150
3151
3152 if ( info->params.data_rate ) {
3153 char_time = info->timeout/(32 * 5);
3154 if (!char_time)
3155 char_time++;
3156 } else
3157 char_time = 1;
3158
3159 if (timeout)
3160 char_time = min_t(unsigned long, char_time, timeout);
3161
3162 if ( info->params.mode == MGSL_MODE_HDLC ||
3163 info->params.mode == MGSL_MODE_RAW ) {
3164 while (info->tx_active) {
3165 msleep_interruptible(jiffies_to_msecs(char_time));
3166 if (signal_pending(current))
3167 break;
3168 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3169 break;
3170 }
3171 } else {
3172 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3173 info->tx_enabled) {
3174 msleep_interruptible(jiffies_to_msecs(char_time));
3175 if (signal_pending(current))
3176 break;
3177 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3178 break;
3179 }
3180 }
3181
3182exit:
3183 if (debug_level >= DEBUG_LEVEL_INFO)
3184 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3185 __FILE__,__LINE__, info->device_name );
3186
3187}
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197static void mgsl_hangup(struct tty_struct *tty)
3198{
3199 struct mgsl_struct * info = tty->driver_data;
3200
3201 if (debug_level >= DEBUG_LEVEL_INFO)
3202 printk("%s(%d):mgsl_hangup(%s)\n",
3203 __FILE__,__LINE__, info->device_name );
3204
3205 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3206 return;
3207
3208 mgsl_flush_buffer(tty);
3209 shutdown(info);
3210
3211 info->port.count = 0;
3212 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3213 info->port.tty = NULL;
3214
3215 wake_up_interruptible(&info->port.open_wait);
3216
3217}
3218
3219
3220
3221
3222
3223
3224
3225static int carrier_raised(struct tty_port *port)
3226{
3227 unsigned long flags;
3228 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3229
3230 spin_lock_irqsave(&info->irq_spinlock, flags);
3231 usc_get_serial_signals(info);
3232 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3233 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3234}
3235
3236static void dtr_rts(struct tty_port *port, int on)
3237{
3238 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3239 unsigned long flags;
3240
3241 spin_lock_irqsave(&info->irq_spinlock,flags);
3242 if (on)
3243 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3244 else
3245 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3246 usc_set_serial_signals(info);
3247 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3248}
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264static int block_til_ready(struct tty_struct *tty, struct file * filp,
3265 struct mgsl_struct *info)
3266{
3267 DECLARE_WAITQUEUE(wait, current);
3268 int retval;
3269 bool do_clocal = false;
3270 bool extra_count = false;
3271 unsigned long flags;
3272 int dcd;
3273 struct tty_port *port = &info->port;
3274
3275 if (debug_level >= DEBUG_LEVEL_INFO)
3276 printk("%s(%d):block_til_ready on %s\n",
3277 __FILE__,__LINE__, tty->driver->name );
3278
3279 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3280
3281 port->flags |= ASYNC_NORMAL_ACTIVE;
3282 return 0;
3283 }
3284
3285 if (tty->termios.c_cflag & CLOCAL)
3286 do_clocal = true;
3287
3288
3289
3290
3291
3292
3293
3294
3295 retval = 0;
3296 add_wait_queue(&port->open_wait, &wait);
3297
3298 if (debug_level >= DEBUG_LEVEL_INFO)
3299 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3300 __FILE__,__LINE__, tty->driver->name, port->count );
3301
3302 spin_lock_irqsave(&info->irq_spinlock, flags);
3303 if (!tty_hung_up_p(filp)) {
3304 extra_count = true;
3305 port->count--;
3306 }
3307 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3308 port->blocked_open++;
3309
3310 while (1) {
3311 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3312 tty_port_raise_dtr_rts(port);
3313
3314 set_current_state(TASK_INTERRUPTIBLE);
3315
3316 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3317 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3318 -EAGAIN : -ERESTARTSYS;
3319 break;
3320 }
3321
3322 dcd = tty_port_carrier_raised(&info->port);
3323
3324 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3325 break;
3326
3327 if (signal_pending(current)) {
3328 retval = -ERESTARTSYS;
3329 break;
3330 }
3331
3332 if (debug_level >= DEBUG_LEVEL_INFO)
3333 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3334 __FILE__,__LINE__, tty->driver->name, port->count );
3335
3336 tty_unlock(tty);
3337 schedule();
3338 tty_lock(tty);
3339 }
3340
3341 set_current_state(TASK_RUNNING);
3342 remove_wait_queue(&port->open_wait, &wait);
3343
3344
3345 if (extra_count)
3346 port->count++;
3347 port->blocked_open--;
3348
3349 if (debug_level >= DEBUG_LEVEL_INFO)
3350 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3351 __FILE__,__LINE__, tty->driver->name, port->count );
3352
3353 if (!retval)
3354 port->flags |= ASYNC_NORMAL_ACTIVE;
3355
3356 return retval;
3357
3358}
3359
3360static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3361{
3362 struct mgsl_struct *info;
3363 int line = tty->index;
3364
3365
3366 if (line >= mgsl_device_count) {
3367 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3368 __FILE__, __LINE__, line);
3369 return -ENODEV;
3370 }
3371
3372
3373 info = mgsl_device_list;
3374 while (info && info->line != line)
3375 info = info->next_device;
3376 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3377 return -ENODEV;
3378 tty->driver_data = info;
3379
3380 return tty_port_install(&info->port, driver, tty);
3381}
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393static int mgsl_open(struct tty_struct *tty, struct file * filp)
3394{
3395 struct mgsl_struct *info = tty->driver_data;
3396 unsigned long flags;
3397 int retval;
3398
3399 info->port.tty = tty;
3400
3401 if (debug_level >= DEBUG_LEVEL_INFO)
3402 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3403 __FILE__,__LINE__,tty->driver->name, info->port.count);
3404
3405
3406 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3407 if (info->port.flags & ASYNC_CLOSING)
3408 interruptible_sleep_on(&info->port.close_wait);
3409 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3410 -EAGAIN : -ERESTARTSYS);
3411 goto cleanup;
3412 }
3413
3414 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3415
3416 spin_lock_irqsave(&info->netlock, flags);
3417 if (info->netcount) {
3418 retval = -EBUSY;
3419 spin_unlock_irqrestore(&info->netlock, flags);
3420 goto cleanup;
3421 }
3422 info->port.count++;
3423 spin_unlock_irqrestore(&info->netlock, flags);
3424
3425 if (info->port.count == 1) {
3426
3427 retval = startup(info);
3428 if (retval < 0)
3429 goto cleanup;
3430 }
3431
3432 retval = block_til_ready(tty, filp, info);
3433 if (retval) {
3434 if (debug_level >= DEBUG_LEVEL_INFO)
3435 printk("%s(%d):block_til_ready(%s) returned %d\n",
3436 __FILE__,__LINE__, info->device_name, retval);
3437 goto cleanup;
3438 }
3439
3440 if (debug_level >= DEBUG_LEVEL_INFO)
3441 printk("%s(%d):mgsl_open(%s) success\n",
3442 __FILE__,__LINE__, info->device_name);
3443 retval = 0;
3444
3445cleanup:
3446 if (retval) {
3447 if (tty->count == 1)
3448 info->port.tty = NULL;
3449 if(info->port.count)
3450 info->port.count--;
3451 }
3452
3453 return retval;
3454
3455}
3456
3457
3458
3459
3460
3461static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3462{
3463 char stat_buf[30];
3464 unsigned long flags;
3465
3466 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3467 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3468 info->device_name, info->io_base, info->irq_level,
3469 info->phys_memory_base, info->phys_lcr_base);
3470 } else {
3471 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3472 info->device_name, info->io_base,
3473 info->irq_level, info->dma_level);
3474 }
3475
3476
3477 spin_lock_irqsave(&info->irq_spinlock,flags);
3478 usc_get_serial_signals(info);
3479 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3480
3481 stat_buf[0] = 0;
3482 stat_buf[1] = 0;
3483 if (info->serial_signals & SerialSignal_RTS)
3484 strcat(stat_buf, "|RTS");
3485 if (info->serial_signals & SerialSignal_CTS)
3486 strcat(stat_buf, "|CTS");
3487 if (info->serial_signals & SerialSignal_DTR)
3488 strcat(stat_buf, "|DTR");
3489 if (info->serial_signals & SerialSignal_DSR)
3490 strcat(stat_buf, "|DSR");
3491 if (info->serial_signals & SerialSignal_DCD)
3492 strcat(stat_buf, "|CD");
3493 if (info->serial_signals & SerialSignal_RI)
3494 strcat(stat_buf, "|RI");
3495
3496 if (info->params.mode == MGSL_MODE_HDLC ||
3497 info->params.mode == MGSL_MODE_RAW ) {
3498 seq_printf(m, " HDLC txok:%d rxok:%d",
3499 info->icount.txok, info->icount.rxok);
3500 if (info->icount.txunder)
3501 seq_printf(m, " txunder:%d", info->icount.txunder);
3502 if (info->icount.txabort)
3503 seq_printf(m, " txabort:%d", info->icount.txabort);
3504 if (info->icount.rxshort)
3505 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3506 if (info->icount.rxlong)
3507 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3508 if (info->icount.rxover)
3509 seq_printf(m, " rxover:%d", info->icount.rxover);
3510 if (info->icount.rxcrc)
3511 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3512 } else {
3513 seq_printf(m, " ASYNC tx:%d rx:%d",
3514 info->icount.tx, info->icount.rx);
3515 if (info->icount.frame)
3516 seq_printf(m, " fe:%d", info->icount.frame);
3517 if (info->icount.parity)
3518 seq_printf(m, " pe:%d", info->icount.parity);
3519 if (info->icount.brk)
3520 seq_printf(m, " brk:%d", info->icount.brk);
3521 if (info->icount.overrun)
3522 seq_printf(m, " oe:%d", info->icount.overrun);
3523 }
3524
3525
3526 seq_printf(m, " %s\n", stat_buf+1);
3527
3528 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3529 info->tx_active,info->bh_requested,info->bh_running,
3530 info->pending_bh);
3531
3532 spin_lock_irqsave(&info->irq_spinlock,flags);
3533 {
3534 u16 Tcsr = usc_InReg( info, TCSR );
3535 u16 Tdmr = usc_InDmaReg( info, TDMR );
3536 u16 Ticr = usc_InReg( info, TICR );
3537 u16 Rscr = usc_InReg( info, RCSR );
3538 u16 Rdmr = usc_InDmaReg( info, RDMR );
3539 u16 Ricr = usc_InReg( info, RICR );
3540 u16 Icr = usc_InReg( info, ICR );
3541 u16 Dccr = usc_InReg( info, DCCR );
3542 u16 Tmr = usc_InReg( info, TMR );
3543 u16 Tccr = usc_InReg( info, TCCR );
3544 u16 Ccar = inw( info->io_base + CCAR );
3545 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3546 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3547 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3548 }
3549 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3550}
3551
3552
3553static int mgsl_proc_show(struct seq_file *m, void *v)
3554{
3555 struct mgsl_struct *info;
3556
3557 seq_printf(m, "synclink driver:%s\n", driver_version);
3558
3559 info = mgsl_device_list;
3560 while( info ) {
3561 line_info(m, info);
3562 info = info->next_device;
3563 }
3564 return 0;
3565}
3566
3567static int mgsl_proc_open(struct inode *inode, struct file *file)
3568{
3569 return single_open(file, mgsl_proc_show, NULL);
3570}
3571
3572static const struct file_operations mgsl_proc_fops = {
3573 .owner = THIS_MODULE,
3574 .open = mgsl_proc_open,
3575 .read = seq_read,
3576 .llseek = seq_lseek,
3577 .release = single_release,
3578};
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3589{
3590 unsigned short BuffersPerFrame;
3591
3592 info->last_mem_alloc = 0;
3593
3594
3595
3596
3597
3598
3599 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3600 if ( info->max_frame_size % DMABUFFERSIZE )
3601 BuffersPerFrame++;
3602
3603 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3627 info->rx_buffer_count = 62 - info->tx_buffer_count;
3628 } else {
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3640 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3641
3642
3643
3644
3645
3646
3647 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3648 info->rx_buffer_count = 62 - info->tx_buffer_count;
3649
3650 }
3651
3652 if ( debug_level >= DEBUG_LEVEL_INFO )
3653 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3654 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3655
3656 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3657 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3658 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3659 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3660 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3661 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3662 return -ENOMEM;
3663 }
3664
3665 mgsl_reset_rx_dma_buffers( info );
3666 mgsl_reset_tx_dma_buffers( info );
3667
3668 return 0;
3669
3670}
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3696{
3697 unsigned int i;
3698
3699 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3700
3701 info->buffer_list = info->memory_base + info->last_mem_alloc;
3702 info->buffer_list_phys = info->last_mem_alloc;
3703 info->last_mem_alloc += BUFFERLISTSIZE;
3704 } else {
3705
3706
3707
3708
3709
3710
3711 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3712 if (info->buffer_list == NULL)
3713 return -ENOMEM;
3714 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3715 }
3716
3717
3718
3719 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3720
3721
3722
3723
3724 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3725 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3726 info->tx_buffer_list += info->rx_buffer_count;
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3738
3739 info->rx_buffer_list[i].phys_entry =
3740 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3741
3742
3743
3744
3745 info->rx_buffer_list[i].link = info->buffer_list_phys;
3746
3747 if ( i < info->rx_buffer_count - 1 )
3748 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3749 }
3750
3751 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3752
3753 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3754 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3755
3756
3757
3758
3759 info->tx_buffer_list[i].link = info->buffer_list_phys +
3760 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3761
3762 if ( i < info->tx_buffer_count - 1 )
3763 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3764 }
3765
3766 return 0;
3767
3768}
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3780{
3781 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3782 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3783
3784 info->buffer_list = NULL;
3785 info->rx_buffer_list = NULL;
3786 info->tx_buffer_list = NULL;
3787
3788}
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3807{
3808 int i;
3809 u32 phys_addr;
3810
3811
3812
3813 for ( i = 0; i < Buffercount; i++ ) {
3814 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3815
3816 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3817 phys_addr = info->last_mem_alloc;
3818 info->last_mem_alloc += DMABUFFERSIZE;
3819 } else {
3820
3821 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3822 if (BufferList[i].virt_addr == NULL)
3823 return -ENOMEM;
3824 phys_addr = (u32)(BufferList[i].dma_addr);
3825 }
3826 BufferList[i].phys_addr = phys_addr;
3827 }
3828
3829 return 0;
3830
3831}
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3848{
3849 int i;
3850
3851 if ( BufferList ) {
3852 for ( i = 0 ; i < Buffercount ; i++ ) {
3853 if ( BufferList[i].virt_addr ) {
3854 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3855 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3856 BufferList[i].virt_addr = NULL;
3857 }
3858 }
3859 }
3860
3861}
3862
3863
3864
3865
3866
3867
3868
3869
3870static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3871{
3872 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3873 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3874 mgsl_free_buffer_list_memory( info );
3875
3876}
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3892{
3893 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3894 if ( info->intermediate_rxbuffer == NULL )
3895 return -ENOMEM;
3896
3897 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3898 if (!info->flag_buf) {
3899 kfree(info->intermediate_rxbuffer);
3900 info->intermediate_rxbuffer = NULL;
3901 return -ENOMEM;
3902 }
3903 return 0;
3904
3905}
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3918{
3919 kfree(info->intermediate_rxbuffer);
3920 info->intermediate_rxbuffer = NULL;
3921 kfree(info->flag_buf);
3922 info->flag_buf = NULL;
3923
3924}
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3940{
3941 int i;
3942
3943 if ( debug_level >= DEBUG_LEVEL_INFO )
3944 printk("%s %s(%d) allocating %d tx holding buffers\n",
3945 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3946
3947 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3948
3949 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3950 info->tx_holding_buffers[i].buffer =
3951 kmalloc(info->max_frame_size, GFP_KERNEL);
3952 if (info->tx_holding_buffers[i].buffer == NULL) {
3953 for (--i; i >= 0; i--) {
3954 kfree(info->tx_holding_buffers[i].buffer);
3955 info->tx_holding_buffers[i].buffer = NULL;
3956 }
3957 return -ENOMEM;
3958 }
3959 }
3960
3961 return 0;
3962
3963}
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3976{
3977 int i;
3978
3979 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3980 kfree(info->tx_holding_buffers[i].buffer);
3981 info->tx_holding_buffers[i].buffer = NULL;
3982 }
3983
3984 info->get_tx_holding_index = 0;
3985 info->put_tx_holding_index = 0;
3986 info->tx_holding_count = 0;
3987
3988}
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4006{
4007 bool ret = false;
4008
4009 if ( info->tx_holding_count ) {
4010
4011
4012
4013 struct tx_holding_buffer *ptx =
4014 &info->tx_holding_buffers[info->get_tx_holding_index];
4015 int num_free = num_free_tx_dma_buffers(info);
4016 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4017 if ( ptx->buffer_size % DMABUFFERSIZE )
4018 ++num_needed;
4019
4020 if (num_needed <= num_free) {
4021 info->xmit_cnt = ptx->buffer_size;
4022 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4023
4024 --info->tx_holding_count;
4025 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4026 info->get_tx_holding_index=0;
4027
4028
4029 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4030
4031 ret = true;
4032 }
4033 }
4034
4035 return ret;
4036}
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4052{
4053 struct tx_holding_buffer *ptx;
4054
4055 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4056 return 0;
4057 }
4058
4059 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4060 ptx->buffer_size = BufferSize;
4061 memcpy( ptx->buffer, Buffer, BufferSize);
4062
4063 ++info->tx_holding_count;
4064 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4065 info->put_tx_holding_index=0;
4066
4067 return 1;
4068}
4069
4070static int mgsl_claim_resources(struct mgsl_struct *info)
4071{
4072 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4073 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4074 __FILE__,__LINE__,info->device_name, info->io_base);
4075 return -ENODEV;
4076 }
4077 info->io_addr_requested = true;
4078
4079 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4080 info->device_name, info ) < 0 ) {
4081 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4082 __FILE__,__LINE__,info->device_name, info->irq_level );
4083 goto errout;
4084 }
4085 info->irq_requested = true;
4086
4087 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4088 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4089 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4090 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4091 goto errout;
4092 }
4093 info->shared_mem_requested = true;
4094 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4095 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4096 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4097 goto errout;
4098 }
4099 info->lcr_mem_requested = true;
4100
4101 info->memory_base = ioremap_nocache(info->phys_memory_base,
4102 0x40000);
4103 if (!info->memory_base) {
4104 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4105 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4106 goto errout;
4107 }
4108
4109 if ( !mgsl_memory_test(info) ) {
4110 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4111 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4112 goto errout;
4113 }
4114
4115 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4116 PAGE_SIZE);
4117 if (!info->lcr_base) {
4118 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4119 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4120 goto errout;
4121 }
4122 info->lcr_base += info->lcr_offset;
4123
4124 } else {
4125
4126
4127 if (request_dma(info->dma_level,info->device_name) < 0){
4128 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4129 __FILE__,__LINE__,info->device_name, info->dma_level );
4130 mgsl_release_resources( info );
4131 return -ENODEV;
4132 }
4133 info->dma_requested = true;
4134
4135
4136 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4137 enable_dma(info->dma_level);
4138 }
4139
4140 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4141 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4142 __FILE__,__LINE__,info->device_name, info->dma_level );
4143 goto errout;
4144 }
4145
4146 return 0;
4147errout:
4148 mgsl_release_resources(info);
4149 return -ENODEV;
4150
4151}
4152
4153static void mgsl_release_resources(struct mgsl_struct *info)
4154{
4155 if ( debug_level >= DEBUG_LEVEL_INFO )
4156 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4157 __FILE__,__LINE__,info->device_name );
4158
4159 if ( info->irq_requested ) {
4160 free_irq(info->irq_level, info);
4161 info->irq_requested = false;
4162 }
4163 if ( info->dma_requested ) {
4164 disable_dma(info->dma_level);
4165 free_dma(info->dma_level);
4166 info->dma_requested = false;
4167 }
4168 mgsl_free_dma_buffers(info);
4169 mgsl_free_intermediate_rxbuffer_memory(info);
4170 mgsl_free_intermediate_txbuffer_memory(info);
4171
4172 if ( info->io_addr_requested ) {
4173 release_region(info->io_base,info->io_addr_size);
4174 info->io_addr_requested = false;
4175 }
4176 if ( info->shared_mem_requested ) {
4177 release_mem_region(info->phys_memory_base,0x40000);
4178 info->shared_mem_requested = false;
4179 }
4180 if ( info->lcr_mem_requested ) {
4181 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4182 info->lcr_mem_requested = false;
4183 }
4184 if (info->memory_base){
4185 iounmap(info->memory_base);
4186 info->memory_base = NULL;
4187 }
4188 if (info->lcr_base){
4189 iounmap(info->lcr_base - info->lcr_offset);
4190 info->lcr_base = NULL;
4191 }
4192
4193 if ( debug_level >= DEBUG_LEVEL_INFO )
4194 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4195 __FILE__,__LINE__,info->device_name );
4196
4197}
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207static void mgsl_add_device( struct mgsl_struct *info )
4208{
4209 info->next_device = NULL;
4210 info->line = mgsl_device_count;
4211 sprintf(info->device_name,"ttySL%d",info->line);
4212
4213 if (info->line < MAX_TOTAL_DEVICES) {
4214 if (maxframe[info->line])
4215 info->max_frame_size = maxframe[info->line];
4216
4217 if (txdmabufs[info->line]) {
4218 info->num_tx_dma_buffers = txdmabufs[info->line];
4219 if (info->num_tx_dma_buffers < 1)
4220 info->num_tx_dma_buffers = 1;
4221 }
4222
4223 if (txholdbufs[info->line]) {
4224 info->num_tx_holding_buffers = txholdbufs[info->line];
4225 if (info->num_tx_holding_buffers < 1)
4226 info->num_tx_holding_buffers = 1;
4227 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4228 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4229 }
4230 }
4231
4232 mgsl_device_count++;
4233
4234 if ( !mgsl_device_list )
4235 mgsl_device_list = info;
4236 else {
4237 struct mgsl_struct *current_dev = mgsl_device_list;
4238 while( current_dev->next_device )
4239 current_dev = current_dev->next_device;
4240 current_dev->next_device = info;
4241 }
4242
4243 if ( info->max_frame_size < 4096 )
4244 info->max_frame_size = 4096;
4245 else if ( info->max_frame_size > 65535 )
4246 info->max_frame_size = 65535;
4247
4248 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4249 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4250 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4251 info->phys_memory_base, info->phys_lcr_base,
4252 info->max_frame_size );
4253 } else {
4254 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4255 info->device_name, info->io_base, info->irq_level, info->dma_level,
4256 info->max_frame_size );
4257 }
4258
4259#if SYNCLINK_GENERIC_HDLC
4260 hdlcdev_init(info);
4261#endif
4262
4263}
4264
4265static const struct tty_port_operations mgsl_port_ops = {
4266 .carrier_raised = carrier_raised,
4267 .dtr_rts = dtr_rts,
4268};
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278static struct mgsl_struct* mgsl_allocate_device(void)
4279{
4280 struct mgsl_struct *info;
4281
4282 info = kzalloc(sizeof(struct mgsl_struct),
4283 GFP_KERNEL);
4284
4285 if (!info) {
4286 printk("Error can't allocate device instance data\n");
4287 } else {
4288 tty_port_init(&info->port);
4289 info->port.ops = &mgsl_port_ops;
4290 info->magic = MGSL_MAGIC;
4291 INIT_WORK(&info->task, mgsl_bh_handler);
4292 info->max_frame_size = 4096;
4293 info->port.close_delay = 5*HZ/10;
4294 info->port.closing_wait = 30*HZ;
4295 init_waitqueue_head(&info->status_event_wait_q);
4296 init_waitqueue_head(&info->event_wait_q);
4297 spin_lock_init(&info->irq_spinlock);
4298 spin_lock_init(&info->netlock);
4299 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4300 info->idle_mode = HDLC_TXIDLE_FLAGS;
4301 info->num_tx_dma_buffers = 1;
4302 info->num_tx_holding_buffers = 0;
4303 }
4304
4305 return info;
4306
4307}
4308
4309static const struct tty_operations mgsl_ops = {
4310 .install = mgsl_install,
4311 .open = mgsl_open,
4312 .close = mgsl_close,
4313 .write = mgsl_write,
4314 .put_char = mgsl_put_char,
4315 .flush_chars = mgsl_flush_chars,
4316 .write_room = mgsl_write_room,
4317 .chars_in_buffer = mgsl_chars_in_buffer,
4318 .flush_buffer = mgsl_flush_buffer,
4319 .ioctl = mgsl_ioctl,
4320 .throttle = mgsl_throttle,
4321 .unthrottle = mgsl_unthrottle,
4322 .send_xchar = mgsl_send_xchar,
4323 .break_ctl = mgsl_break,
4324 .wait_until_sent = mgsl_wait_until_sent,
4325 .set_termios = mgsl_set_termios,
4326 .stop = mgsl_stop,
4327 .start = mgsl_start,
4328 .hangup = mgsl_hangup,
4329 .tiocmget = tiocmget,
4330 .tiocmset = tiocmset,
4331 .get_icount = msgl_get_icount,
4332 .proc_fops = &mgsl_proc_fops,
4333};
4334
4335
4336
4337
4338static int mgsl_init_tty(void)
4339{
4340 int rc;
4341
4342 serial_driver = alloc_tty_driver(128);
4343 if (!serial_driver)
4344 return -ENOMEM;
4345
4346 serial_driver->driver_name = "synclink";
4347 serial_driver->name = "ttySL";
4348 serial_driver->major = ttymajor;
4349 serial_driver->minor_start = 64;
4350 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4351 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4352 serial_driver->init_termios = tty_std_termios;
4353 serial_driver->init_termios.c_cflag =
4354 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4355 serial_driver->init_termios.c_ispeed = 9600;
4356 serial_driver->init_termios.c_ospeed = 9600;
4357 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4358 tty_set_operations(serial_driver, &mgsl_ops);
4359 if ((rc = tty_register_driver(serial_driver)) < 0) {
4360 printk("%s(%d):Couldn't register serial driver\n",
4361 __FILE__,__LINE__);
4362 put_tty_driver(serial_driver);
4363 serial_driver = NULL;
4364 return rc;
4365 }
4366
4367 printk("%s %s, tty major#%d\n",
4368 driver_name, driver_version,
4369 serial_driver->major);
4370 return 0;
4371}
4372
4373
4374
4375static void mgsl_enum_isa_devices(void)
4376{
4377 struct mgsl_struct *info;
4378 int i;
4379
4380
4381
4382 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4383 if ( debug_level >= DEBUG_LEVEL_INFO )
4384 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4385 io[i], irq[i], dma[i] );
4386
4387 info = mgsl_allocate_device();
4388 if ( !info ) {
4389
4390 if ( debug_level >= DEBUG_LEVEL_ERROR )
4391 printk( "can't allocate device instance data.\n");
4392 continue;
4393 }
4394
4395
4396 info->io_base = (unsigned int)io[i];
4397 info->irq_level = (unsigned int)irq[i];
4398 info->irq_level = irq_canonicalize(info->irq_level);
4399 info->dma_level = (unsigned int)dma[i];
4400 info->bus_type = MGSL_BUS_TYPE_ISA;
4401 info->io_addr_size = 16;
4402 info->irq_flags = 0;
4403
4404 mgsl_add_device( info );
4405 }
4406}
4407
4408static void synclink_cleanup(void)
4409{
4410 int rc;
4411 struct mgsl_struct *info;
4412 struct mgsl_struct *tmp;
4413
4414 printk("Unloading %s: %s\n", driver_name, driver_version);
4415
4416 if (serial_driver) {
4417 if ((rc = tty_unregister_driver(serial_driver)))
4418 printk("%s(%d) failed to unregister tty driver err=%d\n",
4419 __FILE__,__LINE__,rc);
4420 put_tty_driver(serial_driver);
4421 }
4422
4423 info = mgsl_device_list;
4424 while(info) {
4425#if SYNCLINK_GENERIC_HDLC
4426 hdlcdev_exit(info);
4427#endif
4428 mgsl_release_resources(info);
4429 tmp = info;
4430 info = info->next_device;
4431 tty_port_destroy(&tmp->port);
4432 kfree(tmp);
4433 }
4434
4435 if (pci_registered)
4436 pci_unregister_driver(&synclink_pci_driver);
4437}
4438
4439static int __init synclink_init(void)
4440{
4441 int rc;
4442
4443 if (break_on_load) {
4444 mgsl_get_text_ptr();
4445 BREAKPOINT();
4446 }
4447
4448 printk("%s %s\n", driver_name, driver_version);
4449
4450 mgsl_enum_isa_devices();
4451 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4452 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4453 else
4454 pci_registered = true;
4455
4456 if ((rc = mgsl_init_tty()) < 0)
4457 goto error;
4458
4459 return 0;
4460
4461error:
4462 synclink_cleanup();
4463 return rc;
4464}
4465
4466static void __exit synclink_exit(void)
4467{
4468 synclink_cleanup();
4469}
4470
4471module_init(synclink_init);
4472module_exit(synclink_exit);
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4496{
4497
4498
4499
4500 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4501
4502
4503 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4504 inw( info->io_base + CCAR );
4505
4506}
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4523{
4524
4525 outw( Cmd + info->mbre_bit, info->io_base );
4526
4527
4528 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4529 inw( info->io_base );
4530
4531}
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4550{
4551
4552
4553
4554 outw( RegAddr + info->mbre_bit, info->io_base );
4555 outw( RegValue, info->io_base );
4556
4557
4558 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4559 inw( info->io_base );
4560
4561}
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4579{
4580
4581
4582
4583 outw( RegAddr + info->mbre_bit, info->io_base );
4584 return inw( info->io_base );
4585
4586}
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4606{
4607 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4608 outw( RegValue, info->io_base + CCAR );
4609
4610
4611 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4612 inw( info->io_base + CCAR );
4613
4614}
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4631{
4632 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4633 return inw( info->io_base + CCAR );
4634
4635}
4636
4637
4638
4639
4640
4641
4642
4643
4644static void usc_set_sdlc_mode( struct mgsl_struct *info )
4645{
4646 u16 RegValue;
4647 bool PreSL1660;
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658 usc_OutReg(info,TMCR,0x1f);
4659 RegValue=usc_InReg(info,TMDR);
4660 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4661
4662 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4663 {
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676 RegValue = 0x8e06;
4677
4678
4679
4680
4681
4682 }
4683 else
4684 {
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696 if (info->params.mode == MGSL_MODE_RAW) {
4697 RegValue = 0x0001;
4698
4699 usc_OutReg( info, IOCR,
4700 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714 RegValue |= 0x0400;
4715 }
4716 else {
4717
4718 RegValue = 0x0606;
4719
4720 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4721 RegValue |= BIT14;
4722 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4723 RegValue |= BIT15;
4724 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4725 RegValue |= BIT15 | BIT14;
4726 }
4727
4728 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4729 RegValue |= BIT13;
4730 }
4731
4732 if ( info->params.mode == MGSL_MODE_HDLC &&
4733 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4734 RegValue |= BIT12;
4735
4736 if ( info->params.addr_filter != 0xff )
4737 {
4738
4739 usc_OutReg( info, RSR, info->params.addr_filter );
4740 RegValue |= BIT4;
4741 }
4742
4743 usc_OutReg( info, CMR, RegValue );
4744 info->cmr_value = RegValue;
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761 RegValue = 0x0500;
4762
4763 switch ( info->params.encoding ) {
4764 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4765 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4766 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
4767 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4768 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4769 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4770 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
4771 }
4772
4773 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4774 RegValue |= BIT9;
4775 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4776 RegValue |= ( BIT12 | BIT10 | BIT9 );
4777
4778 usc_OutReg( info, RMR, RegValue );
4779
4780
4781
4782
4783
4784
4785
4786
4787 usc_OutReg( info, RCLR, RCLRVALUE );
4788
4789 usc_RCmd( info, RCmd_SelectRicrdma_level );
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809 RegValue = usc_InReg( info, RICR ) & 0xc0;
4810
4811 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4812 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4813 else
4814 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4815
4816
4817
4818 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4819 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836 RegValue = 0x0400;
4837
4838 switch ( info->params.encoding ) {
4839 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4840 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4841 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
4842 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4843 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4844 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4845 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
4846 }
4847
4848 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4849 RegValue |= BIT9 | BIT8;
4850 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4851 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4852
4853 usc_OutReg( info, TMR, RegValue );
4854
4855 usc_set_txidle( info );
4856
4857
4858 usc_TCmd( info, TCmd_SelectTicrdma_level );
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4876 usc_OutReg( info, TICR, 0x0736 );
4877 else
4878 usc_OutReg( info, TICR, 0x1436 );
4879
4880 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4881 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900 info->tcsr_value = 0;
4901
4902 if ( !PreSL1660 )
4903 info->tcsr_value |= TCSR_UNDERWAIT;
4904
4905 usc_OutReg( info, TCSR, info->tcsr_value );
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920 RegValue = 0x0f40;
4921
4922 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4923 RegValue |= 0x0003;
4924 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4925 RegValue |= 0x0004;
4926 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4927 RegValue |= 0x0006;
4928 else
4929 RegValue |= 0x0007;
4930
4931 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4932 RegValue |= 0x0018;
4933 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4934 RegValue |= 0x0020;
4935 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4936 RegValue |= 0x0038;
4937 else
4938 RegValue |= 0x0030;
4939
4940 usc_OutReg( info, CMCR, RegValue );
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958 RegValue = 0x0000;
4959
4960 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
4961 u32 XtalSpeed;
4962 u32 DpllDivisor;
4963 u16 Tc;
4964
4965
4966
4967
4968 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4969 XtalSpeed = 11059200;
4970 else
4971 XtalSpeed = 14745600;
4972
4973 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4974 DpllDivisor = 16;
4975 RegValue |= BIT10;
4976 }
4977 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4978 DpllDivisor = 8;
4979 RegValue |= BIT11;
4980 }
4981 else
4982 DpllDivisor = 32;
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998 if ( info->params.clock_speed )
4999 {
5000 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5001 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5002 / info->params.clock_speed) )
5003 Tc--;
5004 }
5005 else
5006 Tc = -1;
5007
5008
5009
5010 usc_OutReg( info, TC1R, Tc );
5011
5012 RegValue |= BIT4;
5013
5014 switch ( info->params.encoding ) {
5015 case HDLC_ENCODING_NRZ:
5016 case HDLC_ENCODING_NRZB:
5017 case HDLC_ENCODING_NRZI_MARK:
5018 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5019 case HDLC_ENCODING_BIPHASE_MARK:
5020 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5021 case HDLC_ENCODING_BIPHASE_LEVEL:
5022 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
5023 }
5024 }
5025
5026 usc_OutReg( info, HCR, RegValue );
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047 usc_OutReg( info, CCSR, 0x1020 );
5048
5049
5050 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5051 usc_OutReg( info, SICR,
5052 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5053 }
5054
5055
5056
5057 usc_EnableMasterIrqBit( info );
5058
5059 usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
5060 TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
5061
5062
5063 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5064 usc_EnableInterrupts(info, MISC);
5065
5066 info->mbre_bit = 0;
5067 outw( 0, info->io_base );
5068 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5069 info->mbre_bit = BIT8;
5070 outw( BIT8, info->io_base );
5071
5072 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5073
5074
5075 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5076 }
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5101
5102 usc_OutDmaReg( info, DCR, 0xa00b );
5103 }
5104 else
5105 usc_OutDmaReg( info, DCR, 0x800b );
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121 usc_OutDmaReg( info, RDMR, 0xf200 );
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137 usc_OutDmaReg( info, TDMR, 0xf200 );
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153 usc_OutDmaReg( info, DICR, 0x9000 );
5154
5155 usc_InDmaReg( info, RDMR );
5156 usc_InDmaReg( info, TDMR );
5157 usc_OutDmaReg( info, CDIR, 0x0303 );
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173 RegValue = 0x8080;
5174
5175 switch ( info->params.preamble_length ) {
5176 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5177 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5178 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
5179 }
5180
5181 switch ( info->params.preamble ) {
5182 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
5183 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5184 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5185 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
5186 }
5187
5188 usc_OutReg( info, CCR, RegValue );
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5199
5200 usc_OutDmaReg( info, BDCR, 0x0000 );
5201 }
5202 else
5203 usc_OutDmaReg( info, BDCR, 0x2000 );
5204
5205 usc_stop_transmitter(info);
5206 usc_stop_receiver(info);
5207
5208}
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5221{
5222 if (enable) {
5223
5224 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239 usc_OutReg( info, CMCR, 0x0f64 );
5240
5241
5242
5243 if (info->params.clock_speed) {
5244 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5245 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5246 else
5247 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5248 } else
5249 usc_OutReg(info, TC0R, (u16)8);
5250
5251
5252
5253 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5254
5255
5256 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5257
5258
5259 info->loopback_bits = 0x300;
5260 outw( 0x0300, info->io_base + CCAR );
5261 } else {
5262
5263 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
5264
5265
5266 info->loopback_bits = 0;
5267 outw( 0,info->io_base + CCAR );
5268 }
5269
5270}
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5285{
5286 u32 XtalSpeed;
5287 u16 Tc;
5288
5289 if ( data_rate ) {
5290 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5291 XtalSpeed = 11059200;
5292 else
5293 XtalSpeed = 14745600;
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303 Tc = (u16)(XtalSpeed/data_rate);
5304 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5305 Tc--;
5306
5307
5308 usc_OutReg( info, TC0R, Tc );
5309
5310
5311
5312
5313
5314
5315
5316 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5317
5318
5319 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5320 } else {
5321
5322 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5323 }
5324
5325}
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5342{
5343 int start_index;
5344 int end_index;
5345 int frame_start_index;
5346 bool start_of_frame_found = false;
5347 bool end_of_frame_found = false;
5348 bool reprogram_dma = false;
5349
5350 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5351 u32 phys_addr;
5352
5353 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5354 usc_RCmd( info, RCmd_EnterHuntmode );
5355 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5356
5357
5358
5359
5360 frame_start_index = start_index = end_index = info->current_rx_buffer;
5361
5362
5363
5364
5365
5366
5367 while( !buffer_list[end_index].count )
5368 {
5369
5370
5371
5372 if ( !start_of_frame_found )
5373 {
5374 start_of_frame_found = true;
5375 frame_start_index = end_index;
5376 end_of_frame_found = false;
5377 }
5378
5379 if ( buffer_list[end_index].status )
5380 {
5381
5382
5383
5384
5385
5386
5387 start_of_frame_found = false;
5388 end_of_frame_found = true;
5389 }
5390
5391
5392 end_index++;
5393 if ( end_index == info->rx_buffer_count )
5394 end_index = 0;
5395
5396 if ( start_index == end_index )
5397 {
5398
5399
5400
5401 mgsl_reset_rx_dma_buffers( info );
5402 frame_start_index = 0;
5403 start_of_frame_found = false;
5404 reprogram_dma = true;
5405 break;
5406 }
5407 }
5408
5409 if ( start_of_frame_found && !end_of_frame_found )
5410 {
5411
5412
5413
5414
5415
5416
5417
5418 start_index = frame_start_index;
5419
5420 do
5421 {
5422 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5423
5424
5425 if ( start_index == info->rx_buffer_count )
5426 start_index = 0;
5427
5428 } while( start_index != end_index );
5429
5430 reprogram_dma = true;
5431 }
5432
5433 if ( reprogram_dma )
5434 {
5435 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5436 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5437 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5438
5439 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5440
5441
5442 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5443
5444
5445 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5446 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5447 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5448
5449 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5450 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5451 usc_EnableInterrupts( info, RECEIVE_STATUS );
5452
5453
5454
5455
5456 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
5457 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5458 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5459 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5460 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5461 else
5462 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5463 }
5464 else
5465 {
5466
5467 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5468 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5469 }
5470
5471}
5472
5473
5474
5475
5476
5477
5478
5479
5480static void usc_stop_receiver( struct mgsl_struct *info )
5481{
5482 if (debug_level >= DEBUG_LEVEL_ISR)
5483 printk("%s(%d):usc_stop_receiver(%s)\n",
5484 __FILE__,__LINE__, info->device_name );
5485
5486
5487
5488 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5489
5490 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5491 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5492 usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
5493
5494 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5495
5496
5497 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5498 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5499
5500 info->rx_enabled = false;
5501 info->rx_overflow = false;
5502 info->rx_rcc_underrun = false;
5503
5504}
5505
5506
5507
5508
5509
5510
5511
5512
5513static void usc_start_receiver( struct mgsl_struct *info )
5514{
5515 u32 phys_addr;
5516
5517 if (debug_level >= DEBUG_LEVEL_ISR)
5518 printk("%s(%d):usc_start_receiver(%s)\n",
5519 __FILE__,__LINE__, info->device_name );
5520
5521 mgsl_reset_rx_dma_buffers( info );
5522 usc_stop_receiver( info );
5523
5524 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5525 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5526
5527 if ( info->params.mode == MGSL_MODE_HDLC ||
5528 info->params.mode == MGSL_MODE_RAW ) {
5529
5530
5531
5532
5533
5534 phys_addr = info->rx_buffer_list[0].phys_entry;
5535 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5536 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5537
5538 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5539 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5540 usc_EnableInterrupts( info, RECEIVE_STATUS );
5541
5542
5543
5544
5545 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
5546 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5547 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5548 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5549 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5550 else
5551 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5552 } else {
5553 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5554 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
5555 usc_EnableInterrupts(info, RECEIVE_DATA);
5556
5557 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5558 usc_RCmd( info, RCmd_EnterHuntmode );
5559
5560 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5561 }
5562
5563 usc_OutReg( info, CCSR, 0x1020 );
5564
5565 info->rx_enabled = true;
5566
5567}
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577static void usc_start_transmitter( struct mgsl_struct *info )
5578{
5579 u32 phys_addr;
5580 unsigned int FrameSize;
5581
5582 if (debug_level >= DEBUG_LEVEL_ISR)
5583 printk("%s(%d):usc_start_transmitter(%s)\n",
5584 __FILE__,__LINE__, info->device_name );
5585
5586 if ( info->xmit_cnt ) {
5587
5588
5589
5590
5591
5592 info->drop_rts_on_tx_done = false;
5593
5594 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5595 usc_get_serial_signals( info );
5596 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5597 info->serial_signals |= SerialSignal_RTS;
5598 usc_set_serial_signals( info );
5599 info->drop_rts_on_tx_done = true;
5600 }
5601 }
5602
5603
5604 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5605 if ( !info->tx_active ) {
5606 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5607 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5608 usc_EnableInterrupts(info, TRANSMIT_DATA);
5609 usc_load_txfifo(info);
5610 }
5611 } else {
5612
5613 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5614
5615
5616
5617
5618 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5619
5620
5621
5622
5623
5624 if ( info->params.mode == MGSL_MODE_RAW )
5625 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5626
5627
5628
5629 usc_OutReg( info, TCLR, (u16)FrameSize );
5630
5631 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5632
5633
5634 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5635 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5636 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5637
5638 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5639 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5640 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5641
5642 if ( info->params.mode == MGSL_MODE_RAW &&
5643 info->num_tx_dma_buffers > 1 ) {
5644
5645
5646
5647
5648
5649
5650
5651 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5652 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5653 }
5654
5655
5656 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5657
5658 usc_TCmd( info, TCmd_SendFrame );
5659
5660 mod_timer(&info->tx_timer, jiffies +
5661 msecs_to_jiffies(5000));
5662 }
5663 info->tx_active = true;
5664 }
5665
5666 if ( !info->tx_enabled ) {
5667 info->tx_enabled = true;
5668 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5669 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5670 else
5671 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5672 }
5673
5674}
5675
5676
5677
5678
5679
5680
5681
5682
5683static void usc_stop_transmitter( struct mgsl_struct *info )
5684{
5685 if (debug_level >= DEBUG_LEVEL_ISR)
5686 printk("%s(%d):usc_stop_transmitter(%s)\n",
5687 __FILE__,__LINE__, info->device_name );
5688
5689 del_timer(&info->tx_timer);
5690
5691 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5692 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5693 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5694
5695 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5696 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5697 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5698
5699 info->tx_enabled = false;
5700 info->tx_active = false;
5701
5702}
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712static void usc_load_txfifo( struct mgsl_struct *info )
5713{
5714 int Fifocount;
5715 u8 TwoBytes[2];
5716
5717 if ( !info->xmit_cnt && !info->x_char )
5718 return;
5719
5720
5721 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5722
5723
5724
5725 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5726
5727
5728
5729 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5730
5731
5732 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5733 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5734 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5735 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5736
5737 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5738
5739 info->xmit_cnt -= 2;
5740 info->icount.tx += 2;
5741 } else {
5742
5743
5744 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5745 info->io_base + CCAR );
5746
5747 if (info->x_char) {
5748
5749 outw( info->x_char,info->io_base + CCAR );
5750 info->x_char = 0;
5751 } else {
5752 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5753 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5754 info->xmit_cnt--;
5755 }
5756 info->icount.tx++;
5757 }
5758 }
5759
5760}
5761
5762
5763
5764
5765
5766
5767
5768
5769static void usc_reset( struct mgsl_struct *info )
5770{
5771 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5772 int i;
5773 u32 readval;
5774
5775
5776
5777
5778 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5779 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5780
5781 info->misc_ctrl_value |= BIT30;
5782 *MiscCtrl = info->misc_ctrl_value;
5783
5784
5785
5786
5787
5788
5789 for(i=0;i<10;i++)
5790 readval = *MiscCtrl;
5791
5792 info->misc_ctrl_value &= ~BIT30;
5793 *MiscCtrl = info->misc_ctrl_value;
5794
5795 *LCR0BRDR = BUS_DESCRIPTOR(
5796 1,
5797 2,
5798 2,
5799 0,
5800 4,
5801 0,
5802 0,
5803 5
5804 );
5805 } else {
5806
5807 outb( 0,info->io_base + 8 );
5808 }
5809
5810 info->mbre_bit = 0;
5811 info->loopback_bits = 0;
5812 info->usc_idle_mode = 0;
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831 outw( 0x000c,info->io_base + SDPIN );
5832
5833
5834 outw( 0,info->io_base );
5835 outw( 0,info->io_base + CCAR );
5836
5837
5838 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855 usc_OutReg( info, PCR, 0xf0f5 );
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872 usc_OutReg( info, IOCR, 0x0004 );
5873
5874}
5875
5876
5877
5878
5879
5880
5881
5882
5883static void usc_set_async_mode( struct mgsl_struct *info )
5884{
5885 u16 RegValue;
5886
5887
5888 usc_DisableMasterIrqBit( info );
5889
5890 outw( 0, info->io_base );
5891 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5892
5893 usc_loopback_frame( info );
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907 RegValue = 0;
5908 if ( info->params.stop_bits != 1 )
5909 RegValue |= BIT14;
5910 usc_OutReg( info, CMR, RegValue );
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925 RegValue = 0;
5926
5927 if ( info->params.data_bits != 8 )
5928 RegValue |= BIT4 | BIT3 | BIT2;
5929
5930 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5931 RegValue |= BIT5;
5932 if ( info->params.parity != ASYNC_PARITY_ODD )
5933 RegValue |= BIT6;
5934 }
5935
5936 usc_OutReg( info, RMR, RegValue );
5937
5938
5939
5940
5941 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964 usc_OutReg( info, RICR, 0x0000 );
5965
5966 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5967 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982 RegValue = 0;
5983
5984 if ( info->params.data_bits != 8 )
5985 RegValue |= BIT4 | BIT3 | BIT2;
5986
5987 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5988 RegValue |= BIT5;
5989 if ( info->params.parity != ASYNC_PARITY_ODD )
5990 RegValue |= BIT6;
5991 }
5992
5993 usc_OutReg( info, TMR, RegValue );
5994
5995 usc_set_txidle( info );
5996
5997
5998
5999
6000 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018 usc_OutReg( info, TICR, 0x1f40 );
6019
6020 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6021 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6022
6023 usc_enable_async_clock( info, info->params.data_rate );
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044 usc_OutReg( info, CCSR, 0x0020 );
6045
6046 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6047 RECEIVE_DATA + RECEIVE_STATUS );
6048
6049 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6050 RECEIVE_DATA + RECEIVE_STATUS );
6051
6052 usc_EnableMasterIrqBit( info );
6053
6054 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6055
6056
6057 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6058 }
6059
6060 if (info->params.loopback) {
6061 info->loopback_bits = 0x300;
6062 outw(0x0300, info->io_base + CCAR);
6063 }
6064
6065}
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081static void usc_loopback_frame( struct mgsl_struct *info )
6082{
6083 int i;
6084 unsigned long oldmode = info->params.mode;
6085
6086 info->params.mode = MGSL_MODE_HDLC;
6087
6088 usc_DisableMasterIrqBit( info );
6089
6090 usc_set_sdlc_mode( info );
6091 usc_enable_loopback( info, 1 );
6092
6093
6094 usc_OutReg( info, TC0R, 0 );
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110 usc_OutReg( info, CCR, 0x0100 );
6111
6112
6113 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6114 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6115
6116
6117
6118
6119 usc_OutReg( info, TCLR, 2 );
6120 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6121
6122
6123 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6124 outw(0,info->io_base + DATAREG);
6125
6126
6127 usc_TCmd( info, TCmd_SendFrame );
6128 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6129
6130
6131 for (i=0 ; i<1000 ; i++)
6132 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
6133 break;
6134
6135
6136 usc_enable_loopback(info, 0);
6137
6138 usc_EnableMasterIrqBit(info);
6139
6140 info->params.mode = oldmode;
6141
6142}
6143
6144
6145
6146
6147
6148
6149static void usc_set_sync_mode( struct mgsl_struct *info )
6150{
6151 usc_loopback_frame( info );
6152 usc_set_sdlc_mode( info );
6153
6154 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6155
6156
6157 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6158 }
6159
6160 usc_enable_aux_clock(info, info->params.clock_speed);
6161
6162 if (info->params.loopback)
6163 usc_enable_loopback(info,1);
6164
6165}
6166
6167
6168
6169
6170
6171
6172static void usc_set_txidle( struct mgsl_struct *info )
6173{
6174 u16 usc_idle_mode = IDLEMODE_FLAGS;
6175
6176
6177
6178 switch( info->idle_mode ){
6179 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6180 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6181 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6182 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6183 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6184 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6185 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6186 }
6187
6188 info->usc_idle_mode = usc_idle_mode;
6189
6190 info->tcsr_value &= ~IDLEMODE_MASK;
6191 info->tcsr_value += usc_idle_mode;
6192 usc_OutReg(info, TCSR, info->tcsr_value);
6193
6194
6195
6196
6197
6198
6199
6200
6201 if ( info->params.mode == MGSL_MODE_RAW ) {
6202 unsigned char syncpat = 0;
6203 switch( info->idle_mode ) {
6204 case HDLC_TXIDLE_FLAGS:
6205 syncpat = 0x7e;
6206 break;
6207 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6208 syncpat = 0x55;
6209 break;
6210 case HDLC_TXIDLE_ZEROS:
6211 case HDLC_TXIDLE_SPACE:
6212 syncpat = 0x00;
6213 break;
6214 case HDLC_TXIDLE_ONES:
6215 case HDLC_TXIDLE_MARK:
6216 syncpat = 0xff;
6217 break;
6218 case HDLC_TXIDLE_ALT_MARK_SPACE:
6219 syncpat = 0xaa;
6220 break;
6221 }
6222
6223 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6224 }
6225
6226}
6227
6228
6229
6230
6231
6232
6233
6234
6235static void usc_get_serial_signals( struct mgsl_struct *info )
6236{
6237 u16 status;
6238
6239
6240 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
6241
6242
6243
6244
6245 status = usc_InReg( info, MISR );
6246
6247
6248
6249 if ( status & MISCSTATUS_CTS )
6250 info->serial_signals |= SerialSignal_CTS;
6251
6252 if ( status & MISCSTATUS_DCD )
6253 info->serial_signals |= SerialSignal_DCD;
6254
6255 if ( status & MISCSTATUS_RI )
6256 info->serial_signals |= SerialSignal_RI;
6257
6258 if ( status & MISCSTATUS_DSR )
6259 info->serial_signals |= SerialSignal_DSR;
6260
6261}
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271static void usc_set_serial_signals( struct mgsl_struct *info )
6272{
6273 u16 Control;
6274 unsigned char V24Out = info->serial_signals;
6275
6276
6277
6278 Control = usc_InReg( info, PCR );
6279
6280 if ( V24Out & SerialSignal_RTS )
6281 Control &= ~(BIT6);
6282 else
6283 Control |= BIT6;
6284
6285 if ( V24Out & SerialSignal_DTR )
6286 Control &= ~(BIT4);
6287 else
6288 Control |= BIT4;
6289
6290 usc_OutReg( info, PCR, Control );
6291
6292}
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6304{
6305 if ( data_rate ) {
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320 usc_OutReg( info, CMCR, 0x0f64 );
6321
6322
6323
6324
6325
6326
6327
6328
6329 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6330 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6331 else
6332 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6333
6334
6335
6336
6337
6338
6339
6340
6341 usc_OutReg( info, HCR,
6342 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6343
6344
6345
6346
6347 usc_OutReg( info, IOCR,
6348 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6349 } else {
6350
6351 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6352 }
6353
6354}
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6414{
6415 unsigned int i;
6416
6417 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6418 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6419 }
6420
6421 info->current_tx_buffer = 0;
6422 info->start_tx_dma_buffer = 0;
6423 info->tx_dma_buffers_used = 0;
6424
6425 info->get_tx_holding_index = 0;
6426 info->put_tx_holding_index = 0;
6427 info->tx_holding_count = 0;
6428
6429}
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6440{
6441 return info->tx_buffer_count - info->tx_dma_buffers_used;
6442}
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6455{
6456 unsigned int i;
6457
6458 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6459 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6460
6461
6462 }
6463
6464 info->current_rx_buffer = 0;
6465
6466}
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6483{
6484 bool Done = false;
6485 DMABUFFERENTRY *pBufEntry;
6486 unsigned int Index;
6487
6488
6489
6490
6491 Index = StartIndex;
6492
6493 while( !Done ) {
6494 pBufEntry = &(info->rx_buffer_list[Index]);
6495
6496 if ( Index == EndIndex ) {
6497
6498 Done = true;
6499 }
6500
6501
6502
6503
6504 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6505
6506
6507 Index++;
6508 if ( Index == info->rx_buffer_count )
6509 Index = 0;
6510 }
6511
6512
6513 info->current_rx_buffer = Index;
6514
6515}
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6526{
6527 unsigned int StartIndex, EndIndex;
6528 unsigned short status;
6529 DMABUFFERENTRY *pBufEntry;
6530 unsigned int framesize = 0;
6531 bool ReturnCode = false;
6532 unsigned long flags;
6533 struct tty_struct *tty = info->port.tty;
6534 bool return_frame = false;
6535
6536
6537
6538
6539
6540
6541
6542
6543 StartIndex = EndIndex = info->current_rx_buffer;
6544
6545 while( !info->rx_buffer_list[EndIndex].status ) {
6546
6547
6548
6549
6550
6551
6552
6553 if ( info->rx_buffer_list[EndIndex].count )
6554 goto Cleanup;
6555
6556
6557 EndIndex++;
6558 if ( EndIndex == info->rx_buffer_count )
6559 EndIndex = 0;
6560
6561
6562 if ( EndIndex == StartIndex ) {
6563
6564
6565
6566
6567
6568 if ( info->rx_enabled ){
6569 spin_lock_irqsave(&info->irq_spinlock,flags);
6570 usc_start_receiver(info);
6571 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6572 }
6573 goto Cleanup;
6574 }
6575 }
6576
6577
6578
6579
6580 status = info->rx_buffer_list[EndIndex].status;
6581
6582 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6583 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
6584 if ( status & RXSTATUS_SHORT_FRAME )
6585 info->icount.rxshort++;
6586 else if ( status & RXSTATUS_ABORT )
6587 info->icount.rxabort++;
6588 else if ( status & RXSTATUS_OVERRUN )
6589 info->icount.rxover++;
6590 else {
6591 info->icount.rxcrc++;
6592 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6593 return_frame = true;
6594 }
6595 framesize = 0;
6596#if SYNCLINK_GENERIC_HDLC
6597 {
6598 info->netdev->stats.rx_errors++;
6599 info->netdev->stats.rx_frame_errors++;
6600 }
6601#endif
6602 } else
6603 return_frame = true;
6604
6605 if ( return_frame ) {
6606
6607
6608
6609
6610
6611
6612 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6613
6614
6615 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6616 framesize -= 2;
6617 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6618 framesize -= 4;
6619 }
6620
6621 if ( debug_level >= DEBUG_LEVEL_BH )
6622 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6623 __FILE__,__LINE__,info->device_name,status,framesize);
6624
6625 if ( debug_level >= DEBUG_LEVEL_DATA )
6626 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6627 min_t(int, framesize, DMABUFFERSIZE),0);
6628
6629 if (framesize) {
6630 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6631 ((framesize+1) > info->max_frame_size) ) ||
6632 (framesize > info->max_frame_size) )
6633 info->icount.rxlong++;
6634 else {
6635
6636 int copy_count = framesize;
6637 int index = StartIndex;
6638 unsigned char *ptmp = info->intermediate_rxbuffer;
6639
6640 if ( !(status & RXSTATUS_CRC_ERROR))
6641 info->icount.rxok++;
6642
6643 while(copy_count) {
6644 int partial_count;
6645 if ( copy_count > DMABUFFERSIZE )
6646 partial_count = DMABUFFERSIZE;
6647 else
6648 partial_count = copy_count;
6649
6650 pBufEntry = &(info->rx_buffer_list[index]);
6651 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6652 ptmp += partial_count;
6653 copy_count -= partial_count;
6654
6655 if ( ++index == info->rx_buffer_count )
6656 index = 0;
6657 }
6658
6659 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6660 ++framesize;
6661 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6662 RX_CRC_ERROR :
6663 RX_OK);
6664
6665 if ( debug_level >= DEBUG_LEVEL_DATA )
6666 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6667 __FILE__,__LINE__,info->device_name,
6668 *ptmp);
6669 }
6670
6671#if SYNCLINK_GENERIC_HDLC
6672 if (info->netcount)
6673 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6674 else
6675#endif
6676 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6677 }
6678 }
6679
6680 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6681
6682 ReturnCode = true;
6683
6684Cleanup:
6685
6686 if ( info->rx_enabled && info->rx_overflow ) {
6687
6688
6689
6690
6691
6692 if ( !info->rx_buffer_list[EndIndex].status &&
6693 info->rx_buffer_list[EndIndex].count ) {
6694 spin_lock_irqsave(&info->irq_spinlock,flags);
6695 usc_start_receiver(info);
6696 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6697 }
6698 }
6699
6700 return ReturnCode;
6701
6702}
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6724{
6725 unsigned int CurrentIndex, NextIndex;
6726 unsigned short status;
6727 DMABUFFERENTRY *pBufEntry;
6728 unsigned int framesize = 0;
6729 bool ReturnCode = false;
6730 unsigned long flags;
6731 struct tty_struct *tty = info->port.tty;
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748 CurrentIndex = NextIndex = info->current_rx_buffer;
6749 ++NextIndex;
6750 if ( NextIndex == info->rx_buffer_count )
6751 NextIndex = 0;
6752
6753 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6754 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6755 info->rx_buffer_list[NextIndex].count == 0)) {
6756
6757
6758
6759
6760
6761
6762
6763 status = info->rx_buffer_list[CurrentIndex].status;
6764
6765 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6766 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
6767 if ( status & RXSTATUS_SHORT_FRAME )
6768 info->icount.rxshort++;
6769 else if ( status & RXSTATUS_ABORT )
6770 info->icount.rxabort++;
6771 else if ( status & RXSTATUS_OVERRUN )
6772 info->icount.rxover++;
6773 else
6774 info->icount.rxcrc++;
6775 framesize = 0;
6776 } else {
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800 if ( status ) {
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812 if ( info->rx_buffer_list[CurrentIndex].rcc )
6813 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6814 else
6815 framesize = DMABUFFERSIZE;
6816 }
6817 else
6818 framesize = DMABUFFERSIZE;
6819 }
6820
6821 if ( framesize > DMABUFFERSIZE ) {
6822
6823
6824
6825
6826
6827
6828 framesize = framesize % DMABUFFERSIZE;
6829 }
6830
6831
6832 if ( debug_level >= DEBUG_LEVEL_BH )
6833 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6834 __FILE__,__LINE__,info->device_name,status,framesize);
6835
6836 if ( debug_level >= DEBUG_LEVEL_DATA )
6837 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6838 min_t(int, framesize, DMABUFFERSIZE),0);
6839
6840 if (framesize) {
6841
6842
6843
6844 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6845 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6846 info->icount.rxok++;
6847
6848 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6849 }
6850
6851
6852 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6853
6854 ReturnCode = true;
6855 }
6856
6857
6858 if ( info->rx_enabled && info->rx_overflow ) {
6859
6860
6861
6862
6863
6864 if ( !info->rx_buffer_list[CurrentIndex].status &&
6865 info->rx_buffer_list[CurrentIndex].count ) {
6866 spin_lock_irqsave(&info->irq_spinlock,flags);
6867 usc_start_receiver(info);
6868 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6869 }
6870 }
6871
6872 return ReturnCode;
6873
6874}
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6889 const char *Buffer, unsigned int BufferSize)
6890{
6891 unsigned short Copycount;
6892 unsigned int i = 0;
6893 DMABUFFERENTRY *pBufEntry;
6894
6895 if ( debug_level >= DEBUG_LEVEL_DATA )
6896 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6897
6898 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6899
6900
6901
6902 info->cmr_value |= BIT13;
6903 }
6904
6905
6906
6907
6908
6909 i = info->current_tx_buffer;
6910 info->start_tx_dma_buffer = i;
6911
6912
6913
6914
6915 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6916 info->tx_buffer_list[i].rcc = BufferSize;
6917 info->tx_buffer_list[i].count = BufferSize;
6918
6919
6920
6921
6922 while( BufferSize ){
6923
6924 pBufEntry = &info->tx_buffer_list[i++];
6925
6926 if ( i == info->tx_buffer_count )
6927 i=0;
6928
6929
6930
6931 if ( BufferSize > DMABUFFERSIZE )
6932 Copycount = DMABUFFERSIZE;
6933 else
6934 Copycount = BufferSize;
6935
6936
6937
6938 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6939 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6940 else
6941 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6942
6943 pBufEntry->count = Copycount;
6944
6945
6946 Buffer += Copycount;
6947 BufferSize -= Copycount;
6948
6949 ++info->tx_dma_buffers_used;
6950 }
6951
6952
6953 info->current_tx_buffer = i;
6954
6955}
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965static bool mgsl_register_test( struct mgsl_struct *info )
6966{
6967 static unsigned short BitPatterns[] =
6968 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6969 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6970 unsigned int i;
6971 bool rc = true;
6972 unsigned long flags;
6973
6974 spin_lock_irqsave(&info->irq_spinlock,flags);
6975 usc_reset(info);
6976
6977
6978
6979 if ( (usc_InReg( info, SICR ) != 0) ||
6980 (usc_InReg( info, IVR ) != 0) ||
6981 (usc_InDmaReg( info, DIVR ) != 0) ){
6982 rc = false;
6983 }
6984
6985 if ( rc ){
6986
6987
6988
6989 for ( i = 0 ; i < Patterncount ; i++ ) {
6990 usc_OutReg( info, TC0R, BitPatterns[i] );
6991 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6992 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6993 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6994 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6995 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6996
6997 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6998 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6999 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7000 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7001 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7002 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7003 rc = false;
7004 break;
7005 }
7006 }
7007 }
7008
7009 usc_reset(info);
7010 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7011
7012 return rc;
7013
7014}
7015
7016
7017
7018
7019
7020
7021static bool mgsl_irq_test( struct mgsl_struct *info )
7022{
7023 unsigned long EndTime;
7024 unsigned long flags;
7025
7026 spin_lock_irqsave(&info->irq_spinlock,flags);
7027 usc_reset(info);
7028
7029
7030
7031
7032
7033
7034 info->irq_occurred = false;
7035
7036
7037
7038
7039
7040 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7041
7042 usc_EnableMasterIrqBit(info);
7043 usc_EnableInterrupts(info, IO_PIN);
7044 usc_ClearIrqPendingBits(info, IO_PIN);
7045
7046 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7047 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7048
7049 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7050
7051 EndTime=100;
7052 while( EndTime-- && !info->irq_occurred ) {
7053 msleep_interruptible(10);
7054 }
7055
7056 spin_lock_irqsave(&info->irq_spinlock,flags);
7057 usc_reset(info);
7058 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7059
7060 return info->irq_occurred;
7061
7062}
7063
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073static bool mgsl_dma_test( struct mgsl_struct *info )
7074{
7075 unsigned short FifoLevel;
7076 unsigned long phys_addr;
7077 unsigned int FrameSize;
7078 unsigned int i;
7079 char *TmpPtr;
7080 bool rc = true;
7081 unsigned short status=0;
7082 unsigned long EndTime;
7083 unsigned long flags;
7084 MGSL_PARAMS tmp_params;
7085
7086
7087 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7088
7089 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7090
7091#define TESTFRAMESIZE 40
7092
7093 spin_lock_irqsave(&info->irq_spinlock,flags);
7094
7095
7096
7097 usc_reset(info);
7098 usc_set_sdlc_mode(info);
7099 usc_enable_loopback(info,1);
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121 usc_OutDmaReg( info, RDMR, 0xe200 );
7122
7123 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7124
7125
7126
7127
7128 FrameSize = TESTFRAMESIZE;
7129
7130
7131
7132
7133 info->tx_buffer_list[0].count = FrameSize;
7134 info->tx_buffer_list[0].rcc = FrameSize;
7135 info->tx_buffer_list[0].status = 0x4000;
7136
7137
7138
7139 TmpPtr = info->tx_buffer_list[0].virt_addr;
7140 for (i = 0; i < FrameSize; i++ )
7141 *TmpPtr++ = i;
7142
7143
7144
7145
7146 info->rx_buffer_list[0].status = 0;
7147 info->rx_buffer_list[0].count = FrameSize + 4;
7148
7149
7150
7151 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7152
7153
7154
7155
7156 info->tx_buffer_list[1].count = 0;
7157 info->rx_buffer_list[1].count = 0;
7158
7159
7160
7161
7162
7163
7164 spin_lock_irqsave(&info->irq_spinlock,flags);
7165
7166
7167 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7168
7169
7170 phys_addr = info->rx_buffer_list[0].phys_entry;
7171 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7172 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7173
7174
7175 usc_InDmaReg( info, RDMR );
7176 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7177
7178
7179 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7180
7181 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7182
7183
7184
7185
7186
7187
7188
7189 EndTime = jiffies + msecs_to_jiffies(100);
7190
7191 for(;;) {
7192 if (time_after(jiffies, EndTime)) {
7193 rc = false;
7194 break;
7195 }
7196
7197 spin_lock_irqsave(&info->irq_spinlock,flags);
7198 status = usc_InDmaReg( info, RDMR );
7199 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7200
7201 if ( !(status & BIT4) && (status & BIT5) ) {
7202
7203
7204
7205 break;
7206 }
7207 }
7208
7209
7210
7211
7212
7213
7214 spin_lock_irqsave(&info->irq_spinlock,flags);
7215
7216
7217
7218
7219 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7220 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7221
7222
7223
7224 phys_addr = info->tx_buffer_list[0].phys_entry;
7225 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7226 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7227
7228
7229
7230 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7231 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7232
7233
7234
7235 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7236
7237 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7238
7239
7240
7241
7242
7243
7244
7245 EndTime = jiffies + msecs_to_jiffies(100);
7246
7247 for(;;) {
7248 if (time_after(jiffies, EndTime)) {
7249 rc = false;
7250 break;
7251 }
7252
7253 spin_lock_irqsave(&info->irq_spinlock,flags);
7254 FifoLevel = usc_InReg(info, TICR) >> 8;
7255 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7256
7257 if ( FifoLevel < 16 )
7258 break;
7259 else
7260 if ( FrameSize < 32 ) {
7261
7262
7263 if ( FifoLevel <= (32 - FrameSize) )
7264 break;
7265 }
7266 }
7267
7268
7269 if ( rc )
7270 {
7271
7272
7273 spin_lock_irqsave(&info->irq_spinlock,flags);
7274
7275
7276 usc_TCmd( info, TCmd_SendFrame );
7277 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7278
7279 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7280
7281
7282
7283
7284
7285
7286
7287 EndTime = jiffies + msecs_to_jiffies(100);
7288
7289
7290
7291 spin_lock_irqsave(&info->irq_spinlock,flags);
7292 status = usc_InReg( info, TCSR );
7293 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7294
7295 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
7296 if (time_after(jiffies, EndTime)) {
7297 rc = false;
7298 break;
7299 }
7300
7301 spin_lock_irqsave(&info->irq_spinlock,flags);
7302 status = usc_InReg( info, TCSR );
7303 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7304 }
7305 }
7306
7307
7308 if ( rc ){
7309
7310 if ( status & (BIT5 | BIT1) )
7311 rc = false;
7312 }
7313
7314 if ( rc ) {
7315
7316
7317
7318 EndTime = jiffies + msecs_to_jiffies(100);
7319
7320
7321 status=info->rx_buffer_list[0].status;
7322 while ( status == 0 ) {
7323 if (time_after(jiffies, EndTime)) {
7324 rc = false;
7325 break;
7326 }
7327 status=info->rx_buffer_list[0].status;
7328 }
7329 }
7330
7331
7332 if ( rc ) {
7333
7334 status = info->rx_buffer_list[0].status;
7335
7336 if ( status & (BIT8 | BIT3 | BIT1) ) {
7337
7338 rc = false;
7339 } else {
7340 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7341 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7342 rc = false;
7343 }
7344 }
7345 }
7346
7347 spin_lock_irqsave(&info->irq_spinlock,flags);
7348 usc_reset( info );
7349 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7350
7351
7352 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7353
7354 return rc;
7355
7356}
7357
7358
7359
7360
7361
7362
7363
7364
7365static int mgsl_adapter_test( struct mgsl_struct *info )
7366{
7367 if ( debug_level >= DEBUG_LEVEL_INFO )
7368 printk( "%s(%d):Testing device %s\n",
7369 __FILE__,__LINE__,info->device_name );
7370
7371 if ( !mgsl_register_test( info ) ) {
7372 info->init_error = DiagStatus_AddressFailure;
7373 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7374 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7375 return -ENODEV;
7376 }
7377
7378 if ( !mgsl_irq_test( info ) ) {
7379 info->init_error = DiagStatus_IrqFailure;
7380 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7381 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7382 return -ENODEV;
7383 }
7384
7385 if ( !mgsl_dma_test( info ) ) {
7386 info->init_error = DiagStatus_DmaFailure;
7387 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7388 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7389 return -ENODEV;
7390 }
7391
7392 if ( debug_level >= DEBUG_LEVEL_INFO )
7393 printk( "%s(%d):device %s passed diagnostics\n",
7394 __FILE__,__LINE__,info->device_name );
7395
7396 return 0;
7397
7398}
7399
7400
7401
7402
7403
7404
7405
7406
7407static bool mgsl_memory_test( struct mgsl_struct *info )
7408{
7409 static unsigned long BitPatterns[] =
7410 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7411 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7412 unsigned long i;
7413 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7414 unsigned long * TestAddr;
7415
7416 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7417 return true;
7418
7419 TestAddr = (unsigned long *)info->memory_base;
7420
7421
7422
7423 for ( i = 0 ; i < Patterncount ; i++ ) {
7424 *TestAddr = BitPatterns[i];
7425 if ( *TestAddr != BitPatterns[i] )
7426 return false;
7427 }
7428
7429
7430
7431
7432 for ( i = 0 ; i < TestLimit ; i++ ) {
7433 *TestAddr = i * 4;
7434 TestAddr++;
7435 }
7436
7437 TestAddr = (unsigned long *)info->memory_base;
7438
7439 for ( i = 0 ; i < TestLimit ; i++ ) {
7440 if ( *TestAddr != i * 4 )
7441 return false;
7442 TestAddr++;
7443 }
7444
7445 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7446
7447 return true;
7448
7449}
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7489 unsigned short count )
7490{
7491
7492#define PCI_LOAD_INTERVAL 64
7493
7494 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7495 unsigned short Index;
7496 unsigned long Dummy;
7497
7498 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7499 {
7500 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7501 Dummy = *((volatile unsigned long *)TargetPtr);
7502 TargetPtr += PCI_LOAD_INTERVAL;
7503 SourcePtr += PCI_LOAD_INTERVAL;
7504 }
7505
7506 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7507
7508}
7509
7510static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7511{
7512 int i;
7513 int linecount;
7514 if (xmit)
7515 printk("%s tx data:\n",info->device_name);
7516 else
7517 printk("%s rx data:\n",info->device_name);
7518
7519 while(count) {
7520 if (count > 16)
7521 linecount = 16;
7522 else
7523 linecount = count;
7524
7525 for(i=0;i<linecount;i++)
7526 printk("%02X ",(unsigned char)data[i]);
7527 for(;i<17;i++)
7528 printk(" ");
7529 for(i=0;i<linecount;i++) {
7530 if (data[i]>=040 && data[i]<=0176)
7531 printk("%c",data[i]);
7532 else
7533 printk(".");
7534 }
7535 printk("\n");
7536
7537 data += linecount;
7538 count -= linecount;
7539 }
7540}
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550static void mgsl_tx_timeout(unsigned long context)
7551{
7552 struct mgsl_struct *info = (struct mgsl_struct*)context;
7553 unsigned long flags;
7554
7555 if ( debug_level >= DEBUG_LEVEL_INFO )
7556 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7557 __FILE__,__LINE__,info->device_name);
7558 if(info->tx_active &&
7559 (info->params.mode == MGSL_MODE_HDLC ||
7560 info->params.mode == MGSL_MODE_RAW) ) {
7561 info->icount.txtimeout++;
7562 }
7563 spin_lock_irqsave(&info->irq_spinlock,flags);
7564 info->tx_active = false;
7565 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7566
7567 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7568 usc_loopmode_cancel_transmit( info );
7569
7570 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7571
7572#if SYNCLINK_GENERIC_HDLC
7573 if (info->netcount)
7574 hdlcdev_tx_done(info);
7575 else
7576#endif
7577 mgsl_bh_transmit(info);
7578
7579}
7580
7581
7582
7583
7584
7585static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7586{
7587 unsigned long flags;
7588
7589 spin_lock_irqsave(&info->irq_spinlock,flags);
7590 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7591 if (info->tx_active)
7592 info->loopmode_send_done_requested = true;
7593 else
7594 usc_loopmode_send_done(info);
7595 }
7596 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7597
7598 return 0;
7599}
7600
7601
7602
7603
7604static void usc_loopmode_send_done( struct mgsl_struct * info )
7605{
7606 info->loopmode_send_done_requested = false;
7607
7608 info->cmr_value &= ~BIT13;
7609 usc_OutReg(info, CMR, info->cmr_value);
7610}
7611
7612
7613
7614static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7615{
7616
7617 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7618 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7619 usc_loopmode_send_done( info );
7620}
7621
7622
7623
7624
7625
7626static void usc_loopmode_insert_request( struct mgsl_struct * info )
7627{
7628 info->loopmode_insert_requested = true;
7629
7630
7631
7632
7633 usc_OutReg( info, RICR,
7634 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7635
7636
7637 info->cmr_value |= BIT13;
7638 usc_OutReg(info, CMR, info->cmr_value);
7639}
7640
7641
7642
7643static int usc_loopmode_active( struct mgsl_struct * info)
7644{
7645 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7646}
7647
7648#if SYNCLINK_GENERIC_HDLC
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7661 unsigned short parity)
7662{
7663 struct mgsl_struct *info = dev_to_port(dev);
7664 unsigned char new_encoding;
7665 unsigned short new_crctype;
7666
7667
7668 if (info->port.count)
7669 return -EBUSY;
7670
7671 switch (encoding)
7672 {
7673 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7674 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7675 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7676 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7677 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7678 default: return -EINVAL;
7679 }
7680
7681 switch (parity)
7682 {
7683 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7684 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7685 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7686 default: return -EINVAL;
7687 }
7688
7689 info->params.encoding = new_encoding;
7690 info->params.crc_type = new_crctype;
7691
7692
7693 if (info->netcount)
7694 mgsl_program_hw(info);
7695
7696 return 0;
7697}
7698
7699
7700
7701
7702
7703
7704
7705static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7706 struct net_device *dev)
7707{
7708 struct mgsl_struct *info = dev_to_port(dev);
7709 unsigned long flags;
7710
7711 if (debug_level >= DEBUG_LEVEL_INFO)
7712 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7713
7714
7715 netif_stop_queue(dev);
7716
7717
7718 info->xmit_cnt = skb->len;
7719 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7720
7721
7722 dev->stats.tx_packets++;
7723 dev->stats.tx_bytes += skb->len;
7724
7725
7726 dev_kfree_skb(skb);
7727
7728
7729 dev->trans_start = jiffies;
7730
7731
7732 spin_lock_irqsave(&info->irq_spinlock,flags);
7733 if (!info->tx_active)
7734 usc_start_transmitter(info);
7735 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7736
7737 return NETDEV_TX_OK;
7738}
7739
7740
7741
7742
7743
7744
7745
7746
7747
7748static int hdlcdev_open(struct net_device *dev)
7749{
7750 struct mgsl_struct *info = dev_to_port(dev);
7751 int rc;
7752 unsigned long flags;
7753
7754 if (debug_level >= DEBUG_LEVEL_INFO)
7755 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7756
7757
7758 if ((rc = hdlc_open(dev)))
7759 return rc;
7760
7761
7762 spin_lock_irqsave(&info->netlock, flags);
7763 if (info->port.count != 0 || info->netcount != 0) {
7764 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7765 spin_unlock_irqrestore(&info->netlock, flags);
7766 return -EBUSY;
7767 }
7768 info->netcount=1;
7769 spin_unlock_irqrestore(&info->netlock, flags);
7770
7771
7772 if ((rc = startup(info)) != 0) {
7773 spin_lock_irqsave(&info->netlock, flags);
7774 info->netcount=0;
7775 spin_unlock_irqrestore(&info->netlock, flags);
7776 return rc;
7777 }
7778
7779
7780 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
7781 mgsl_program_hw(info);
7782
7783
7784 dev->trans_start = jiffies;
7785 netif_start_queue(dev);
7786
7787
7788 spin_lock_irqsave(&info->irq_spinlock, flags);
7789 usc_get_serial_signals(info);
7790 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7791 if (info->serial_signals & SerialSignal_DCD)
7792 netif_carrier_on(dev);
7793 else
7794 netif_carrier_off(dev);
7795 return 0;
7796}
7797
7798
7799
7800
7801
7802
7803
7804
7805
7806static int hdlcdev_close(struct net_device *dev)
7807{
7808 struct mgsl_struct *info = dev_to_port(dev);
7809 unsigned long flags;
7810
7811 if (debug_level >= DEBUG_LEVEL_INFO)
7812 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7813
7814 netif_stop_queue(dev);
7815
7816
7817 shutdown(info);
7818
7819 hdlc_close(dev);
7820
7821 spin_lock_irqsave(&info->netlock, flags);
7822 info->netcount=0;
7823 spin_unlock_irqrestore(&info->netlock, flags);
7824
7825 return 0;
7826}
7827
7828
7829
7830
7831
7832
7833
7834
7835
7836
7837static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7838{
7839 const size_t size = sizeof(sync_serial_settings);
7840 sync_serial_settings new_line;
7841 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7842 struct mgsl_struct *info = dev_to_port(dev);
7843 unsigned int flags;
7844
7845 if (debug_level >= DEBUG_LEVEL_INFO)
7846 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7847
7848
7849 if (info->port.count)
7850 return -EBUSY;
7851
7852 if (cmd != SIOCWANDEV)
7853 return hdlc_ioctl(dev, ifr, cmd);
7854
7855 switch(ifr->ifr_settings.type) {
7856 case IF_GET_IFACE:
7857
7858 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7859 if (ifr->ifr_settings.size < size) {
7860 ifr->ifr_settings.size = size;
7861 return -ENOBUFS;
7862 }
7863
7864 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7865 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7866 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7867 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7868
7869 switch (flags){
7870 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7871 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7872 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7873 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7874 default: new_line.clock_type = CLOCK_DEFAULT;
7875 }
7876
7877 new_line.clock_rate = info->params.clock_speed;
7878 new_line.loopback = info->params.loopback ? 1:0;
7879
7880 if (copy_to_user(line, &new_line, size))
7881 return -EFAULT;
7882 return 0;
7883
7884 case IF_IFACE_SYNC_SERIAL:
7885
7886 if(!capable(CAP_NET_ADMIN))
7887 return -EPERM;
7888 if (copy_from_user(&new_line, line, size))
7889 return -EFAULT;
7890
7891 switch (new_line.clock_type)
7892 {
7893 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7894 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7895 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7896 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7897 case CLOCK_DEFAULT: flags = info->params.flags &
7898 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7899 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7900 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7901 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7902 default: return -EINVAL;
7903 }
7904
7905 if (new_line.loopback != 0 && new_line.loopback != 1)
7906 return -EINVAL;
7907
7908 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7909 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7910 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7911 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7912 info->params.flags |= flags;
7913
7914 info->params.loopback = new_line.loopback;
7915
7916 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7917 info->params.clock_speed = new_line.clock_rate;
7918 else
7919 info->params.clock_speed = 0;
7920
7921
7922 if (info->netcount)
7923 mgsl_program_hw(info);
7924 return 0;
7925
7926 default:
7927 return hdlc_ioctl(dev, ifr, cmd);
7928 }
7929}
7930
7931
7932
7933
7934
7935
7936static void hdlcdev_tx_timeout(struct net_device *dev)
7937{
7938 struct mgsl_struct *info = dev_to_port(dev);
7939 unsigned long flags;
7940
7941 if (debug_level >= DEBUG_LEVEL_INFO)
7942 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7943
7944 dev->stats.tx_errors++;
7945 dev->stats.tx_aborted_errors++;
7946
7947 spin_lock_irqsave(&info->irq_spinlock,flags);
7948 usc_stop_transmitter(info);
7949 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7950
7951 netif_wake_queue(dev);
7952}
7953
7954
7955
7956
7957
7958
7959
7960static void hdlcdev_tx_done(struct mgsl_struct *info)
7961{
7962 if (netif_queue_stopped(info->netdev))
7963 netif_wake_queue(info->netdev);
7964}
7965
7966
7967
7968
7969
7970
7971
7972
7973
7974static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7975{
7976 struct sk_buff *skb = dev_alloc_skb(size);
7977 struct net_device *dev = info->netdev;
7978
7979 if (debug_level >= DEBUG_LEVEL_INFO)
7980 printk("hdlcdev_rx(%s)\n", dev->name);
7981
7982 if (skb == NULL) {
7983 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7984 dev->name);
7985 dev->stats.rx_dropped++;
7986 return;
7987 }
7988
7989 memcpy(skb_put(skb, size), buf, size);
7990
7991 skb->protocol = hdlc_type_trans(skb, dev);
7992
7993 dev->stats.rx_packets++;
7994 dev->stats.rx_bytes += size;
7995
7996 netif_rx(skb);
7997}
7998
7999static const struct net_device_ops hdlcdev_ops = {
8000 .ndo_open = hdlcdev_open,
8001 .ndo_stop = hdlcdev_close,
8002 .ndo_change_mtu = hdlc_change_mtu,
8003 .ndo_start_xmit = hdlc_start_xmit,
8004 .ndo_do_ioctl = hdlcdev_ioctl,
8005 .ndo_tx_timeout = hdlcdev_tx_timeout,
8006};
8007
8008
8009
8010
8011
8012
8013
8014
8015
8016static int hdlcdev_init(struct mgsl_struct *info)
8017{
8018 int rc;
8019 struct net_device *dev;
8020 hdlc_device *hdlc;
8021
8022
8023
8024 if (!(dev = alloc_hdlcdev(info))) {
8025 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8026 return -ENOMEM;
8027 }
8028
8029
8030 dev->base_addr = info->io_base;
8031 dev->irq = info->irq_level;
8032 dev->dma = info->dma_level;
8033
8034
8035 dev->netdev_ops = &hdlcdev_ops;
8036 dev->watchdog_timeo = 10 * HZ;
8037 dev->tx_queue_len = 50;
8038
8039
8040 hdlc = dev_to_hdlc(dev);
8041 hdlc->attach = hdlcdev_attach;
8042 hdlc->xmit = hdlcdev_xmit;
8043
8044
8045 if ((rc = register_hdlc_device(dev))) {
8046 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8047 free_netdev(dev);
8048 return rc;
8049 }
8050
8051 info->netdev = dev;
8052 return 0;
8053}
8054
8055
8056
8057
8058
8059
8060
8061static void hdlcdev_exit(struct mgsl_struct *info)
8062{
8063 unregister_hdlc_device(info->netdev);
8064 free_netdev(info->netdev);
8065 info->netdev = NULL;
8066}
8067
8068#endif
8069
8070
8071static int synclink_init_one (struct pci_dev *dev,
8072 const struct pci_device_id *ent)
8073{
8074 struct mgsl_struct *info;
8075
8076 if (pci_enable_device(dev)) {
8077 printk("error enabling pci device %p\n", dev);
8078 return -EIO;
8079 }
8080
8081 if (!(info = mgsl_allocate_device())) {
8082 printk("can't allocate device instance data.\n");
8083 return -EIO;
8084 }
8085
8086
8087
8088 info->io_base = pci_resource_start(dev, 2);
8089 info->irq_level = dev->irq;
8090 info->phys_memory_base = pci_resource_start(dev, 3);
8091
8092
8093
8094
8095
8096 info->phys_lcr_base = pci_resource_start(dev, 0);
8097 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8098 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8099
8100 info->bus_type = MGSL_BUS_TYPE_PCI;
8101 info->io_addr_size = 8;
8102 info->irq_flags = IRQF_SHARED;
8103
8104 if (dev->device == 0x0210) {
8105
8106 info->misc_ctrl_value = 0x007c4080;
8107 info->hw_version = 1;
8108 } else {
8109
8110
8111
8112
8113
8114 info->misc_ctrl_value = 0x087e4546;
8115 info->hw_version = 0;
8116 }
8117
8118 mgsl_add_device(info);
8119
8120 return 0;
8121}
8122
8123static void synclink_remove_one (struct pci_dev *dev)
8124{
8125}
8126
8127