LXR linux/include/linux/mtd/onenand

   1/*
   2 *  linux/include/linux/mtd/onenand_regs.h
   3 *
   4 *  OneNAND Register header file
   5 *
   6 *  Copyright (C) 2005-2007 Samsung Electronics
   7 *  Kyungmin Park <kyungmin.park@samsung.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13
  14#ifndef __ONENAND_REG_H
  15#define __ONENAND_REG_H
  16
  17/* Memory Address Map Translation (Word order) */
  18#define ONENAND_MEMORY_MAP(x)           ((x) << 1)
  19
  20/*
  21 * External BufferRAM area
  22 */
  23#define ONENAND_BOOTRAM                 ONENAND_MEMORY_MAP(0x0000)
  24#define ONENAND_DATARAM                 ONENAND_MEMORY_MAP(0x0200)
  25#define ONENAND_SPARERAM                ONENAND_MEMORY_MAP(0x8010)
  26
  27/*
  28 * OneNAND Registers
  29 */
  30#define ONENAND_REG_MANUFACTURER_ID     ONENAND_MEMORY_MAP(0xF000)
  31#define ONENAND_REG_DEVICE_ID           ONENAND_MEMORY_MAP(0xF001)
  32#define ONENAND_REG_VERSION_ID          ONENAND_MEMORY_MAP(0xF002)
  33#define ONENAND_REG_DATA_BUFFER_SIZE    ONENAND_MEMORY_MAP(0xF003)
  34#define ONENAND_REG_BOOT_BUFFER_SIZE    ONENAND_MEMORY_MAP(0xF004)
  35#define ONENAND_REG_NUM_BUFFERS         ONENAND_MEMORY_MAP(0xF005)
  36#define ONENAND_REG_TECHNOLOGY          ONENAND_MEMORY_MAP(0xF006)
  37
  38#define ONENAND_REG_START_ADDRESS1      ONENAND_MEMORY_MAP(0xF100)
  39#define ONENAND_REG_START_ADDRESS2      ONENAND_MEMORY_MAP(0xF101)
  40#define ONENAND_REG_START_ADDRESS3      ONENAND_MEMORY_MAP(0xF102)
  41#define ONENAND_REG_START_ADDRESS4      ONENAND_MEMORY_MAP(0xF103)
  42#define ONENAND_REG_START_ADDRESS5      ONENAND_MEMORY_MAP(0xF104)
  43#define ONENAND_REG_START_ADDRESS6      ONENAND_MEMORY_MAP(0xF105)
  44#define ONENAND_REG_START_ADDRESS7      ONENAND_MEMORY_MAP(0xF106)
  45#define ONENAND_REG_START_ADDRESS8      ONENAND_MEMORY_MAP(0xF107)
  46
  47#define ONENAND_REG_START_BUFFER        ONENAND_MEMORY_MAP(0xF200)
  48#define ONENAND_REG_COMMAND             ONENAND_MEMORY_MAP(0xF220)
  49#define ONENAND_REG_SYS_CFG1            ONENAND_MEMORY_MAP(0xF221)
  50#define ONENAND_REG_SYS_CFG2            ONENAND_MEMORY_MAP(0xF222)
  51#define ONENAND_REG_CTRL_STATUS         ONENAND_MEMORY_MAP(0xF240)
  52#define ONENAND_REG_INTERRUPT           ONENAND_MEMORY_MAP(0xF241)
  53#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
  54#define ONENAND_REG_END_BLOCK_ADDRESS   ONENAND_MEMORY_MAP(0xF24D)
  55#define ONENAND_REG_WP_STATUS           ONENAND_MEMORY_MAP(0xF24E)
  56
  57#define ONENAND_REG_ECC_STATUS          ONENAND_MEMORY_MAP(0xFF00)
  58#define ONENAND_REG_ECC_M0              ONENAND_MEMORY_MAP(0xFF01)
  59#define ONENAND_REG_ECC_S0              ONENAND_MEMORY_MAP(0xFF02)
  60#define ONENAND_REG_ECC_M1              ONENAND_MEMORY_MAP(0xFF03)
  61#define ONENAND_REG_ECC_S1              ONENAND_MEMORY_MAP(0xFF04)
  62#define ONENAND_REG_ECC_M2              ONENAND_MEMORY_MAP(0xFF05)
  63#define ONENAND_REG_ECC_S2              ONENAND_MEMORY_MAP(0xFF06)
  64#define ONENAND_REG_ECC_M3              ONENAND_MEMORY_MAP(0xFF07)
  65#define ONENAND_REG_ECC_S3              ONENAND_MEMORY_MAP(0xFF08)
  66
  67/*
  68 * Device ID Register F001h (R)
  69 */
  70#define DEVICE_IS_FLEXONENAND           (1 << 9)
  71#define FLEXONENAND_PI_MASK             (0x3ff)
  72#define FLEXONENAND_PI_UNLOCK_SHIFT     (14)
  73#define ONENAND_DEVICE_DENSITY_MASK     (0xf)
  74#define ONENAND_DEVICE_DENSITY_SHIFT    (4)
  75#define ONENAND_DEVICE_IS_DDP           (1 << 3)
  76#define ONENAND_DEVICE_IS_DEMUX         (1 << 2)
  77#define ONENAND_DEVICE_VCC_MASK         (0x3)
  78
  79#define ONENAND_DEVICE_DENSITY_512Mb    (0x002)
  80#define ONENAND_DEVICE_DENSITY_1Gb      (0x003)
  81#define ONENAND_DEVICE_DENSITY_2Gb      (0x004)
  82#define ONENAND_DEVICE_DENSITY_4Gb      (0x005)
  83
  84/*
  85 * Version ID Register F002h (R)
  86 */
  87#define ONENAND_VERSION_PROCESS_SHIFT   (8)
  88
  89/*
  90 * Technology Register F006h (R)
  91 */
  92#define ONENAND_TECHNOLOGY_IS_MLC       (1 << 0)
  93
  94/*
  95 * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
  96 */
  97#define ONENAND_DDP_SHIFT               (15)
  98#define ONENAND_DDP_CHIP0               (0)
  99#define ONENAND_DDP_CHIP1               (1 << ONENAND_DDP_SHIFT)
 100
 101/*
 102 * Start Address 8 F107h (R/W)
 103 */
 104/* Note: It's actually 0x3f in case of SLC */
 105#define ONENAND_FPA_MASK                (0x7f)
 106#define ONENAND_FPA_SHIFT               (2)
 107#define ONENAND_FSA_MASK                (0x03)
 108
 109/*
 110 * Start Buffer Register F200h (R/W)
 111 */
 112#define ONENAND_BSA_MASK                (0x03)
 113#define ONENAND_BSA_SHIFT               (8)
 114#define ONENAND_BSA_BOOTRAM             (0 << 2)
 115#define ONENAND_BSA_DATARAM0            (2 << 2)
 116#define ONENAND_BSA_DATARAM1            (3 << 2)
 117/* Note: It's actually 0x03 in case of SLC */
 118#define ONENAND_BSC_MASK                (0x07)
 119
 120/*
 121 * Command Register F220h (R/W)
 122 */
 123#define ONENAND_CMD_READ                (0x00)
 124#define ONENAND_CMD_READOOB             (0x13)
 125#define ONENAND_CMD_PROG                (0x80)
 126#define ONENAND_CMD_PROGOOB             (0x1A)
 127#define ONENAND_CMD_2X_PROG             (0x7D)
 128#define ONENAND_CMD_2X_CACHE_PROG       (0x7F)
 129#define ONENAND_CMD_UNLOCK              (0x23)
 130#define ONENAND_CMD_LOCK                (0x2A)
 131#define ONENAND_CMD_LOCK_TIGHT          (0x2C)
 132#define ONENAND_CMD_UNLOCK_ALL          (0x27)
 133#define ONENAND_CMD_ERASE               (0x94)
 134#define ONENAND_CMD_MULTIBLOCK_ERASE    (0x95)
 135#define ONENAND_CMD_ERASE_VERIFY        (0x71)
 136#define ONENAND_CMD_RESET               (0xF0)
 137#define ONENAND_CMD_OTP_ACCESS          (0x65)
 138#define ONENAND_CMD_READID              (0x90)
 139#define FLEXONENAND_CMD_PI_UPDATE       (0x05)
 140#define FLEXONENAND_CMD_PI_ACCESS       (0x66)
 141#define FLEXONENAND_CMD_RECOVER_LSB     (0x05)
 142
 143/* NOTE: Those are not *REAL* commands */
 144#define ONENAND_CMD_BUFFERRAM           (0x1978)
 145#define FLEXONENAND_CMD_READ_PI         (0x1985)
 146
 147/*
 148 * System Configuration 1 Register F221h (R, R/W)
 149 */
 150#define ONENAND_SYS_CFG1_SYNC_READ      (1 << 15)
 151#define ONENAND_SYS_CFG1_BRL_7          (7 << 12)
 152#define ONENAND_SYS_CFG1_BRL_6          (6 << 12)
 153#define ONENAND_SYS_CFG1_BRL_5          (5 << 12)
 154#define ONENAND_SYS_CFG1_BRL_4          (4 << 12)
 155#define ONENAND_SYS_CFG1_BRL_3          (3 << 12)
 156#define ONENAND_SYS_CFG1_BRL_10         (2 << 12)
 157#define ONENAND_SYS_CFG1_BRL_9          (1 << 12)
 158#define ONENAND_SYS_CFG1_BRL_8          (0 << 12)
 159#define ONENAND_SYS_CFG1_BRL_SHIFT      (12)
 160#define ONENAND_SYS_CFG1_BL_32          (4 << 9)
 161#define ONENAND_SYS_CFG1_BL_16          (3 << 9)
 162#define ONENAND_SYS_CFG1_BL_8           (2 << 9)
 163#define ONENAND_SYS_CFG1_BL_4           (1 << 9)
 164#define ONENAND_SYS_CFG1_BL_CONT        (0 << 9)
 165#define ONENAND_SYS_CFG1_BL_SHIFT       (9)
 166#define ONENAND_SYS_CFG1_NO_ECC         (1 << 8)
 167#define ONENAND_SYS_CFG1_RDY            (1 << 7)
 168#define ONENAND_SYS_CFG1_INT            (1 << 6)
 169#define ONENAND_SYS_CFG1_IOBE           (1 << 5)
 170#define ONENAND_SYS_CFG1_RDY_CONF       (1 << 4)
 171#define ONENAND_SYS_CFG1_VHF            (1 << 3)
 172#define ONENAND_SYS_CFG1_HF             (1 << 2)
 173#define ONENAND_SYS_CFG1_SYNC_WRITE     (1 << 1)
 174
 175/*
 176 * Controller Status Register F240h (R)
 177 */
 178#define ONENAND_CTRL_ONGO               (1 << 15)
 179#define ONENAND_CTRL_LOCK               (1 << 14)
 180#define ONENAND_CTRL_LOAD               (1 << 13)
 181#define ONENAND_CTRL_PROGRAM            (1 << 12)
 182#define ONENAND_CTRL_ERASE              (1 << 11)
 183#define ONENAND_CTRL_ERROR              (1 << 10)
 184#define ONENAND_CTRL_RSTB               (1 << 7)
 185#define ONENAND_CTRL_OTP_L              (1 << 6)
 186#define ONENAND_CTRL_OTP_BL             (1 << 5)
 187
 188/*
 189 * Interrupt Status Register F241h (R)
 190 */
 191#define ONENAND_INT_MASTER              (1 << 15)
 192#define ONENAND_INT_READ                (1 << 7)
 193#define ONENAND_INT_WRITE               (1 << 6)
 194#define ONENAND_INT_ERASE               (1 << 5)
 195#define ONENAND_INT_RESET               (1 << 4)
 196#define ONENAND_INT_CLEAR               (0 << 0)
 197
 198/*
 199 * NAND Flash Write Protection Status Register F24Eh (R)
 200 */
 201#define ONENAND_WP_US                   (1 << 2)
 202#define ONENAND_WP_LS                   (1 << 1)
 203#define ONENAND_WP_LTS                  (1 << 0)
 204
 205/*
 206 * ECC Status Reigser FF00h (R)
 207 */
 208#define ONENAND_ECC_1BIT                (1 << 0)
 209#define ONENAND_ECC_1BIT_ALL            (0x5555)
 210#define ONENAND_ECC_2BIT                (1 << 1)
 211#define ONENAND_ECC_2BIT_ALL            (0xAAAA)
 212#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
 213#define ONENAND_ECC_3BIT                (1 << 2)
 214#define ONENAND_ECC_4BIT                (1 << 3)
 215#define ONENAND_ECC_4BIT_UNCORRECTABLE  (0x1010)
 216
 217/*
 218 * One-Time Programmable (OTP)
 219 */
 220#define FLEXONENAND_OTP_LOCK_OFFSET             (2048)
 221#define ONENAND_OTP_LOCK_OFFSET         (14)
 222
 223#endif  /* __ONENAND_REG_H */
 224