1/* 2 * wm8996.h - WM8996 audio codec interface 3 * 4 * Copyright 2011 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13#ifndef _WM8996_H 14#define _WM8996_H 15 16#define WM8996_SYSCLK_MCLK1 1 17#define WM8996_SYSCLK_MCLK2 2 18#define WM8996_SYSCLK_FLL 3 19 20#define WM8996_FLL_MCLK1 1 21#define WM8996_FLL_MCLK2 2 22#define WM8996_FLL_DACLRCLK1 3 23#define WM8996_FLL_BCLK1 4 24 25typedef void (*wm8996_polarity_fn)(struct snd_soc_codec *codec, int polarity); 26 27int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 28 wm8996_polarity_fn polarity_cb); 29 30/* 31 * Register values. 32 */ 33#define WM8996_SOFTWARE_RESET 0x00 34#define WM8996_POWER_MANAGEMENT_1 0x01 35#define WM8996_POWER_MANAGEMENT_2 0x02 36#define WM8996_POWER_MANAGEMENT_3 0x03 37#define WM8996_POWER_MANAGEMENT_4 0x04 38#define WM8996_POWER_MANAGEMENT_5 0x05 39#define WM8996_POWER_MANAGEMENT_6 0x06 40#define WM8996_POWER_MANAGEMENT_7 0x07 41#define WM8996_POWER_MANAGEMENT_8 0x08 42#define WM8996_LEFT_LINE_INPUT_VOLUME 0x10 43#define WM8996_RIGHT_LINE_INPUT_VOLUME 0x11 44#define WM8996_LINE_INPUT_CONTROL 0x12 45#define WM8996_DAC1_HPOUT1_VOLUME 0x15 46#define WM8996_DAC2_HPOUT2_VOLUME 0x16 47#define WM8996_DAC1_LEFT_VOLUME 0x18 48#define WM8996_DAC1_RIGHT_VOLUME 0x19 49#define WM8996_DAC2_LEFT_VOLUME 0x1A 50#define WM8996_DAC2_RIGHT_VOLUME 0x1B 51#define WM8996_OUTPUT1_LEFT_VOLUME 0x1C 52#define WM8996_OUTPUT1_RIGHT_VOLUME 0x1D 53#define WM8996_OUTPUT2_LEFT_VOLUME 0x1E 54#define WM8996_OUTPUT2_RIGHT_VOLUME 0x1F 55#define WM8996_MICBIAS_1 0x20 56#define WM8996_MICBIAS_2 0x21 57#define WM8996_LDO_1 0x28 58#define WM8996_LDO_2 0x29 59#define WM8996_ACCESSORY_DETECT_MODE_1 0x30 60#define WM8996_ACCESSORY_DETECT_MODE_2 0x31 61#define WM8996_HEADPHONE_DETECT_1 0x34 62#define WM8996_HEADPHONE_DETECT_2 0x35 63#define WM8996_MIC_DETECT_1 0x38 64#define WM8996_MIC_DETECT_2 0x39 65#define WM8996_MIC_DETECT_3 0x3A 66#define WM8996_CHARGE_PUMP_1 0x40 67#define WM8996_CHARGE_PUMP_2 0x41 68#define WM8996_DC_SERVO_1 0x50 69#define WM8996_DC_SERVO_2 0x51 70#define WM8996_DC_SERVO_3 0x52 71#define WM8996_DC_SERVO_5 0x54 72#define WM8996_DC_SERVO_6 0x55 73#define WM8996_DC_SERVO_7 0x56 74#define WM8996_DC_SERVO_READBACK_0 0x57 75#define WM8996_ANALOGUE_HP_1 0x60 76#define WM8996_ANALOGUE_HP_2 0x61 77#define WM8996_CHIP_REVISION 0x100 78#define WM8996_CONTROL_INTERFACE_1 0x101 79#define WM8996_WRITE_SEQUENCER_CTRL_1 0x110 80#define WM8996_WRITE_SEQUENCER_CTRL_2 0x111 81#define WM8996_AIF_CLOCKING_1 0x200 82#define WM8996_AIF_CLOCKING_2 0x201 83#define WM8996_CLOCKING_1 0x208 84#define WM8996_CLOCKING_2 0x209 85#define WM8996_AIF_RATE 0x210 86#define WM8996_FLL_CONTROL_1 0x220 87#define WM8996_FLL_CONTROL_2 0x221 88#define WM8996_FLL_CONTROL_3 0x222 89#define WM8996_FLL_CONTROL_4 0x223 90#define WM8996_FLL_CONTROL_5 0x224 91#define WM8996_FLL_CONTROL_6 0x225 92#define WM8996_FLL_EFS_1 0x226 93#define WM8996_FLL_EFS_2 0x227 94#define WM8996_AIF1_CONTROL 0x300 95#define WM8996_AIF1_BCLK 0x301 96#define WM8996_AIF1_TX_LRCLK_1 0x302 97#define WM8996_AIF1_TX_LRCLK_2 0x303 98#define WM8996_AIF1_RX_LRCLK_1 0x304 99#define WM8996_AIF1_RX_LRCLK_2 0x305 100#define WM8996_AIF1TX_DATA_CONFIGURATION_1 0x306 101#define WM8996_AIF1TX_DATA_CONFIGURATION_2 0x307 102#define WM8996_AIF1RX_DATA_CONFIGURATION 0x308 103#define WM8996_AIF1TX_CHANNEL_0_CONFIGURATION 0x309 104#define WM8996_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A 105#define WM8996_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B 106#define WM8996_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C 107#define WM8996_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D 108#define WM8996_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E 109#define WM8996_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F 110#define WM8996_AIF1RX_CHANNEL_1_CONFIGURATION 0x310 111#define WM8996_AIF1RX_CHANNEL_2_CONFIGURATION 0x311 112#define WM8996_AIF1RX_CHANNEL_3_CONFIGURATION 0x312 113#define WM8996_AIF1RX_CHANNEL_4_CONFIGURATION 0x313 114#define WM8996_AIF1RX_CHANNEL_5_CONFIGURATION 0x314 115#define WM8996_AIF1RX_MONO_CONFIGURATION 0x315 116#define WM8996_AIF1TX_TEST 0x31A 117#define WM8996_AIF2_CONTROL 0x320 118#define WM8996_AIF2_BCLK 0x321 119#define WM8996_AIF2_TX_LRCLK_1 0x322 120#define WM8996_AIF2_TX_LRCLK_2 0x323 121#define WM8996_AIF2_RX_LRCLK_1 0x324 122#define WM8996_AIF2_RX_LRCLK_2 0x325 123#define WM8996_AIF2TX_DATA_CONFIGURATION_1 0x326 124#define WM8996_AIF2TX_DATA_CONFIGURATION_2 0x327 125#define WM8996_AIF2RX_DATA_CONFIGURATION 0x328 126#define WM8996_AIF2TX_CHANNEL_0_CONFIGURATION 0x329 127#define WM8996_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A 128#define WM8996_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B 129#define WM8996_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C 130#define WM8996_AIF2RX_MONO_CONFIGURATION 0x32D 131#define WM8996_AIF2TX_TEST 0x32F 132#define WM8996_DSP1_TX_LEFT_VOLUME 0x400 133#define WM8996_DSP1_TX_RIGHT_VOLUME 0x401 134#define WM8996_DSP1_RX_LEFT_VOLUME 0x402 135#define WM8996_DSP1_RX_RIGHT_VOLUME 0x403 136#define WM8996_DSP1_TX_FILTERS 0x410 137#define WM8996_DSP1_RX_FILTERS_1 0x420 138#define WM8996_DSP1_RX_FILTERS_2 0x421 139#define WM8996_DSP1_DRC_1 0x440 140#define WM8996_DSP1_DRC_2 0x441 141#define WM8996_DSP1_DRC_3 0x442 142#define WM8996_DSP1_DRC_4 0x443 143#define WM8996_DSP1_DRC_5 0x444 144#define WM8996_DSP1_RX_EQ_GAINS_1 0x480 145#define WM8996_DSP1_RX_EQ_GAINS_2 0x481 146#define WM8996_DSP1_RX_EQ_BAND_1_A 0x482 147#define WM8996_DSP1_RX_EQ_BAND_1_B 0x483 148#define WM8996_DSP1_RX_EQ_BAND_1_PG 0x484 149#define WM8996_DSP1_RX_EQ_BAND_2_A 0x485 150#define WM8996_DSP1_RX_EQ_BAND_2_B 0x486 151#define WM8996_DSP1_RX_EQ_BAND_2_C 0x487 152#define WM8996_DSP1_RX_EQ_BAND_2_PG 0x488 153#define WM8996_DSP1_RX_EQ_BAND_3_A 0x489 154#define WM8996_DSP1_RX_EQ_BAND_3_B 0x48A 155#define WM8996_DSP1_RX_EQ_BAND_3_C 0x48B 156#define WM8996_DSP1_RX_EQ_BAND_3_PG 0x48C 157#define WM8996_DSP1_RX_EQ_BAND_4_A 0x48D 158#define WM8996_DSP1_RX_EQ_BAND_4_B 0x48E 159#define WM8996_DSP1_RX_EQ_BAND_4_C 0x48F 160#define WM8996_DSP1_RX_EQ_BAND_4_PG 0x490 161#define WM8996_DSP1_RX_EQ_BAND_5_A 0x491 162#define WM8996_DSP1_RX_EQ_BAND_5_B 0x492 163#define WM8996_DSP1_RX_EQ_BAND_5_PG 0x493 164#define WM8996_DSP2_TX_LEFT_VOLUME 0x500 165#define WM8996_DSP2_TX_RIGHT_VOLUME 0x501 166#define WM8996_DSP2_RX_LEFT_VOLUME 0x502 167#define WM8996_DSP2_RX_RIGHT_VOLUME 0x503 168#define WM8996_DSP2_TX_FILTERS 0x510 169#define WM8996_DSP2_RX_FILTERS_1 0x520 170#define WM8996_DSP2_RX_FILTERS_2 0x521 171#define WM8996_DSP2_DRC_1 0x540 172#define WM8996_DSP2_DRC_2 0x541 173#define WM8996_DSP2_DRC_3 0x542 174#define WM8996_DSP2_DRC_4 0x543 175#define WM8996_DSP2_DRC_5 0x544 176#define WM8996_DSP2_RX_EQ_GAINS_1 0x580 177#define WM8996_DSP2_RX_EQ_GAINS_2 0x581 178#define WM8996_DSP2_RX_EQ_BAND_1_A 0x582 179#define WM8996_DSP2_RX_EQ_BAND_1_B 0x583 180#define WM8996_DSP2_RX_EQ_BAND_1_PG 0x584 181#define WM8996_DSP2_RX_EQ_BAND_2_A 0x585 182#define WM8996_DSP2_RX_EQ_BAND_2_B 0x586 183#define WM8996_DSP2_RX_EQ_BAND_2_C 0x587 184#define WM8996_DSP2_RX_EQ_BAND_2_PG 0x588 185#define WM8996_DSP2_RX_EQ_BAND_3_A 0x589 186#define WM8996_DSP2_RX_EQ_BAND_3_B 0x58A 187#define WM8996_DSP2_RX_EQ_BAND_3_C 0x58B 188#define WM8996_DSP2_RX_EQ_BAND_3_PG 0x58C 189#define WM8996_DSP2_RX_EQ_BAND_4_A 0x58D 190#define WM8996_DSP2_RX_EQ_BAND_4_B 0x58E 191#define WM8996_DSP2_RX_EQ_BAND_4_C 0x58F 192#define WM8996_DSP2_RX_EQ_BAND_4_PG 0x590 193#define WM8996_DSP2_RX_EQ_BAND_5_A 0x591 194#define WM8996_DSP2_RX_EQ_BAND_5_B 0x592 195#define WM8996_DSP2_RX_EQ_BAND_5_PG 0x593 196#define WM8996_DAC1_MIXER_VOLUMES 0x600 197#define WM8996_DAC1_LEFT_MIXER_ROUTING 0x601 198#define WM8996_DAC1_RIGHT_MIXER_ROUTING 0x602 199#define WM8996_DAC2_MIXER_VOLUMES 0x603 200#define WM8996_DAC2_LEFT_MIXER_ROUTING 0x604 201#define WM8996_DAC2_RIGHT_MIXER_ROUTING 0x605 202#define WM8996_DSP1_TX_LEFT_MIXER_ROUTING 0x606 203#define WM8996_DSP1_TX_RIGHT_MIXER_ROUTING 0x607 204#define WM8996_DSP2_TX_LEFT_MIXER_ROUTING 0x608 205#define WM8996_DSP2_TX_RIGHT_MIXER_ROUTING 0x609 206#define WM8996_DSP_TX_MIXER_SELECT 0x60A 207#define WM8996_DAC_SOFTMUTE 0x610 208#define WM8996_OVERSAMPLING 0x620 209#define WM8996_SIDETONE 0x621 210#define WM8996_GPIO_1 0x700 211#define WM8996_GPIO_2 0x701 212#define WM8996_GPIO_3 0x702 213#define WM8996_GPIO_4 0x703 214#define WM8996_GPIO_5 0x704 215#define WM8996_PULL_CONTROL_1 0x720 216#define WM8996_PULL_CONTROL_2 0x721 217#define WM8996_INTERRUPT_STATUS_1 0x730 218#define WM8996_INTERRUPT_STATUS_2 0x731 219#define WM8996_INTERRUPT_RAW_STATUS_2 0x732 220#define WM8996_INTERRUPT_STATUS_1_MASK 0x738 221#define WM8996_INTERRUPT_STATUS_2_MASK 0x739 222#define WM8996_INTERRUPT_CONTROL 0x740 223#define WM8996_LEFT_PDM_SPEAKER 0x800 224#define WM8996_RIGHT_PDM_SPEAKER 0x801 225#define WM8996_PDM_SPEAKER_MUTE_SEQUENCE 0x802 226#define WM8996_PDM_SPEAKER_VOLUME 0x803 227#define WM8996_WRITE_SEQUENCER_0 0x3000 228#define WM8996_WRITE_SEQUENCER_1 0x3001 229#define WM8996_WRITE_SEQUENCER_2 0x3002 230#define WM8996_WRITE_SEQUENCER_3 0x3003 231#define WM8996_WRITE_SEQUENCER_4 0x3004 232#define WM8996_WRITE_SEQUENCER_5 0x3005 233#define WM8996_WRITE_SEQUENCER_6 0x3006 234#define WM8996_WRITE_SEQUENCER_7 0x3007 235#define WM8996_WRITE_SEQUENCER_8 0x3008 236#define WM8996_WRITE_SEQUENCER_9 0x3009 237#define WM8996_WRITE_SEQUENCER_10 0x300A 238#define WM8996_WRITE_SEQUENCER_11 0x300B 239#define WM8996_WRITE_SEQUENCER_12 0x300C 240#define WM8996_WRITE_SEQUENCER_13 0x300D 241#define WM8996_WRITE_SEQUENCER_14 0x300E 242#define WM8996_WRITE_SEQUENCER_15 0x300F 243#define WM8996_WRITE_SEQUENCER_16 0x3010 244#define WM8996_WRITE_SEQUENCER_17 0x3011 245#define WM8996_WRITE_SEQUENCER_18 0x3012 246#define WM8996_WRITE_SEQUENCER_19 0x3013 247#define WM8996_WRITE_SEQUENCER_20 0x3014 248#define WM8996_WRITE_SEQUENCER_21 0x3015 249#define WM8996_WRITE_SEQUENCER_22 0x3016 250#define WM8996_WRITE_SEQUENCER_23 0x3017 251#define WM8996_WRITE_SEQUENCER_24 0x3018 252#define WM8996_WRITE_SEQUENCER_25 0x3019 253#define WM8996_WRITE_SEQUENCER_26 0x301A 254#define WM8996_WRITE_SEQUENCER_27 0x301B 255#define WM8996_WRITE_SEQUENCER_28 0x301C 256#define WM8996_WRITE_SEQUENCER_29 0x301D 257#define WM8996_WRITE_SEQUENCER_30 0x301E 258#define WM8996_WRITE_SEQUENCER_31 0x301F 259#define WM8996_WRITE_SEQUENCER_32 0x3020 260#define WM8996_WRITE_SEQUENCER_33 0x3021 261#define WM8996_WRITE_SEQUENCER_34 0x3022 262#define WM8996_WRITE_SEQUENCER_35 0x3023 263#define WM8996_WRITE_SEQUENCER_36 0x3024 264#define WM8996_WRITE_SEQUENCER_37 0x3025 265#define WM8996_WRITE_SEQUENCER_38 0x3026 266#define WM8996_WRITE_SEQUENCER_39 0x3027 267#define WM8996_WRITE_SEQUENCER_40 0x3028 268#define WM8996_WRITE_SEQUENCER_41 0x3029 269#define WM8996_WRITE_SEQUENCER_42 0x302A 270#define WM8996_WRITE_SEQUENCER_43 0x302B 271#define WM8996_WRITE_SEQUENCER_44 0x302C 272#define WM8996_WRITE_SEQUENCER_45 0x302D 273#define WM8996_WRITE_SEQUENCER_46 0x302E 274#define WM8996_WRITE_SEQUENCER_47 0x302F 275#define WM8996_WRITE_SEQUENCER_48 0x3030 276#define WM8996_WRITE_SEQUENCER_49 0x3031 277#define WM8996_WRITE_SEQUENCER_50 0x3032 278#define WM8996_WRITE_SEQUENCER_51 0x3033 279#define WM8996_WRITE_SEQUENCER_52 0x3034 280#define WM8996_WRITE_SEQUENCER_53 0x3035 281#define WM8996_WRITE_SEQUENCER_54 0x3036 282#define WM8996_WRITE_SEQUENCER_55 0x3037 283#define WM8996_WRITE_SEQUENCER_56 0x3038 284#define WM8996_WRITE_SEQUENCER_57 0x3039 285#define WM8996_WRITE_SEQUENCER_58 0x303A 286#define WM8996_WRITE_SEQUENCER_59 0x303B 287#define WM8996_WRITE_SEQUENCER_60 0x303C 288#define WM8996_WRITE_SEQUENCER_61 0x303D 289#define WM8996_WRITE_SEQUENCER_62 0x303E 290#define WM8996_WRITE_SEQUENCER_63 0x303F 291#define WM8996_WRITE_SEQUENCER_64 0x3040 292#define WM8996_WRITE_SEQUENCER_65 0x3041 293#define WM8996_WRITE_SEQUENCER_66 0x3042 294#define WM8996_WRITE_SEQUENCER_67 0x3043 295#define WM8996_WRITE_SEQUENCER_68 0x3044 296#define WM8996_WRITE_SEQUENCER_69 0x3045 297#define WM8996_WRITE_SEQUENCER_70 0x3046 298#define WM8996_WRITE_SEQUENCER_71 0x3047 299#define WM8996_WRITE_SEQUENCER_72 0x3048 300#define WM8996_WRITE_SEQUENCER_73 0x3049 301#define WM8996_WRITE_SEQUENCER_74 0x304A 302#define WM8996_WRITE_SEQUENCER_75 0x304B 303#define WM8996_WRITE_SEQUENCER_76 0x304C 304#define WM8996_WRITE_SEQUENCER_77 0x304D 305#define WM8996_WRITE_SEQUENCER_78 0x304E 306#define WM8996_WRITE_SEQUENCER_79 0x304F 307#define WM8996_WRITE_SEQUENCER_80 0x3050 308#define WM8996_WRITE_SEQUENCER_81 0x3051 309#define WM8996_WRITE_SEQUENCER_82 0x3052 310#define WM8996_WRITE_SEQUENCER_83 0x3053 311#define WM8996_WRITE_SEQUENCER_84 0x3054 312#define WM8996_WRITE_SEQUENCER_85 0x3055 313#define WM8996_WRITE_SEQUENCER_86 0x3056 314#define WM8996_WRITE_SEQUENCER_87 0x3057 315#define WM8996_WRITE_SEQUENCER_88 0x3058 316#define WM8996_WRITE_SEQUENCER_89 0x3059 317#define WM8996_WRITE_SEQUENCER_90 0x305A 318#define WM8996_WRITE_SEQUENCER_91 0x305B 319#define WM8996_WRITE_SEQUENCER_92 0x305C 320#define WM8996_WRITE_SEQUENCER_93 0x305D 321#define WM8996_WRITE_SEQUENCER_94 0x305E 322#define WM8996_WRITE_SEQUENCER_95 0x305F 323#define WM8996_WRITE_SEQUENCER_96 0x3060 324#define WM8996_WRITE_SEQUENCER_97 0x3061 325#define WM8996_WRITE_SEQUENCER_98 0x3062 326#define WM8996_WRITE_SEQUENCER_99 0x3063 327#define WM8996_WRITE_SEQUENCER_100 0x3064 328#define WM8996_WRITE_SEQUENCER_101 0x3065 329#define WM8996_WRITE_SEQUENCER_102 0x3066 330#define WM8996_WRITE_SEQUENCER_103 0x3067 331#define WM8996_WRITE_SEQUENCER_104 0x3068 332#define WM8996_WRITE_SEQUENCER_105 0x3069 333#define WM8996_WRITE_SEQUENCER_106 0x306A 334#define WM8996_WRITE_SEQUENCER_107 0x306B 335#define WM8996_WRITE_SEQUENCER_108 0x306C 336#define WM8996_WRITE_SEQUENCER_109 0x306D 337#define WM8996_WRITE_SEQUENCER_110 0x306E 338#define WM8996_WRITE_SEQUENCER_111 0x306F 339#define WM8996_WRITE_SEQUENCER_112 0x3070 340#define WM8996_WRITE_SEQUENCER_113 0x3071 341#define WM8996_WRITE_SEQUENCER_114 0x3072 342#define WM8996_WRITE_SEQUENCER_115 0x3073 343#define WM8996_WRITE_SEQUENCER_116 0x3074 344#define WM8996_WRITE_SEQUENCER_117 0x3075 345#define WM8996_WRITE_SEQUENCER_118 0x3076 346#define WM8996_WRITE_SEQUENCER_119 0x3077 347#define WM8996_WRITE_SEQUENCER_120 0x3078 348#define WM8996_WRITE_SEQUENCER_121 0x3079 349#define WM8996_WRITE_SEQUENCER_122 0x307A 350#define WM8996_WRITE_SEQUENCER_123 0x307B 351#define WM8996_WRITE_SEQUENCER_124 0x307C 352#define WM8996_WRITE_SEQUENCER_125 0x307D 353#define WM8996_WRITE_SEQUENCER_126 0x307E 354#define WM8996_WRITE_SEQUENCER_127 0x307F 355#define WM8996_WRITE_SEQUENCER_128 0x3080 356#define WM8996_WRITE_SEQUENCER_129 0x3081 357#define WM8996_WRITE_SEQUENCER_130 0x3082 358#define WM8996_WRITE_SEQUENCER_131 0x3083 359#define WM8996_WRITE_SEQUENCER_132 0x3084 360#define WM8996_WRITE_SEQUENCER_133 0x3085 361#define WM8996_WRITE_SEQUENCER_134 0x3086 362#define WM8996_WRITE_SEQUENCER_135 0x3087 363#define WM8996_WRITE_SEQUENCER_136 0x3088 364#define WM8996_WRITE_SEQUENCER_137 0x3089 365#define WM8996_WRITE_SEQUENCER_138 0x308A 366#define WM8996_WRITE_SEQUENCER_139 0x308B 367#define WM8996_WRITE_SEQUENCER_140 0x308C 368#define WM8996_WRITE_SEQUENCER_141 0x308D 369#define WM8996_WRITE_SEQUENCER_142 0x308E 370#define WM8996_WRITE_SEQUENCER_143 0x308F 371#define WM8996_WRITE_SEQUENCER_144 0x3090 372#define WM8996_WRITE_SEQUENCER_145 0x3091 373#define WM8996_WRITE_SEQUENCER_146 0x3092 374#define WM8996_WRITE_SEQUENCER_147 0x3093 375#define WM8996_WRITE_SEQUENCER_148 0x3094 376#define WM8996_WRITE_SEQUENCER_149 0x3095 377#define WM8996_WRITE_SEQUENCER_150 0x3096 378#define WM8996_WRITE_SEQUENCER_151 0x3097 379#define WM8996_WRITE_SEQUENCER_152 0x3098 380#define WM8996_WRITE_SEQUENCER_153 0x3099 381#define WM8996_WRITE_SEQUENCER_154 0x309A 382#define WM8996_WRITE_SEQUENCER_155 0x309B 383#define WM8996_WRITE_SEQUENCER_156 0x309C 384#define WM8996_WRITE_SEQUENCER_157 0x309D 385#define WM8996_WRITE_SEQUENCER_158 0x309E 386#define WM8996_WRITE_SEQUENCER_159 0x309F 387#define WM8996_WRITE_SEQUENCER_160 0x30A0 388#define WM8996_WRITE_SEQUENCER_161 0x30A1 389#define WM8996_WRITE_SEQUENCER_162 0x30A2 390#define WM8996_WRITE_SEQUENCER_163 0x30A3 391#define WM8996_WRITE_SEQUENCER_164 0x30A4 392#define WM8996_WRITE_SEQUENCER_165 0x30A5 393#define WM8996_WRITE_SEQUENCER_166 0x30A6 394#define WM8996_WRITE_SEQUENCER_167 0x30A7 395#define WM8996_WRITE_SEQUENCER_168 0x30A8 396#define WM8996_WRITE_SEQUENCER_169 0x30A9 397#define WM8996_WRITE_SEQUENCER_170 0x30AA 398#define WM8996_WRITE_SEQUENCER_171 0x30AB 399#define WM8996_WRITE_SEQUENCER_172 0x30AC 400#define WM8996_WRITE_SEQUENCER_173 0x30AD 401#define WM8996_WRITE_SEQUENCER_174 0x30AE 402#define WM8996_WRITE_SEQUENCER_175 0x30AF 403#define WM8996_WRITE_SEQUENCER_176 0x30B0 404#define WM8996_WRITE_SEQUENCER_177 0x30B1 405#define WM8996_WRITE_SEQUENCER_178 0x30B2 406#define WM8996_WRITE_SEQUENCER_179 0x30B3 407#define WM8996_WRITE_SEQUENCER_180 0x30B4 408#define WM8996_WRITE_SEQUENCER_181 0x30B5 409#define WM8996_WRITE_SEQUENCER_182 0x30B6 410#define WM8996_WRITE_SEQUENCER_183 0x30B7 411#define WM8996_WRITE_SEQUENCER_184 0x30B8 412#define WM8996_WRITE_SEQUENCER_185 0x30B9 413#define WM8996_WRITE_SEQUENCER_186 0x30BA 414#define WM8996_WRITE_SEQUENCER_187 0x30BB 415#define WM8996_WRITE_SEQUENCER_188 0x30BC 416#define WM8996_WRITE_SEQUENCER_189 0x30BD 417#define WM8996_WRITE_SEQUENCER_190 0x30BE 418#define WM8996_WRITE_SEQUENCER_191 0x30BF 419#define WM8996_WRITE_SEQUENCER_192 0x30C0 420#define WM8996_WRITE_SEQUENCER_193 0x30C1 421#define WM8996_WRITE_SEQUENCER_194 0x30C2 422#define WM8996_WRITE_SEQUENCER_195 0x30C3 423#define WM8996_WRITE_SEQUENCER_196 0x30C4 424#define WM8996_WRITE_SEQUENCER_197 0x30C5 425#define WM8996_WRITE_SEQUENCER_198 0x30C6 426#define WM8996_WRITE_SEQUENCER_199 0x30C7 427#define WM8996_WRITE_SEQUENCER_200 0x30C8 428#define WM8996_WRITE_SEQUENCER_201 0x30C9 429#define WM8996_WRITE_SEQUENCER_202 0x30CA 430#define WM8996_WRITE_SEQUENCER_203 0x30CB 431#define WM8996_WRITE_SEQUENCER_204 0x30CC 432#define WM8996_WRITE_SEQUENCER_205 0x30CD 433#define WM8996_WRITE_SEQUENCER_206 0x30CE 434#define WM8996_WRITE_SEQUENCER_207 0x30CF 435#define WM8996_WRITE_SEQUENCER_208 0x30D0 436#define WM8996_WRITE_SEQUENCER_209 0x30D1 437#define WM8996_WRITE_SEQUENCER_210 0x30D2 438#define WM8996_WRITE_SEQUENCER_211 0x30D3 439#define WM8996_WRITE_SEQUENCER_212 0x30D4 440#define WM8996_WRITE_SEQUENCER_213 0x30D5 441#define WM8996_WRITE_SEQUENCER_214 0x30D6 442#define WM8996_WRITE_SEQUENCER_215 0x30D7 443#define WM8996_WRITE_SEQUENCER_216 0x30D8 444#define WM8996_WRITE_SEQUENCER_217 0x30D9 445#define WM8996_WRITE_SEQUENCER_218 0x30DA 446#define WM8996_WRITE_SEQUENCER_219 0x30DB 447#define WM8996_WRITE_SEQUENCER_220 0x30DC 448#define WM8996_WRITE_SEQUENCER_221 0x30DD 449#define WM8996_WRITE_SEQUENCER_222 0x30DE 450#define WM8996_WRITE_SEQUENCER_223 0x30DF 451#define WM8996_WRITE_SEQUENCER_224 0x30E0 452#define WM8996_WRITE_SEQUENCER_225 0x30E1 453#define WM8996_WRITE_SEQUENCER_226 0x30E2 454#define WM8996_WRITE_SEQUENCER_227 0x30E3 455#define WM8996_WRITE_SEQUENCER_228 0x30E4 456#define WM8996_WRITE_SEQUENCER_229 0x30E5 457#define WM8996_WRITE_SEQUENCER_230 0x30E6 458#define WM8996_WRITE_SEQUENCER_231 0x30E7 459#define WM8996_WRITE_SEQUENCER_232 0x30E8 460#define WM8996_WRITE_SEQUENCER_233 0x30E9 461#define WM8996_WRITE_SEQUENCER_234 0x30EA 462#define WM8996_WRITE_SEQUENCER_235 0x30EB 463#define WM8996_WRITE_SEQUENCER_236 0x30EC 464#define WM8996_WRITE_SEQUENCER_237 0x30ED 465#define WM8996_WRITE_SEQUENCER_238 0x30EE 466#define WM8996_WRITE_SEQUENCER_239 0x30EF 467#define WM8996_WRITE_SEQUENCER_240 0x30F0 468#define WM8996_WRITE_SEQUENCER_241 0x30F1 469#define WM8996_WRITE_SEQUENCER_242 0x30F2 470#define WM8996_WRITE_SEQUENCER_243 0x30F3 471#define WM8996_WRITE_SEQUENCER_244 0x30F4 472#define WM8996_WRITE_SEQUENCER_245 0x30F5 473#define WM8996_WRITE_SEQUENCER_246 0x30F6 474#define WM8996_WRITE_SEQUENCER_247 0x30F7 475#define WM8996_WRITE_SEQUENCER_248 0x30F8 476#define WM8996_WRITE_SEQUENCER_249 0x30F9 477#define WM8996_WRITE_SEQUENCER_250 0x30FA 478#define WM8996_WRITE_SEQUENCER_251 0x30FB 479#define WM8996_WRITE_SEQUENCER_252 0x30FC 480#define WM8996_WRITE_SEQUENCER_253 0x30FD 481#define WM8996_WRITE_SEQUENCER_254 0x30FE 482#define WM8996_WRITE_SEQUENCER_255 0x30FF 483#define WM8996_WRITE_SEQUENCER_256 0x3100 484#define WM8996_WRITE_SEQUENCER_257 0x3101 485#define WM8996_WRITE_SEQUENCER_258 0x3102 486#define WM8996_WRITE_SEQUENCER_259 0x3103 487#define WM8996_WRITE_SEQUENCER_260 0x3104 488#define WM8996_WRITE_SEQUENCER_261 0x3105 489#define WM8996_WRITE_SEQUENCER_262 0x3106 490#define WM8996_WRITE_SEQUENCER_263 0x3107 491#define WM8996_WRITE_SEQUENCER_264 0x3108 492#define WM8996_WRITE_SEQUENCER_265 0x3109 493#define WM8996_WRITE_SEQUENCER_266 0x310A 494#define WM8996_WRITE_SEQUENCER_267 0x310B 495#define WM8996_WRITE_SEQUENCER_268 0x310C 496#define WM8996_WRITE_SEQUENCER_269 0x310D 497#define WM8996_WRITE_SEQUENCER_270 0x310E 498#define WM8996_WRITE_SEQUENCER_271 0x310F 499#define WM8996_WRITE_SEQUENCER_272 0x3110 500#define WM8996_WRITE_SEQUENCER_273 0x3111 501#define WM8996_WRITE_SEQUENCER_274 0x3112 502#define WM8996_WRITE_SEQUENCER_275 0x3113 503#define WM8996_WRITE_SEQUENCER_276 0x3114 504#define WM8996_WRITE_SEQUENCER_277 0x3115 505#define WM8996_WRITE_SEQUENCER_278 0x3116 506#define WM8996_WRITE_SEQUENCER_279 0x3117 507#define WM8996_WRITE_SEQUENCER_280 0x3118 508#define WM8996_WRITE_SEQUENCER_281 0x3119 509#define WM8996_WRITE_SEQUENCER_282 0x311A 510#define WM8996_WRITE_SEQUENCER_283 0x311B 511#define WM8996_WRITE_SEQUENCER_284 0x311C 512#define WM8996_WRITE_SEQUENCER_285 0x311D 513#define WM8996_WRITE_SEQUENCER_286 0x311E 514#define WM8996_WRITE_SEQUENCER_287 0x311F 515#define WM8996_WRITE_SEQUENCER_288 0x3120 516#define WM8996_WRITE_SEQUENCER_289 0x3121 517#define WM8996_WRITE_SEQUENCER_290 0x3122 518#define WM8996_WRITE_SEQUENCER_291 0x3123 519#define WM8996_WRITE_SEQUENCER_292 0x3124 520#define WM8996_WRITE_SEQUENCER_293 0x3125 521#define WM8996_WRITE_SEQUENCER_294 0x3126 522#define WM8996_WRITE_SEQUENCER_295 0x3127 523#define WM8996_WRITE_SEQUENCER_296 0x3128 524#define WM8996_WRITE_SEQUENCER_297 0x3129 525#define WM8996_WRITE_SEQUENCER_298 0x312A 526#define WM8996_WRITE_SEQUENCER_299 0x312B 527#define WM8996_WRITE_SEQUENCER_300 0x312C 528#define WM8996_WRITE_SEQUENCER_301 0x312D 529#define WM8996_WRITE_SEQUENCER_302 0x312E 530#define WM8996_WRITE_SEQUENCER_303 0x312F 531#define WM8996_WRITE_SEQUENCER_304 0x3130 532#define WM8996_WRITE_SEQUENCER_305 0x3131 533#define WM8996_WRITE_SEQUENCER_306 0x3132 534#define WM8996_WRITE_SEQUENCER_307 0x3133 535#define WM8996_WRITE_SEQUENCER_308 0x3134 536#define WM8996_WRITE_SEQUENCER_309 0x3135 537#define WM8996_WRITE_SEQUENCER_310 0x3136 538#define WM8996_WRITE_SEQUENCER_311 0x3137 539#define WM8996_WRITE_SEQUENCER_312 0x3138 540#define WM8996_WRITE_SEQUENCER_313 0x3139 541#define WM8996_WRITE_SEQUENCER_314 0x313A 542#define WM8996_WRITE_SEQUENCER_315 0x313B 543#define WM8996_WRITE_SEQUENCER_316 0x313C 544#define WM8996_WRITE_SEQUENCER_317 0x313D 545#define WM8996_WRITE_SEQUENCER_318 0x313E 546#define WM8996_WRITE_SEQUENCER_319 0x313F 547#define WM8996_WRITE_SEQUENCER_320 0x3140 548#define WM8996_WRITE_SEQUENCER_321 0x3141 549#define WM8996_WRITE_SEQUENCER_322 0x3142 550#define WM8996_WRITE_SEQUENCER_323 0x3143 551#define WM8996_WRITE_SEQUENCER_324 0x3144 552#define WM8996_WRITE_SEQUENCER_325 0x3145 553#define WM8996_WRITE_SEQUENCER_326 0x3146 554#define WM8996_WRITE_SEQUENCER_327 0x3147 555#define WM8996_WRITE_SEQUENCER_328 0x3148 556#define WM8996_WRITE_SEQUENCER_329 0x3149 557#define WM8996_WRITE_SEQUENCER_330 0x314A 558#define WM8996_WRITE_SEQUENCER_331 0x314B 559#define WM8996_WRITE_SEQUENCER_332 0x314C 560#define WM8996_WRITE_SEQUENCER_333 0x314D 561#define WM8996_WRITE_SEQUENCER_334 0x314E 562#define WM8996_WRITE_SEQUENCER_335 0x314F 563#define WM8996_WRITE_SEQUENCER_336 0x3150 564#define WM8996_WRITE_SEQUENCER_337 0x3151 565#define WM8996_WRITE_SEQUENCER_338 0x3152 566#define WM8996_WRITE_SEQUENCER_339 0x3153 567#define WM8996_WRITE_SEQUENCER_340 0x3154 568#define WM8996_WRITE_SEQUENCER_341 0x3155 569#define WM8996_WRITE_SEQUENCER_342 0x3156 570#define WM8996_WRITE_SEQUENCER_343 0x3157 571#define WM8996_WRITE_SEQUENCER_344 0x3158 572#define WM8996_WRITE_SEQUENCER_345 0x3159 573#define WM8996_WRITE_SEQUENCER_346 0x315A 574#define WM8996_WRITE_SEQUENCER_347 0x315B 575#define WM8996_WRITE_SEQUENCER_348 0x315C 576#define WM8996_WRITE_SEQUENCER_349 0x315D 577#define WM8996_WRITE_SEQUENCER_350 0x315E 578#define WM8996_WRITE_SEQUENCER_351 0x315F 579#define WM8996_WRITE_SEQUENCER_352 0x3160 580#define WM8996_WRITE_SEQUENCER_353 0x3161 581#define WM8996_WRITE_SEQUENCER_354 0x3162 582#define WM8996_WRITE_SEQUENCER_355 0x3163 583#define WM8996_WRITE_SEQUENCER_356 0x3164 584#define WM8996_WRITE_SEQUENCER_357 0x3165 585#define WM8996_WRITE_SEQUENCER_358 0x3166 586#define WM8996_WRITE_SEQUENCER_359 0x3167 587#define WM8996_WRITE_SEQUENCER_360 0x3168 588#define WM8996_WRITE_SEQUENCER_361 0x3169 589#define WM8996_WRITE_SEQUENCER_362 0x316A 590#define WM8996_WRITE_SEQUENCER_363 0x316B 591#define WM8996_WRITE_SEQUENCER_364 0x316C 592#define WM8996_WRITE_SEQUENCER_365 0x316D 593#define WM8996_WRITE_SEQUENCER_366 0x316E 594#define WM8996_WRITE_SEQUENCER_367 0x316F 595#define WM8996_WRITE_SEQUENCER_368 0x3170 596#define WM8996_WRITE_SEQUENCER_369 0x3171 597#define WM8996_WRITE_SEQUENCER_370 0x3172 598#define WM8996_WRITE_SEQUENCER_371 0x3173 599#define WM8996_WRITE_SEQUENCER_372 0x3174 600#define WM8996_WRITE_SEQUENCER_373 0x3175 601#define WM8996_WRITE_SEQUENCER_374 0x3176 602#define WM8996_WRITE_SEQUENCER_375 0x3177 603#define WM8996_WRITE_SEQUENCER_376 0x3178 604#define WM8996_WRITE_SEQUENCER_377 0x3179 605#define WM8996_WRITE_SEQUENCER_378 0x317A 606#define WM8996_WRITE_SEQUENCER_379 0x317B 607#define WM8996_WRITE_SEQUENCER_380 0x317C 608#define WM8996_WRITE_SEQUENCER_381 0x317D 609#define WM8996_WRITE_SEQUENCER_382 0x317E 610#define WM8996_WRITE_SEQUENCER_383 0x317F 611#define WM8996_WRITE_SEQUENCER_384 0x3180 612#define WM8996_WRITE_SEQUENCER_385 0x3181 613#define WM8996_WRITE_SEQUENCER_386 0x3182 614#define WM8996_WRITE_SEQUENCER_387 0x3183 615#define WM8996_WRITE_SEQUENCER_388 0x3184 616#define WM8996_WRITE_SEQUENCER_389 0x3185 617#define WM8996_WRITE_SEQUENCER_390 0x3186 618#define WM8996_WRITE_SEQUENCER_391 0x3187 619#define WM8996_WRITE_SEQUENCER_392 0x3188 620#define WM8996_WRITE_SEQUENCER_393 0x3189 621#define WM8996_WRITE_SEQUENCER_394 0x318A 622#define WM8996_WRITE_SEQUENCER_395 0x318B 623#define WM8996_WRITE_SEQUENCER_396 0x318C 624#define WM8996_WRITE_SEQUENCER_397 0x318D 625#define WM8996_WRITE_SEQUENCER_398 0x318E 626#define WM8996_WRITE_SEQUENCER_399 0x318F 627#define WM8996_WRITE_SEQUENCER_400 0x3190 628#define WM8996_WRITE_SEQUENCER_401 0x3191 629#define WM8996_WRITE_SEQUENCER_402 0x3192 630#define WM8996_WRITE_SEQUENCER_403 0x3193 631#define WM8996_WRITE_SEQUENCER_404 0x3194 632#define WM8996_WRITE_SEQUENCER_405 0x3195 633#define WM8996_WRITE_SEQUENCER_406 0x3196 634#define WM8996_WRITE_SEQUENCER_407 0x3197 635#define WM8996_WRITE_SEQUENCER_408 0x3198 636#define WM8996_WRITE_SEQUENCER_409 0x3199 637#define WM8996_WRITE_SEQUENCER_410 0x319A 638#define WM8996_WRITE_SEQUENCER_411 0x319B 639#define WM8996_WRITE_SEQUENCER_412 0x319C 640#define WM8996_WRITE_SEQUENCER_413 0x319D 641#define WM8996_WRITE_SEQUENCER_414 0x319E 642#define WM8996_WRITE_SEQUENCER_415 0x319F 643#define WM8996_WRITE_SEQUENCER_416 0x31A0 644#define WM8996_WRITE_SEQUENCER_417 0x31A1 645#define WM8996_WRITE_SEQUENCER_418 0x31A2 646#define WM8996_WRITE_SEQUENCER_419 0x31A3 647#define WM8996_WRITE_SEQUENCER_420 0x31A4 648#define WM8996_WRITE_SEQUENCER_421 0x31A5 649#define WM8996_WRITE_SEQUENCER_422 0x31A6 650#define WM8996_WRITE_SEQUENCER_423 0x31A7 651#define WM8996_WRITE_SEQUENCER_424 0x31A8 652#define WM8996_WRITE_SEQUENCER_425 0x31A9 653#define WM8996_WRITE_SEQUENCER_426 0x31AA 654#define WM8996_WRITE_SEQUENCER_427 0x31AB 655#define WM8996_WRITE_SEQUENCER_428 0x31AC 656#define WM8996_WRITE_SEQUENCER_429 0x31AD 657#define WM8996_WRITE_SEQUENCER_430 0x31AE 658#define WM8996_WRITE_SEQUENCER_431 0x31AF 659#define WM8996_WRITE_SEQUENCER_432 0x31B0 660#define WM8996_WRITE_SEQUENCER_433 0x31B1 661#define WM8996_WRITE_SEQUENCER_434 0x31B2 662#define WM8996_WRITE_SEQUENCER_435 0x31B3 663#define WM8996_WRITE_SEQUENCER_436 0x31B4 664#define WM8996_WRITE_SEQUENCER_437 0x31B5 665#define WM8996_WRITE_SEQUENCER_438 0x31B6 666#define WM8996_WRITE_SEQUENCER_439 0x31B7 667#define WM8996_WRITE_SEQUENCER_440 0x31B8 668#define WM8996_WRITE_SEQUENCER_441 0x31B9 669#define WM8996_WRITE_SEQUENCER_442 0x31BA 670#define WM8996_WRITE_SEQUENCER_443 0x31BB 671#define WM8996_WRITE_SEQUENCER_444 0x31BC 672#define WM8996_WRITE_SEQUENCER_445 0x31BD 673#define WM8996_WRITE_SEQUENCER_446 0x31BE 674#define WM8996_WRITE_SEQUENCER_447 0x31BF 675#define WM8996_WRITE_SEQUENCER_448 0x31C0 676#define WM8996_WRITE_SEQUENCER_449 0x31C1 677#define WM8996_WRITE_SEQUENCER_450 0x31C2 678#define WM8996_WRITE_SEQUENCER_451 0x31C3 679#define WM8996_WRITE_SEQUENCER_452 0x31C4 680#define WM8996_WRITE_SEQUENCER_453 0x31C5 681#define WM8996_WRITE_SEQUENCER_454 0x31C6 682#define WM8996_WRITE_SEQUENCER_455 0x31C7 683#define WM8996_WRITE_SEQUENCER_456 0x31C8 684#define WM8996_WRITE_SEQUENCER_457 0x31C9 685#define WM8996_WRITE_SEQUENCER_458 0x31CA 686#define WM8996_WRITE_SEQUENCER_459 0x31CB 687#define WM8996_WRITE_SEQUENCER_460 0x31CC 688#define WM8996_WRITE_SEQUENCER_461 0x31CD 689#define WM8996_WRITE_SEQUENCER_462 0x31CE 690#define WM8996_WRITE_SEQUENCER_463 0x31CF 691#define WM8996_WRITE_SEQUENCER_464 0x31D0 692#define WM8996_WRITE_SEQUENCER_465 0x31D1 693#define WM8996_WRITE_SEQUENCER_466 0x31D2 694#define WM8996_WRITE_SEQUENCER_467 0x31D3 695#define WM8996_WRITE_SEQUENCER_468 0x31D4 696#define WM8996_WRITE_SEQUENCER_469 0x31D5 697#define WM8996_WRITE_SEQUENCER_470 0x31D6 698#define WM8996_WRITE_SEQUENCER_471 0x31D7 699#define WM8996_WRITE_SEQUENCER_472 0x31D8 700#define WM8996_WRITE_SEQUENCER_473 0x31D9 701#define WM8996_WRITE_SEQUENCER_474 0x31DA 702#define WM8996_WRITE_SEQUENCER_475 0x31DB 703#define WM8996_WRITE_SEQUENCER_476 0x31DC 704#define WM8996_WRITE_SEQUENCER_477 0x31DD 705#define WM8996_WRITE_SEQUENCER_478 0x31DE 706#define WM8996_WRITE_SEQUENCER_479 0x31DF 707#define WM8996_WRITE_SEQUENCER_480 0x31E0 708#define WM8996_WRITE_SEQUENCER_481 0x31E1 709#define WM8996_WRITE_SEQUENCER_482 0x31E2 710#define WM8996_WRITE_SEQUENCER_483 0x31E3 711#define WM8996_WRITE_SEQUENCER_484 0x31E4 712#define WM8996_WRITE_SEQUENCER_485 0x31E5 713#define WM8996_WRITE_SEQUENCER_486 0x31E6 714#define WM8996_WRITE_SEQUENCER_487 0x31E7 715#define WM8996_WRITE_SEQUENCER_488 0x31E8 716#define WM8996_WRITE_SEQUENCER_489 0x31E9 717#define WM8996_WRITE_SEQUENCER_490 0x31EA 718#define WM8996_WRITE_SEQUENCER_491 0x31EB 719#define WM8996_WRITE_SEQUENCER_492 0x31EC 720#define WM8996_WRITE_SEQUENCER_493 0x31ED 721#define WM8996_WRITE_SEQUENCER_494 0x31EE 722#define WM8996_WRITE_SEQUENCER_495 0x31EF 723#define WM8996_WRITE_SEQUENCER_496 0x31F0 724#define WM8996_WRITE_SEQUENCER_497 0x31F1 725#define WM8996_WRITE_SEQUENCER_498 0x31F2 726#define WM8996_WRITE_SEQUENCER_499 0x31F3 727#define WM8996_WRITE_SEQUENCER_500 0x31F4 728#define WM8996_WRITE_SEQUENCER_501 0x31F5 729#define WM8996_WRITE_SEQUENCER_502 0x31F6 730#define WM8996_WRITE_SEQUENCER_503 0x31F7 731#define WM8996_WRITE_SEQUENCER_504 0x31F8 732#define WM8996_WRITE_SEQUENCER_505 0x31F9 733#define WM8996_WRITE_SEQUENCER_506 0x31FA 734#define WM8996_WRITE_SEQUENCER_507 0x31FB 735#define WM8996_WRITE_SEQUENCER_508 0x31FC 736#define WM8996_WRITE_SEQUENCER_509 0x31FD 737#define WM8996_WRITE_SEQUENCER_510 0x31FE 738#define WM8996_WRITE_SEQUENCER_511 0x31FF 739 740#define WM8996_REGISTER_COUNT 706 741#define WM8996_MAX_REGISTER 0x31FF 742 743/* 744 * Field Definitions. 745 */ 746 747/* 748 * R0 (0x00) - Software Reset 749 */ 750#define WM8996_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 751#define WM8996_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 752#define WM8996_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 753 754/* 755 * R1 (0x01) - Power Management (1) 756 */ 757#define WM8996_MICB2_ENA 0x0200 /* MICB2_ENA */ 758#define WM8996_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ 759#define WM8996_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ 760#define WM8996_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 761#define WM8996_MICB1_ENA 0x0100 /* MICB1_ENA */ 762#define WM8996_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ 763#define WM8996_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ 764#define WM8996_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 765#define WM8996_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ 766#define WM8996_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ 767#define WM8996_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ 768#define WM8996_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ 769#define WM8996_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ 770#define WM8996_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ 771#define WM8996_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ 772#define WM8996_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ 773#define WM8996_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ 774#define WM8996_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ 775#define WM8996_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ 776#define WM8996_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 777#define WM8996_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ 778#define WM8996_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ 779#define WM8996_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ 780#define WM8996_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 781#define WM8996_BG_ENA 0x0001 /* BG_ENA */ 782#define WM8996_BG_ENA_MASK 0x0001 /* BG_ENA */ 783#define WM8996_BG_ENA_SHIFT 0 /* BG_ENA */ 784#define WM8996_BG_ENA_WIDTH 1 /* BG_ENA */ 785 786/* 787 * R2 (0x02) - Power Management (2) 788 */ 789#define WM8996_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 790#define WM8996_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 791#define WM8996_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 792#define WM8996_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 793#define WM8996_INL_ENA 0x0020 /* INL_ENA */ 794#define WM8996_INL_ENA_MASK 0x0020 /* INL_ENA */ 795#define WM8996_INL_ENA_SHIFT 5 /* INL_ENA */ 796#define WM8996_INL_ENA_WIDTH 1 /* INL_ENA */ 797#define WM8996_INR_ENA 0x0010 /* INR_ENA */ 798#define WM8996_INR_ENA_MASK 0x0010 /* INR_ENA */ 799#define WM8996_INR_ENA_SHIFT 4 /* INR_ENA */ 800#define WM8996_INR_ENA_WIDTH 1 /* INR_ENA */ 801#define WM8996_LDO2_ENA 0x0002 /* LDO2_ENA */ 802#define WM8996_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ 803#define WM8996_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ 804#define WM8996_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 805 806/* 807 * R3 (0x03) - Power Management (3) 808 */ 809#define WM8996_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */ 810#define WM8996_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */ 811#define WM8996_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */ 812#define WM8996_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */ 813#define WM8996_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */ 814#define WM8996_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */ 815#define WM8996_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */ 816#define WM8996_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */ 817#define WM8996_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */ 818#define WM8996_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */ 819#define WM8996_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */ 820#define WM8996_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */ 821#define WM8996_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */ 822#define WM8996_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */ 823#define WM8996_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */ 824#define WM8996_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */ 825#define WM8996_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 826#define WM8996_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 827#define WM8996_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 828#define WM8996_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 829#define WM8996_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 830#define WM8996_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 831#define WM8996_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 832#define WM8996_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 833#define WM8996_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 834#define WM8996_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 835#define WM8996_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 836#define WM8996_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 837#define WM8996_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 838#define WM8996_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 839#define WM8996_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 840#define WM8996_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 841#define WM8996_ADCL_ENA 0x0002 /* ADCL_ENA */ 842#define WM8996_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 843#define WM8996_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 844#define WM8996_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 845#define WM8996_ADCR_ENA 0x0001 /* ADCR_ENA */ 846#define WM8996_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 847#define WM8996_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 848#define WM8996_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 849 850/* 851 * R4 (0x04) - Power Management (4) 852 */ 853#define WM8996_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */ 854#define WM8996_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */ 855#define WM8996_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */ 856#define WM8996_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */ 857#define WM8996_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */ 858#define WM8996_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */ 859#define WM8996_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */ 860#define WM8996_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */ 861#define WM8996_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */ 862#define WM8996_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */ 863#define WM8996_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */ 864#define WM8996_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */ 865#define WM8996_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */ 866#define WM8996_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */ 867#define WM8996_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */ 868#define WM8996_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */ 869#define WM8996_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */ 870#define WM8996_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */ 871#define WM8996_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */ 872#define WM8996_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */ 873#define WM8996_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */ 874#define WM8996_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */ 875#define WM8996_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */ 876#define WM8996_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */ 877#define WM8996_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */ 878#define WM8996_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */ 879#define WM8996_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */ 880#define WM8996_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */ 881#define WM8996_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */ 882#define WM8996_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */ 883#define WM8996_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */ 884#define WM8996_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */ 885 886/* 887 * R5 (0x05) - Power Management (5) 888 */ 889#define WM8996_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */ 890#define WM8996_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */ 891#define WM8996_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */ 892#define WM8996_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */ 893#define WM8996_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */ 894#define WM8996_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */ 895#define WM8996_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */ 896#define WM8996_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */ 897#define WM8996_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */ 898#define WM8996_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */ 899#define WM8996_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */ 900#define WM8996_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */ 901#define WM8996_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */ 902#define WM8996_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */ 903#define WM8996_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */ 904#define WM8996_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */ 905#define WM8996_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 906#define WM8996_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 907#define WM8996_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 908#define WM8996_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 909#define WM8996_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 910#define WM8996_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 911#define WM8996_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 912#define WM8996_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 913#define WM8996_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 914#define WM8996_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 915#define WM8996_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 916#define WM8996_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 917#define WM8996_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 918#define WM8996_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 919#define WM8996_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 920#define WM8996_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 921 922/* 923 * R6 (0x06) - Power Management (6) 924 */ 925#define WM8996_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */ 926#define WM8996_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */ 927#define WM8996_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */ 928#define WM8996_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */ 929#define WM8996_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */ 930#define WM8996_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */ 931#define WM8996_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */ 932#define WM8996_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */ 933#define WM8996_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */ 934#define WM8996_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */ 935#define WM8996_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */ 936#define WM8996_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */ 937#define WM8996_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */ 938#define WM8996_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */ 939#define WM8996_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */ 940#define WM8996_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */ 941#define WM8996_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */ 942#define WM8996_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */ 943#define WM8996_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */ 944#define WM8996_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */ 945#define WM8996_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */ 946#define WM8996_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */ 947#define WM8996_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */ 948#define WM8996_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */ 949#define WM8996_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */ 950#define WM8996_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */ 951#define WM8996_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */ 952#define WM8996_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */ 953#define WM8996_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */ 954#define WM8996_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */ 955#define WM8996_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */ 956#define WM8996_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */ 957 958/* 959 * R7 (0x07) - Power Management (7) 960 */ 961#define WM8996_DMIC2_FN 0x0200 /* DMIC2_FN */ 962#define WM8996_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */ 963#define WM8996_DMIC2_FN_SHIFT 9 /* DMIC2_FN */ 964#define WM8996_DMIC2_FN_WIDTH 1 /* DMIC2_FN */ 965#define WM8996_DMIC1_FN 0x0100 /* DMIC1_FN */ 966#define WM8996_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */ 967#define WM8996_DMIC1_FN_SHIFT 8 /* DMIC1_FN */ 968#define WM8996_DMIC1_FN_WIDTH 1 /* DMIC1_FN */ 969#define WM8996_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */ 970#define WM8996_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */ 971#define WM8996_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */ 972#define WM8996_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */ 973#define WM8996_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */ 974#define WM8996_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */ 975#define WM8996_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */ 976#define WM8996_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */ 977#define WM8996_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */ 978#define WM8996_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */ 979#define WM8996_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */ 980#define WM8996_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */ 981#define WM8996_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */ 982#define WM8996_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */ 983#define WM8996_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */ 984#define WM8996_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */ 985#define WM8996_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */ 986#define WM8996_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */ 987#define WM8996_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */ 988#define WM8996_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */ 989#define WM8996_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */ 990#define WM8996_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */ 991 992/* 993 * R8 (0x08) - Power Management (8) 994 */ 995#define WM8996_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */ 996#define WM8996_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */ 997#define WM8996_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */ 998#define WM8996_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */ 999#define WM8996_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */ 1000#define WM8996_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */
1001#define WM8996_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */ 1002#define WM8996_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */ 1003#define WM8996_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */ 1004#define WM8996_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */ 1005#define WM8996_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */ 1006 1007/* 1008 * R16 (0x10) - Left Line Input Volume 1009 */ 1010#define WM8996_IN1_VU 0x0080 /* IN1_VU */ 1011#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */ 1012#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */ 1013#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */ 1014#define WM8996_IN1L_ZC 0x0020 /* IN1L_ZC */ 1015#define WM8996_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ 1016#define WM8996_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ 1017#define WM8996_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 1018#define WM8996_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 1019#define WM8996_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 1020#define WM8996_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 1021 1022/* 1023 * R17 (0x11) - Right Line Input Volume 1024 */ 1025#define WM8996_IN1_VU 0x0080 /* IN1_VU */ 1026#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */ 1027#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */ 1028#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */ 1029#define WM8996_IN1R_ZC 0x0020 /* IN1R_ZC */ 1030#define WM8996_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ 1031#define WM8996_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ 1032#define WM8996_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 1033#define WM8996_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 1034#define WM8996_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 1035#define WM8996_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 1036 1037/* 1038 * R18 (0x12) - Line Input Control 1039 */ 1040#define WM8996_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */ 1041#define WM8996_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */ 1042#define WM8996_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */ 1043#define WM8996_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */ 1044#define WM8996_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */ 1045#define WM8996_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */ 1046 1047/* 1048 * R21 (0x15) - DAC1 HPOUT1 Volume 1049 */ 1050#define WM8996_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */ 1051#define WM8996_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ 1052#define WM8996_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ 1053#define WM8996_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */ 1054#define WM8996_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */ 1055#define WM8996_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */ 1056 1057/* 1058 * R22 (0x16) - DAC2 HPOUT2 Volume 1059 */ 1060#define WM8996_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */ 1061#define WM8996_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ 1062#define WM8996_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ 1063#define WM8996_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */ 1064#define WM8996_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */ 1065#define WM8996_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */ 1066 1067/* 1068 * R24 (0x18) - DAC1 Left Volume 1069 */ 1070#define WM8996_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 1071#define WM8996_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 1072#define WM8996_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 1073#define WM8996_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 1074#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1075#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1076#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1077#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1078#define WM8996_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 1079#define WM8996_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 1080#define WM8996_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 1081 1082/* 1083 * R25 (0x19) - DAC1 Right Volume 1084 */ 1085#define WM8996_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 1086#define WM8996_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 1087#define WM8996_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 1088#define WM8996_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 1089#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1090#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1091#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1092#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1093#define WM8996_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 1094#define WM8996_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 1095#define WM8996_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 1096 1097/* 1098 * R26 (0x1A) - DAC2 Left Volume 1099 */ 1100#define WM8996_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 1101#define WM8996_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 1102#define WM8996_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 1103#define WM8996_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 1104#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1105#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1106#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1107#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1108#define WM8996_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 1109#define WM8996_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 1110#define WM8996_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 1111 1112/* 1113 * R27 (0x1B) - DAC2 Right Volume 1114 */ 1115#define WM8996_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 1116#define WM8996_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 1117#define WM8996_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 1118#define WM8996_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 1119#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1120#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1121#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1122#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1123#define WM8996_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 1124#define WM8996_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 1125#define WM8996_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 1126 1127/* 1128 * R28 (0x1C) - Output1 Left Volume 1129 */ 1130#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1131#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1132#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1133#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1134#define WM8996_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ 1135#define WM8996_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ 1136#define WM8996_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ 1137#define WM8996_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1138#define WM8996_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */ 1139#define WM8996_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */ 1140#define WM8996_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */ 1141 1142/* 1143 * R29 (0x1D) - Output1 Right Volume 1144 */ 1145#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1146#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1147#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1148#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1149#define WM8996_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ 1150#define WM8996_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ 1151#define WM8996_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ 1152#define WM8996_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1153#define WM8996_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */ 1154#define WM8996_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */ 1155#define WM8996_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */ 1156 1157/* 1158 * R30 (0x1E) - Output2 Left Volume 1159 */ 1160#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1161#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1162#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1163#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1164#define WM8996_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */ 1165#define WM8996_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */ 1166#define WM8996_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */ 1167#define WM8996_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ 1168#define WM8996_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */ 1169#define WM8996_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */ 1170#define WM8996_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */ 1171 1172/* 1173 * R31 (0x1F) - Output2 Right Volume 1174 */ 1175#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1176#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1177#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1178#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1179#define WM8996_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */ 1180#define WM8996_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */ 1181#define WM8996_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */ 1182#define WM8996_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ 1183#define WM8996_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */ 1184#define WM8996_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */ 1185#define WM8996_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */ 1186 1187/* 1188 * R32 (0x20) - MICBIAS (1) 1189 */ 1190#define WM8996_MICB1_RATE 0x0020 /* MICB1_RATE */ 1191#define WM8996_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1192#define WM8996_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1193#define WM8996_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1194#define WM8996_MICB1_MODE 0x0010 /* MICB1_MODE */ 1195#define WM8996_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */ 1196#define WM8996_MICB1_MODE_SHIFT 4 /* MICB1_MODE */ 1197#define WM8996_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 1198#define WM8996_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */ 1199#define WM8996_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */ 1200#define WM8996_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */ 1201#define WM8996_MICB1_DISCH 0x0001 /* MICB1_DISCH */ 1202#define WM8996_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ 1203#define WM8996_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ 1204#define WM8996_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1205 1206/* 1207 * R33 (0x21) - MICBIAS (2) 1208 */ 1209#define WM8996_MICB2_RATE 0x0020 /* MICB2_RATE */ 1210#define WM8996_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 1211#define WM8996_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 1212#define WM8996_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 1213#define WM8996_MICB2_MODE 0x0010 /* MICB2_MODE */ 1214#define WM8996_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */ 1215#define WM8996_MICB2_MODE_SHIFT 4 /* MICB2_MODE */ 1216#define WM8996_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 1217#define WM8996_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */ 1218#define WM8996_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */ 1219#define WM8996_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */ 1220#define WM8996_MICB2_DISCH 0x0001 /* MICB2_DISCH */ 1221#define WM8996_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ 1222#define WM8996_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ 1223#define WM8996_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1224 1225/* 1226 * R40 (0x28) - LDO 1 1227 */ 1228#define WM8996_LDO1_MODE 0x0020 /* LDO1_MODE */ 1229#define WM8996_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ 1230#define WM8996_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ 1231#define WM8996_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ 1232#define WM8996_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ 1233#define WM8996_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ 1234#define WM8996_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ 1235#define WM8996_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1236#define WM8996_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1237#define WM8996_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1238#define WM8996_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1239 1240/* 1241 * R41 (0x29) - LDO 2 1242 */ 1243#define WM8996_LDO2_MODE 0x0020 /* LDO2_MODE */ 1244#define WM8996_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ 1245#define WM8996_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ 1246#define WM8996_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ 1247#define WM8996_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ 1248#define WM8996_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ 1249#define WM8996_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ 1250#define WM8996_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1251#define WM8996_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1252#define WM8996_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1253#define WM8996_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1254 1255/* 1256 * R48 (0x30) - Accessory Detect Mode 1 1257 */ 1258#define WM8996_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ 1259#define WM8996_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ 1260#define WM8996_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ 1261 1262/* 1263 * R49 (0x31) - Accessory Detect Mode 2 1264 */ 1265#define WM8996_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */ 1266#define WM8996_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */ 1267#define WM8996_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */ 1268#define WM8996_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */ 1269#define WM8996_MICD_SRC 0x0002 /* MICD_SRC */ 1270#define WM8996_MICD_SRC_MASK 0x0002 /* MICD_SRC */ 1271#define WM8996_MICD_SRC_SHIFT 1 /* MICD_SRC */ 1272#define WM8996_MICD_SRC_WIDTH 1 /* MICD_SRC */ 1273#define WM8996_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */ 1274#define WM8996_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */ 1275#define WM8996_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */ 1276#define WM8996_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */ 1277 1278/* 1279 * R52 (0x34) - Headphone Detect 1 1280 */ 1281#define WM8996_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 1282#define WM8996_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 1283#define WM8996_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 1284#define WM8996_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 1285#define WM8996_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 1286#define WM8996_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 1287#define WM8996_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ 1288#define WM8996_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ 1289#define WM8996_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ 1290#define WM8996_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 1291#define WM8996_HP_POLL 0x0001 /* HP_POLL */ 1292#define WM8996_HP_POLL_MASK 0x0001 /* HP_POLL */ 1293#define WM8996_HP_POLL_SHIFT 0 /* HP_POLL */ 1294#define WM8996_HP_POLL_WIDTH 1 /* HP_POLL */ 1295 1296/* 1297 * R53 (0x35) - Headphone Detect 2 1298 */ 1299#define WM8996_HP_DONE 0x0080 /* HP_DONE */ 1300#define WM8996_HP_DONE_MASK 0x0080 /* HP_DONE */ 1301#define WM8996_HP_DONE_SHIFT 7 /* HP_DONE */ 1302#define WM8996_HP_DONE_WIDTH 1 /* HP_DONE */ 1303#define WM8996_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1304#define WM8996_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1305#define WM8996_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1306 1307/* 1308 * R56 (0x38) - Mic Detect 1 1309 */ 1310#define WM8996_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ 1311#define WM8996_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ 1312#define WM8996_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ 1313#define WM8996_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ 1314#define WM8996_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ 1315#define WM8996_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ 1316#define WM8996_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 1317#define WM8996_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 1318#define WM8996_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 1319#define WM8996_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 1320#define WM8996_MICD_ENA 0x0001 /* MICD_ENA */ 1321#define WM8996_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 1322#define WM8996_MICD_ENA_SHIFT 0 /* MICD_ENA */ 1323#define WM8996_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1324 1325/* 1326 * R57 (0x39) - Mic Detect 2 1327 */ 1328#define WM8996_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ 1329#define WM8996_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ 1330#define WM8996_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ 1331 1332/* 1333 * R58 (0x3A) - Mic Detect 3 1334 */ 1335#define WM8996_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ 1336#define WM8996_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ 1337#define WM8996_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ 1338#define WM8996_MICD_VALID 0x0002 /* MICD_VALID */ 1339#define WM8996_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 1340#define WM8996_MICD_VALID_SHIFT 1 /* MICD_VALID */ 1341#define WM8996_MICD_VALID_WIDTH 1 /* MICD_VALID */ 1342#define WM8996_MICD_STS 0x0001 /* MICD_STS */ 1343#define WM8996_MICD_STS_MASK 0x0001 /* MICD_STS */ 1344#define WM8996_MICD_STS_SHIFT 0 /* MICD_STS */ 1345#define WM8996_MICD_STS_WIDTH 1 /* MICD_STS */ 1346 1347/* 1348 * R64 (0x40) - Charge Pump (1) 1349 */ 1350#define WM8996_CP_ENA 0x8000 /* CP_ENA */ 1351#define WM8996_CP_ENA_MASK 0x8000 /* CP_ENA */ 1352#define WM8996_CP_ENA_SHIFT 15 /* CP_ENA */ 1353#define WM8996_CP_ENA_WIDTH 1 /* CP_ENA */ 1354 1355/* 1356 * R65 (0x41) - Charge Pump (2) 1357 */ 1358#define WM8996_CP_DISCH 0x8000 /* CP_DISCH */ 1359#define WM8996_CP_DISCH_MASK 0x8000 /* CP_DISCH */ 1360#define WM8996_CP_DISCH_SHIFT 15 /* CP_DISCH */ 1361#define WM8996_CP_DISCH_WIDTH 1 /* CP_DISCH */ 1362 1363/* 1364 * R80 (0x50) - DC Servo (1) 1365 */ 1366#define WM8996_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 1367#define WM8996_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 1368#define WM8996_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 1369#define WM8996_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 1370#define WM8996_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 1371#define WM8996_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 1372#define WM8996_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 1373#define WM8996_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 1374#define WM8996_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 1375#define WM8996_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 1376#define WM8996_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 1377#define WM8996_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 1378#define WM8996_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 1379#define WM8996_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 1380#define WM8996_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 1381#define WM8996_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 1382 1383/* 1384 * R81 (0x51) - DC Servo (2) 1385 */ 1386#define WM8996_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 1387#define WM8996_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 1388#define WM8996_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 1389#define WM8996_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 1390#define WM8996_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 1391#define WM8996_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 1392#define WM8996_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 1393#define WM8996_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 1394#define WM8996_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 1395#define WM8996_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 1396#define WM8996_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 1397#define WM8996_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 1398#define WM8996_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 1399#define WM8996_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 1400#define WM8996_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 1401#define WM8996_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 1402#define WM8996_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 1403#define WM8996_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 1404#define WM8996_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 1405#define WM8996_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 1406#define WM8996_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 1407#define WM8996_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 1408#define WM8996_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 1409#define WM8996_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 1410#define WM8996_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 1411#define WM8996_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 1412#define WM8996_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 1413#define WM8996_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 1414#define WM8996_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 1415#define WM8996_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 1416#define WM8996_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 1417#define WM8996_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 1418#define WM8996_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 1419#define WM8996_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 1420#define WM8996_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 1421#define WM8996_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 1422#define WM8996_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 1423#define WM8996_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 1424#define WM8996_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 1425#define WM8996_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 1426#define WM8996_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 1427#define WM8996_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 1428#define WM8996_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 1429#define WM8996_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 1430#define WM8996_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 1431#define WM8996_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 1432#define WM8996_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 1433#define WM8996_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 1434#define WM8996_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1435#define WM8996_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1436#define WM8996_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 1437#define WM8996_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 1438#define WM8996_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1439#define WM8996_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1440#define WM8996_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 1441#define WM8996_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 1442#define WM8996_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1443#define WM8996_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1444#define WM8996_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 1445#define WM8996_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 1446#define WM8996_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1447#define WM8996_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1448#define WM8996_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 1449#define WM8996_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 1450 1451/* 1452 * R82 (0x52) - DC Servo (3) 1453 */ 1454#define WM8996_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1455#define WM8996_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1456#define WM8996_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1457#define WM8996_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 1458#define WM8996_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1459#define WM8996_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1460 1461/* 1462 * R84 (0x54) - DC Servo (5) 1463 */ 1464#define WM8996_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ 1465#define WM8996_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ 1466#define WM8996_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ 1467#define WM8996_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 1468#define WM8996_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 1469#define WM8996_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 1470 1471/* 1472 * R85 (0x55) - DC Servo (6) 1473 */ 1474#define WM8996_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1475#define WM8996_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1476#define WM8996_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1477#define WM8996_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 1478#define WM8996_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1479#define WM8996_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1480 1481/* 1482 * R86 (0x56) - DC Servo (7) 1483 */ 1484#define WM8996_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1485#define WM8996_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1486#define WM8996_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1487#define WM8996_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 1488#define WM8996_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1489#define WM8996_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1490 1491/* 1492 * R87 (0x57) - DC Servo Readback 0 1493 */ 1494#define WM8996_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 1495#define WM8996_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 1496#define WM8996_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 1497#define WM8996_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1498#define WM8996_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1499#define WM8996_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1500#define WM8996_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 1501#define WM8996_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 1502#define WM8996_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 1503 1504/* 1505 * R96 (0x60) - Analogue HP (1) 1506 */ 1507#define WM8996_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 1508#define WM8996_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 1509#define WM8996_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 1510#define WM8996_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 1511#define WM8996_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 1512#define WM8996_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 1513#define WM8996_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 1514#define WM8996_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 1515#define WM8996_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 1516#define WM8996_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 1517#define WM8996_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 1518#define WM8996_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 1519#define WM8996_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 1520#define WM8996_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 1521#define WM8996_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 1522#define WM8996_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 1523#define WM8996_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 1524#define WM8996_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 1525#define WM8996_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 1526#define WM8996_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 1527#define WM8996_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 1528#define WM8996_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 1529#define WM8996_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 1530#define WM8996_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 1531 1532/* 1533 * R97 (0x61) - Analogue HP (2) 1534 */ 1535#define WM8996_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ 1536#define WM8996_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ 1537#define WM8996_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ 1538#define WM8996_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ 1539#define WM8996_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ 1540#define WM8996_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ 1541#define WM8996_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ 1542#define WM8996_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ 1543#define WM8996_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ 1544#define WM8996_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ 1545#define WM8996_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ 1546#define WM8996_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ 1547#define WM8996_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ 1548#define WM8996_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ 1549#define WM8996_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ 1550#define WM8996_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ 1551#define WM8996_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ 1552#define WM8996_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ 1553#define WM8996_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ 1554#define WM8996_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ 1555#define WM8996_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ 1556#define WM8996_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ 1557#define WM8996_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ 1558#define WM8996_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ 1559 1560/* 1561 * R256 (0x100) - Chip Revision 1562 */ 1563#define WM8996_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 1564#define WM8996_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 1565#define WM8996_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 1566 1567/* 1568 * R257 (0x101) - Control Interface (1) 1569 */ 1570#define WM8996_REG_SYNC 0x8000 /* REG_SYNC */ 1571#define WM8996_REG_SYNC_MASK 0x8000 /* REG_SYNC */ 1572#define WM8996_REG_SYNC_SHIFT 15 /* REG_SYNC */ 1573#define WM8996_REG_SYNC_WIDTH 1 /* REG_SYNC */ 1574#define WM8996_AUTO_INC 0x0004 /* AUTO_INC */ 1575#define WM8996_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 1576#define WM8996_AUTO_INC_SHIFT 2 /* AUTO_INC */ 1577#define WM8996_AUTO_INC_WIDTH 1 /* AUTO_INC */ 1578 1579/* 1580 * R272 (0x110) - Write Sequencer Ctrl (1) 1581 */ 1582#define WM8996_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 1583#define WM8996_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 1584#define WM8996_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 1585#define WM8996_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1586#define WM8996_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1587#define WM8996_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1588#define WM8996_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1589#define WM8996_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1590#define WM8996_WSEQ_START 0x0100 /* WSEQ_START */ 1591#define WM8996_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1592#define WM8996_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1593#define WM8996_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1594#define WM8996_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 1595#define WM8996_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 1596#define WM8996_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 1597 1598/* 1599 * R273 (0x111) - Write Sequencer Ctrl (2) 1600 */ 1601#define WM8996_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 1602#define WM8996_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 1603#define WM8996_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 1604#define WM8996_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1605#define WM8996_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 1606#define WM8996_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 1607#define WM8996_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 1608 1609/* 1610 * R512 (0x200) - AIF Clocking (1) 1611 */ 1612#define WM8996_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */ 1613#define WM8996_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */ 1614#define WM8996_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */ 1615#define WM8996_SYSCLK_INV 0x0004 /* SYSCLK_INV */ 1616#define WM8996_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */ 1617#define WM8996_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */ 1618#define WM8996_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */ 1619#define WM8996_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */ 1620#define WM8996_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */ 1621#define WM8996_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */ 1622#define WM8996_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */ 1623#define WM8996_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */ 1624#define WM8996_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */ 1625#define WM8996_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */ 1626#define WM8996_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 1627 1628/* 1629 * R513 (0x201) - AIF Clocking (2) 1630 */ 1631#define WM8996_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */ 1632#define WM8996_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */ 1633#define WM8996_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */ 1634#define WM8996_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */ 1635#define WM8996_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */ 1636#define WM8996_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */ 1637 1638/* 1639 * R520 (0x208) - Clocking (1) 1640 */ 1641#define WM8996_LFCLK_ENA 0x0020 /* LFCLK_ENA */ 1642#define WM8996_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ 1643#define WM8996_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ 1644#define WM8996_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ 1645#define WM8996_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 1646#define WM8996_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 1647#define WM8996_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 1648#define WM8996_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 1649#define WM8996_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */ 1650#define WM8996_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */ 1651#define WM8996_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */ 1652#define WM8996_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */ 1653#define WM8996_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 1654#define WM8996_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 1655#define WM8996_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 1656#define WM8996_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 1657 1658/* 1659 * R521 (0x209) - Clocking (2) 1660 */ 1661#define WM8996_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 1662#define WM8996_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 1663#define WM8996_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 1664#define WM8996_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ 1665#define WM8996_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ 1666#define WM8996_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ 1667#define WM8996_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 1668#define WM8996_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 1669#define WM8996_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 1670 1671/* 1672 * R528 (0x210) - AIF Rate 1673 */ 1674#define WM8996_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */ 1675#define WM8996_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */ 1676#define WM8996_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */ 1677#define WM8996_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */ 1678 1679/* 1680 * R544 (0x220) - FLL Control (1) 1681 */ 1682#define WM8996_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ 1683#define WM8996_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ 1684#define WM8996_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ 1685#define WM8996_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ 1686#define WM8996_FLL_ENA 0x0001 /* FLL_ENA */ 1687#define WM8996_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 1688#define WM8996_FLL_ENA_SHIFT 0 /* FLL_ENA */ 1689#define WM8996_FLL_ENA_WIDTH 1 /* FLL_ENA */ 1690 1691/* 1692 * R545 (0x221) - FLL Control (2) 1693 */ 1694#define WM8996_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ 1695#define WM8996_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ 1696#define WM8996_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ 1697#define WM8996_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 1698#define WM8996_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 1699#define WM8996_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 1700 1701/* 1702 * R546 (0x222) - FLL Control (3) 1703 */ 1704#define WM8996_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ 1705#define WM8996_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ 1706#define WM8996_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ 1707 1708/* 1709 * R547 (0x223) - FLL Control (4) 1710 */ 1711#define WM8996_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ 1712#define WM8996_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ 1713#define WM8996_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ 1714#define WM8996_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */ 1715#define WM8996_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */ 1716#define WM8996_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */ 1717 1718/* 1719 * R548 (0x224) - FLL Control (5) 1720 */ 1721#define WM8996_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */ 1722#define WM8996_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */ 1723#define WM8996_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */ 1724#define WM8996_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */ 1725#define WM8996_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */ 1726#define WM8996_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */ 1727#define WM8996_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ 1728#define WM8996_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */ 1729#define WM8996_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */ 1730#define WM8996_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */ 1731#define WM8996_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */ 1732#define WM8996_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */ 1733#define WM8996_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */ 1734#define WM8996_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */ 1735#define WM8996_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */ 1736#define WM8996_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */ 1737#define WM8996_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */ 1738 1739/* 1740 * R549 (0x225) - FLL Control (6) 1741 */ 1742#define WM8996_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */ 1743#define WM8996_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */ 1744#define WM8996_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */ 1745#define WM8996_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */ 1746#define WM8996_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */ 1747#define WM8996_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */ 1748#define WM8996_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */ 1749 1750/* 1751 * R550 (0x226) - FLL EFS 1 1752 */ 1753#define WM8996_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ 1754#define WM8996_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ 1755#define WM8996_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ 1756 1757/* 1758 * R551 (0x227) - FLL EFS 2 1759 */ 1760#define WM8996_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */ 1761#define WM8996_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */ 1762#define WM8996_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */ 1763#define WM8996_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ 1764#define WM8996_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ 1765#define WM8996_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ 1766#define WM8996_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ 1767 1768/* 1769 * R768 (0x300) - AIF1 Control 1770 */ 1771#define WM8996_AIF1_TRI 0x0004 /* AIF1_TRI */ 1772#define WM8996_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */ 1773#define WM8996_AIF1_TRI_SHIFT 2 /* AIF1_TRI */ 1774#define WM8996_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 1775#define WM8996_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */ 1776#define WM8996_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */ 1777#define WM8996_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */ 1778 1779/* 1780 * R769 (0x301) - AIF1 BCLK 1781 */ 1782#define WM8996_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */ 1783#define WM8996_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */ 1784#define WM8996_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */ 1785#define WM8996_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 1786#define WM8996_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */ 1787#define WM8996_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */ 1788#define WM8996_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */ 1789#define WM8996_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 1790#define WM8996_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */ 1791#define WM8996_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */ 1792#define WM8996_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */ 1793#define WM8996_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 1794#define WM8996_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ 1795#define WM8996_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ 1796#define WM8996_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ 1797 1798/* 1799 * R770 (0x302) - AIF1 TX LRCLK(1) 1800 */ 1801#define WM8996_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */ 1802#define WM8996_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */ 1803#define WM8996_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */ 1804 1805/* 1806 * R771 (0x303) - AIF1 TX LRCLK(2) 1807 */ 1808#define WM8996_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */ 1809#define WM8996_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */ 1810#define WM8996_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */ 1811#define WM8996_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */ 1812#define WM8996_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 1813#define WM8996_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 1814#define WM8996_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 1815#define WM8996_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 1816#define WM8996_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 1817#define WM8996_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 1818#define WM8996_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 1819#define WM8996_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 1820#define WM8996_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 1821#define WM8996_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 1822#define WM8996_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 1823#define WM8996_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 1824 1825/* 1826 * R772 (0x304) - AIF1 RX LRCLK(1) 1827 */ 1828#define WM8996_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */ 1829#define WM8996_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */ 1830#define WM8996_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */ 1831 1832/* 1833 * R773 (0x305) - AIF1 RX LRCLK(2) 1834 */ 1835#define WM8996_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 1836#define WM8996_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 1837#define WM8996_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 1838#define WM8996_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 1839#define WM8996_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 1840#define WM8996_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 1841#define WM8996_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 1842#define WM8996_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 1843#define WM8996_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 1844#define WM8996_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 1845#define WM8996_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 1846#define WM8996_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 1847 1848/* 1849 * R774 (0x306) - AIF1TX Data Configuration (1) 1850 */ 1851#define WM8996_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */ 1852#define WM8996_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */ 1853#define WM8996_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */ 1854#define WM8996_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 1855#define WM8996_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 1856#define WM8996_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 1857 1858/* 1859 * R775 (0x307) - AIF1TX Data Configuration (2) 1860 */ 1861#define WM8996_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */ 1862#define WM8996_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */ 1863#define WM8996_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */ 1864#define WM8996_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 1865 1866/* 1867 * R776 (0x308) - AIF1RX Data Configuration 1868 */ 1869#define WM8996_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */ 1870#define WM8996_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */ 1871#define WM8996_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */ 1872#define WM8996_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 1873#define WM8996_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 1874#define WM8996_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 1875 1876/* 1877 * R777 (0x309) - AIF1TX Channel 0 Configuration 1878 */ 1879#define WM8996_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */ 1880#define WM8996_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */ 1881#define WM8996_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */ 1882#define WM8996_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */ 1883#define WM8996_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */ 1884#define WM8996_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */ 1885#define WM8996_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */ 1886#define WM8996_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */ 1887#define WM8996_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */ 1888#define WM8996_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */ 1889#define WM8996_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */ 1890#define WM8996_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ 1891#define WM8996_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ 1892 1893/* 1894 * R778 (0x30A) - AIF1TX Channel 1 Configuration 1895 */ 1896#define WM8996_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */ 1897#define WM8996_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */ 1898#define WM8996_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */ 1899#define WM8996_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */ 1900#define WM8996_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */ 1901#define WM8996_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */ 1902#define WM8996_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */ 1903#define WM8996_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */ 1904#define WM8996_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */ 1905#define WM8996_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */ 1906#define WM8996_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */ 1907#define WM8996_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ 1908#define WM8996_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ 1909 1910/* 1911 * R779 (0x30B) - AIF1TX Channel 2 Configuration 1912 */ 1913#define WM8996_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */ 1914#define WM8996_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */ 1915#define WM8996_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */ 1916#define WM8996_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */ 1917#define WM8996_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */ 1918#define WM8996_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */ 1919#define WM8996_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */ 1920#define WM8996_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */ 1921#define WM8996_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */ 1922#define WM8996_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */ 1923#define WM8996_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */ 1924#define WM8996_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ 1925#define WM8996_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ 1926 1927/* 1928 * R780 (0x30C) - AIF1TX Channel 3 Configuration 1929 */ 1930#define WM8996_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */ 1931#define WM8996_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */ 1932#define WM8996_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */ 1933#define WM8996_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */ 1934#define WM8996_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */ 1935#define WM8996_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */ 1936#define WM8996_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */ 1937#define WM8996_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */ 1938#define WM8996_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */ 1939#define WM8996_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */ 1940#define WM8996_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */ 1941#define WM8996_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ 1942#define WM8996_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ 1943 1944/* 1945 * R781 (0x30D) - AIF1TX Channel 4 Configuration 1946 */ 1947#define WM8996_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */ 1948#define WM8996_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */ 1949#define WM8996_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */ 1950#define WM8996_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */ 1951#define WM8996_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */ 1952#define WM8996_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */ 1953#define WM8996_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */ 1954#define WM8996_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */ 1955#define WM8996_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */ 1956#define WM8996_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */ 1957#define WM8996_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */ 1958#define WM8996_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ 1959#define WM8996_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ 1960 1961/* 1962 * R782 (0x30E) - AIF1TX Channel 5 Configuration 1963 */ 1964#define WM8996_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */ 1965#define WM8996_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */ 1966#define WM8996_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */ 1967#define WM8996_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */ 1968#define WM8996_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */ 1969#define WM8996_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */ 1970#define WM8996_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */ 1971#define WM8996_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */ 1972#define WM8996_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */ 1973#define WM8996_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */ 1974#define WM8996_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */ 1975#define WM8996_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ 1976#define WM8996_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ 1977 1978/* 1979 * R783 (0x30F) - AIF1RX Channel 0 Configuration 1980 */ 1981#define WM8996_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */ 1982#define WM8996_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */ 1983#define WM8996_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */ 1984#define WM8996_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */ 1985#define WM8996_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */ 1986#define WM8996_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */ 1987#define WM8996_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */ 1988#define WM8996_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */ 1989#define WM8996_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */ 1990#define WM8996_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */ 1991#define WM8996_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */ 1992#define WM8996_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ 1993#define WM8996_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ 1994 1995/* 1996 * R784 (0x310) - AIF1RX Channel 1 Configuration 1997 */ 1998#define WM8996_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */ 1999#define WM8996_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */ 2000#define WM8996_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */
2001#define WM8996_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */ 2002#define WM8996_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */ 2003#define WM8996_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */ 2004#define WM8996_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */ 2005#define WM8996_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */ 2006#define WM8996_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */ 2007#define WM8996_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */ 2008#define WM8996_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */ 2009#define WM8996_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ 2010#define WM8996_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ 2011 2012/* 2013 * R785 (0x311) - AIF1RX Channel 2 Configuration 2014 */ 2015#define WM8996_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */ 2016#define WM8996_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */ 2017#define WM8996_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */ 2018#define WM8996_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */ 2019#define WM8996_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */ 2020#define WM8996_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */ 2021#define WM8996_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */ 2022#define WM8996_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */ 2023#define WM8996_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */ 2024#define WM8996_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */ 2025#define WM8996_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */ 2026#define WM8996_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ 2027#define WM8996_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ 2028 2029/* 2030 * R786 (0x312) - AIF1RX Channel 3 Configuration 2031 */ 2032#define WM8996_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */ 2033#define WM8996_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */ 2034#define WM8996_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */ 2035#define WM8996_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */ 2036#define WM8996_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */ 2037#define WM8996_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */ 2038#define WM8996_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */ 2039#define WM8996_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */ 2040#define WM8996_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */ 2041#define WM8996_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */ 2042#define WM8996_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */ 2043#define WM8996_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ 2044#define WM8996_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ 2045 2046/* 2047 * R787 (0x313) - AIF1RX Channel 4 Configuration 2048 */ 2049#define WM8996_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */ 2050#define WM8996_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */ 2051#define WM8996_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */ 2052#define WM8996_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */ 2053#define WM8996_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */ 2054#define WM8996_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */ 2055#define WM8996_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */ 2056#define WM8996_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */ 2057#define WM8996_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */ 2058#define WM8996_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */ 2059#define WM8996_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */ 2060#define WM8996_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ 2061#define WM8996_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ 2062 2063/* 2064 * R788 (0x314) - AIF1RX Channel 5 Configuration 2065 */ 2066#define WM8996_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */ 2067#define WM8996_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */ 2068#define WM8996_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */ 2069#define WM8996_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */ 2070#define WM8996_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */ 2071#define WM8996_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */ 2072#define WM8996_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */ 2073#define WM8996_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */ 2074#define WM8996_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */ 2075#define WM8996_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */ 2076#define WM8996_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */ 2077#define WM8996_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ 2078#define WM8996_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ 2079 2080/* 2081 * R789 (0x315) - AIF1RX Mono Configuration 2082 */ 2083#define WM8996_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ 2084#define WM8996_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ 2085#define WM8996_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */ 2086#define WM8996_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */ 2087#define WM8996_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ 2088#define WM8996_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ 2089#define WM8996_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */ 2090#define WM8996_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */ 2091#define WM8996_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ 2092#define WM8996_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ 2093#define WM8996_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */ 2094#define WM8996_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */ 2095 2096/* 2097 * R794 (0x31A) - AIF1TX Test 2098 */ 2099#define WM8996_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */ 2100#define WM8996_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */ 2101#define WM8996_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */ 2102#define WM8996_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */ 2103#define WM8996_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */ 2104#define WM8996_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */ 2105#define WM8996_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */ 2106#define WM8996_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */ 2107#define WM8996_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */ 2108#define WM8996_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */ 2109#define WM8996_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */ 2110#define WM8996_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */ 2111 2112/* 2113 * R800 (0x320) - AIF2 Control 2114 */ 2115#define WM8996_AIF2_TRI 0x0004 /* AIF2_TRI */ 2116#define WM8996_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */ 2117#define WM8996_AIF2_TRI_SHIFT 2 /* AIF2_TRI */ 2118#define WM8996_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2119#define WM8996_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */ 2120#define WM8996_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */ 2121#define WM8996_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */ 2122 2123/* 2124 * R801 (0x321) - AIF2 BCLK 2125 */ 2126#define WM8996_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */ 2127#define WM8996_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */ 2128#define WM8996_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */ 2129#define WM8996_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2130#define WM8996_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */ 2131#define WM8996_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */ 2132#define WM8996_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */ 2133#define WM8996_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 2134#define WM8996_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */ 2135#define WM8996_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */ 2136#define WM8996_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */ 2137#define WM8996_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 2138#define WM8996_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */ 2139#define WM8996_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */ 2140#define WM8996_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */ 2141 2142/* 2143 * R802 (0x322) - AIF2 TX LRCLK(1) 2144 */ 2145#define WM8996_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */ 2146#define WM8996_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */ 2147#define WM8996_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */ 2148 2149/* 2150 * R803 (0x323) - AIF2 TX LRCLK(2) 2151 */ 2152#define WM8996_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */ 2153#define WM8996_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */ 2154#define WM8996_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */ 2155#define WM8996_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */ 2156#define WM8996_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 2157#define WM8996_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 2158#define WM8996_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 2159#define WM8996_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 2160#define WM8996_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 2161#define WM8996_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 2162#define WM8996_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 2163#define WM8996_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 2164#define WM8996_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 2165#define WM8996_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 2166#define WM8996_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 2167#define WM8996_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 2168 2169/* 2170 * R804 (0x324) - AIF2 RX LRCLK(1) 2171 */ 2172#define WM8996_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */ 2173#define WM8996_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */ 2174#define WM8996_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */ 2175 2176/* 2177 * R805 (0x325) - AIF2 RX LRCLK(2) 2178 */ 2179#define WM8996_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 2180#define WM8996_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 2181#define WM8996_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 2182#define WM8996_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 2183#define WM8996_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 2184#define WM8996_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 2185#define WM8996_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 2186#define WM8996_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 2187#define WM8996_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 2188#define WM8996_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 2189#define WM8996_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 2190#define WM8996_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 2191 2192/* 2193 * R806 (0x326) - AIF2TX Data Configuration (1) 2194 */ 2195#define WM8996_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */ 2196#define WM8996_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */ 2197#define WM8996_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */ 2198#define WM8996_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 2199#define WM8996_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 2200#define WM8996_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 2201 2202/* 2203 * R807 (0x327) - AIF2TX Data Configuration (2) 2204 */ 2205#define WM8996_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */ 2206#define WM8996_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */ 2207#define WM8996_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */ 2208#define WM8996_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 2209 2210/* 2211 * R808 (0x328) - AIF2RX Data Configuration 2212 */ 2213#define WM8996_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */ 2214#define WM8996_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */ 2215#define WM8996_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */ 2216#define WM8996_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 2217#define WM8996_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 2218#define WM8996_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 2219 2220/* 2221 * R809 (0x329) - AIF2TX Channel 0 Configuration 2222 */ 2223#define WM8996_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */ 2224#define WM8996_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */ 2225#define WM8996_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */ 2226#define WM8996_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */ 2227#define WM8996_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */ 2228#define WM8996_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */ 2229#define WM8996_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */ 2230#define WM8996_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */ 2231#define WM8996_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */ 2232#define WM8996_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */ 2233#define WM8996_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */ 2234#define WM8996_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ 2235#define WM8996_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ 2236 2237/* 2238 * R810 (0x32A) - AIF2TX Channel 1 Configuration 2239 */ 2240#define WM8996_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */ 2241#define WM8996_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */ 2242#define WM8996_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */ 2243#define WM8996_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */ 2244#define WM8996_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */ 2245#define WM8996_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */ 2246#define WM8996_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */ 2247#define WM8996_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */ 2248#define WM8996_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */ 2249#define WM8996_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */ 2250#define WM8996_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */ 2251#define WM8996_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ 2252#define WM8996_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ 2253 2254/* 2255 * R811 (0x32B) - AIF2RX Channel 0 Configuration 2256 */ 2257#define WM8996_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */ 2258#define WM8996_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */ 2259#define WM8996_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */ 2260#define WM8996_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */ 2261#define WM8996_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */ 2262#define WM8996_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */ 2263#define WM8996_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */ 2264#define WM8996_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */ 2265#define WM8996_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */ 2266#define WM8996_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */ 2267#define WM8996_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */ 2268#define WM8996_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ 2269#define WM8996_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ 2270 2271/* 2272 * R812 (0x32C) - AIF2RX Channel 1 Configuration 2273 */ 2274#define WM8996_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */ 2275#define WM8996_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */ 2276#define WM8996_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */ 2277#define WM8996_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */ 2278#define WM8996_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */ 2279#define WM8996_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */ 2280#define WM8996_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */ 2281#define WM8996_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */ 2282#define WM8996_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */ 2283#define WM8996_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */ 2284#define WM8996_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */ 2285#define WM8996_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ 2286#define WM8996_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ 2287 2288/* 2289 * R813 (0x32D) - AIF2RX Mono Configuration 2290 */ 2291#define WM8996_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ 2292#define WM8996_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ 2293#define WM8996_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */ 2294#define WM8996_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */ 2295 2296/* 2297 * R815 (0x32F) - AIF2TX Test 2298 */ 2299#define WM8996_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */ 2300#define WM8996_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */ 2301#define WM8996_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */ 2302#define WM8996_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */ 2303 2304/* 2305 * R1024 (0x400) - DSP1 TX Left Volume 2306 */ 2307#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */ 2308#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ 2309#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ 2310#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ 2311#define WM8996_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */ 2312#define WM8996_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */ 2313#define WM8996_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */ 2314 2315/* 2316 * R1025 (0x401) - DSP1 TX Right Volume 2317 */ 2318#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */ 2319#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ 2320#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ 2321#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ 2322#define WM8996_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */ 2323#define WM8996_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */ 2324#define WM8996_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */ 2325 2326/* 2327 * R1026 (0x402) - DSP1 RX Left Volume 2328 */ 2329#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */ 2330#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ 2331#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ 2332#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ 2333#define WM8996_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */ 2334#define WM8996_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */ 2335#define WM8996_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */ 2336 2337/* 2338 * R1027 (0x403) - DSP1 RX Right Volume 2339 */ 2340#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */ 2341#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ 2342#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ 2343#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ 2344#define WM8996_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */ 2345#define WM8996_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */ 2346#define WM8996_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */ 2347 2348/* 2349 * R1040 (0x410) - DSP1 TX Filters 2350 */ 2351#define WM8996_DSP1TX_NF 0x2000 /* DSP1TX_NF */ 2352#define WM8996_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */ 2353#define WM8996_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */ 2354#define WM8996_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */ 2355#define WM8996_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */ 2356#define WM8996_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */ 2357#define WM8996_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */ 2358#define WM8996_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */ 2359#define WM8996_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */ 2360#define WM8996_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */ 2361#define WM8996_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */ 2362#define WM8996_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */ 2363#define WM8996_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */ 2364#define WM8996_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */ 2365#define WM8996_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */ 2366#define WM8996_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */ 2367#define WM8996_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */ 2368#define WM8996_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */ 2369 2370/* 2371 * R1056 (0x420) - DSP1 RX Filters (1) 2372 */ 2373#define WM8996_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */ 2374#define WM8996_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */ 2375#define WM8996_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */ 2376#define WM8996_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */ 2377#define WM8996_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */ 2378#define WM8996_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */ 2379#define WM8996_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */ 2380#define WM8996_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */ 2381#define WM8996_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */ 2382#define WM8996_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */ 2383#define WM8996_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */ 2384#define WM8996_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */ 2385#define WM8996_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */ 2386#define WM8996_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */ 2387#define WM8996_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */ 2388#define WM8996_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */ 2389 2390/* 2391 * R1057 (0x421) - DSP1 RX Filters (2) 2392 */ 2393#define WM8996_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */ 2394#define WM8996_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */ 2395#define WM8996_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */ 2396#define WM8996_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */ 2397#define WM8996_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */ 2398#define WM8996_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */ 2399#define WM8996_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */ 2400 2401/* 2402 * R1088 (0x440) - DSP1 DRC (1) 2403 */ 2404#define WM8996_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */ 2405#define WM8996_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */ 2406#define WM8996_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */ 2407#define WM8996_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */ 2408#define WM8996_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */ 2409#define WM8996_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */ 2410#define WM8996_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */ 2411#define WM8996_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */ 2412#define WM8996_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */ 2413#define WM8996_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */ 2414#define WM8996_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */ 2415#define WM8996_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */ 2416#define WM8996_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */ 2417#define WM8996_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */ 2418#define WM8996_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */ 2419#define WM8996_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */ 2420#define WM8996_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */ 2421#define WM8996_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */ 2422#define WM8996_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ 2423#define WM8996_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ 2424#define WM8996_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */ 2425#define WM8996_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */ 2426#define WM8996_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */ 2427#define WM8996_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */ 2428#define WM8996_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */ 2429#define WM8996_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */ 2430#define WM8996_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */ 2431#define WM8996_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */ 2432#define WM8996_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */ 2433#define WM8996_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */ 2434#define WM8996_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */ 2435#define WM8996_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */ 2436#define WM8996_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */ 2437#define WM8996_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */ 2438#define WM8996_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */ 2439#define WM8996_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */ 2440#define WM8996_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */ 2441#define WM8996_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */ 2442#define WM8996_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */ 2443#define WM8996_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */ 2444#define WM8996_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */ 2445#define WM8996_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */ 2446 2447/* 2448 * R1089 (0x441) - DSP1 DRC (2) 2449 */ 2450#define WM8996_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */ 2451#define WM8996_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */ 2452#define WM8996_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */ 2453#define WM8996_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */ 2454#define WM8996_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */ 2455#define WM8996_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */ 2456#define WM8996_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */ 2457#define WM8996_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */ 2458#define WM8996_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */ 2459#define WM8996_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */ 2460#define WM8996_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */ 2461#define WM8996_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */ 2462 2463/* 2464 * R1090 (0x442) - DSP1 DRC (3) 2465 */ 2466#define WM8996_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */ 2467#define WM8996_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */ 2468#define WM8996_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */ 2469#define WM8996_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */ 2470#define WM8996_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */ 2471#define WM8996_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */ 2472#define WM8996_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */ 2473#define WM8996_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */ 2474#define WM8996_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */ 2475#define WM8996_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */ 2476#define WM8996_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */ 2477#define WM8996_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */ 2478#define WM8996_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */ 2479#define WM8996_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */ 2480#define WM8996_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */ 2481#define WM8996_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */ 2482#define WM8996_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */ 2483#define WM8996_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */ 2484 2485/* 2486 * R1091 (0x443) - DSP1 DRC (4) 2487 */ 2488#define WM8996_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */ 2489#define WM8996_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */ 2490#define WM8996_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */ 2491#define WM8996_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */ 2492#define WM8996_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */ 2493#define WM8996_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */ 2494 2495/* 2496 * R1092 (0x444) - DSP1 DRC (5) 2497 */ 2498#define WM8996_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */ 2499#define WM8996_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */ 2500#define WM8996_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */ 2501#define WM8996_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */ 2502#define WM8996_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */ 2503#define WM8996_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */ 2504 2505/* 2506 * R1152 (0x480) - DSP1 RX EQ Gains (1) 2507 */ 2508#define WM8996_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */ 2509#define WM8996_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */ 2510#define WM8996_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */ 2511#define WM8996_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */ 2512#define WM8996_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */ 2513#define WM8996_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */ 2514#define WM8996_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */ 2515#define WM8996_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */ 2516#define WM8996_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */ 2517#define WM8996_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */ 2518#define WM8996_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */ 2519#define WM8996_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */ 2520#define WM8996_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */ 2521 2522/* 2523 * R1153 (0x481) - DSP1 RX EQ Gains (2) 2524 */ 2525#define WM8996_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */ 2526#define WM8996_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */ 2527#define WM8996_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */ 2528#define WM8996_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */ 2529#define WM8996_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */ 2530#define WM8996_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */ 2531 2532/* 2533 * R1154 (0x482) - DSP1 RX EQ Band 1 A 2534 */ 2535#define WM8996_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */ 2536#define WM8996_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */ 2537#define WM8996_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */ 2538 2539/* 2540 * R1155 (0x483) - DSP1 RX EQ Band 1 B 2541 */ 2542#define WM8996_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */ 2543#define WM8996_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */ 2544#define WM8996_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */ 2545 2546/* 2547 * R1156 (0x484) - DSP1 RX EQ Band 1 PG 2548 */ 2549#define WM8996_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */ 2550#define WM8996_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */ 2551#define WM8996_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */ 2552 2553/* 2554 * R1157 (0x485) - DSP1 RX EQ Band 2 A 2555 */ 2556#define WM8996_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */ 2557#define WM8996_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */ 2558#define WM8996_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */ 2559 2560/* 2561 * R1158 (0x486) - DSP1 RX EQ Band 2 B 2562 */ 2563#define WM8996_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */ 2564#define WM8996_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */ 2565#define WM8996_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */ 2566 2567/* 2568 * R1159 (0x487) - DSP1 RX EQ Band 2 C 2569 */ 2570#define WM8996_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */ 2571#define WM8996_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */ 2572#define WM8996_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */ 2573 2574/* 2575 * R1160 (0x488) - DSP1 RX EQ Band 2 PG 2576 */ 2577#define WM8996_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */ 2578#define WM8996_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */ 2579#define WM8996_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */ 2580 2581/* 2582 * R1161 (0x489) - DSP1 RX EQ Band 3 A 2583 */ 2584#define WM8996_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */ 2585#define WM8996_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */ 2586#define WM8996_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */ 2587 2588/* 2589 * R1162 (0x48A) - DSP1 RX EQ Band 3 B 2590 */ 2591#define WM8996_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */ 2592#define WM8996_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */ 2593#define WM8996_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */ 2594 2595/* 2596 * R1163 (0x48B) - DSP1 RX EQ Band 3 C 2597 */ 2598#define WM8996_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */ 2599#define WM8996_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */ 2600#define WM8996_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */ 2601 2602/* 2603 * R1164 (0x48C) - DSP1 RX EQ Band 3 PG 2604 */ 2605#define WM8996_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */ 2606#define WM8996_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */ 2607#define WM8996_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */ 2608 2609/* 2610 * R1165 (0x48D) - DSP1 RX EQ Band 4 A 2611 */ 2612#define WM8996_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */ 2613#define WM8996_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */ 2614#define WM8996_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */ 2615 2616/* 2617 * R1166 (0x48E) - DSP1 RX EQ Band 4 B 2618 */ 2619#define WM8996_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */ 2620#define WM8996_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */ 2621#define WM8996_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */ 2622 2623/* 2624 * R1167 (0x48F) - DSP1 RX EQ Band 4 C 2625 */ 2626#define WM8996_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */ 2627#define WM8996_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */ 2628#define WM8996_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */ 2629 2630/* 2631 * R1168 (0x490) - DSP1 RX EQ Band 4 PG 2632 */ 2633#define WM8996_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */ 2634#define WM8996_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */ 2635#define WM8996_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */ 2636 2637/* 2638 * R1169 (0x491) - DSP1 RX EQ Band 5 A 2639 */ 2640#define WM8996_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */ 2641#define WM8996_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */ 2642#define WM8996_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */ 2643 2644/* 2645 * R1170 (0x492) - DSP1 RX EQ Band 5 B 2646 */ 2647#define WM8996_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */ 2648#define WM8996_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */ 2649#define WM8996_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */ 2650 2651/* 2652 * R1171 (0x493) - DSP1 RX EQ Band 5 PG 2653 */ 2654#define WM8996_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */ 2655#define WM8996_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */ 2656#define WM8996_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */ 2657 2658/* 2659 * R1280 (0x500) - DSP2 TX Left Volume 2660 */ 2661#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */ 2662#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ 2663#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ 2664#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ 2665#define WM8996_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */ 2666#define WM8996_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */ 2667#define WM8996_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */ 2668 2669/* 2670 * R1281 (0x501) - DSP2 TX Right Volume 2671 */ 2672#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */ 2673#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ 2674#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ 2675#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ 2676#define WM8996_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */ 2677#define WM8996_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */ 2678#define WM8996_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */ 2679 2680/* 2681 * R1282 (0x502) - DSP2 RX Left Volume 2682 */ 2683#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */ 2684#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ 2685#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ 2686#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ 2687#define WM8996_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */ 2688#define WM8996_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */ 2689#define WM8996_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */ 2690 2691/* 2692 * R1283 (0x503) - DSP2 RX Right Volume 2693 */ 2694#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */ 2695#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ 2696#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ 2697#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ 2698#define WM8996_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */ 2699#define WM8996_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */ 2700#define WM8996_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */ 2701 2702/* 2703 * R1296 (0x510) - DSP2 TX Filters 2704 */ 2705#define WM8996_DSP2TX_NF 0x2000 /* DSP2TX_NF */ 2706#define WM8996_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */ 2707#define WM8996_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */ 2708#define WM8996_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */ 2709#define WM8996_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */ 2710#define WM8996_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */ 2711#define WM8996_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */ 2712#define WM8996_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */ 2713#define WM8996_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */ 2714#define WM8996_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */ 2715#define WM8996_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */ 2716#define WM8996_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */ 2717#define WM8996_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */ 2718#define WM8996_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */ 2719#define WM8996_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */ 2720#define WM8996_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */ 2721#define WM8996_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */ 2722#define WM8996_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */ 2723 2724/* 2725 * R1312 (0x520) - DSP2 RX Filters (1) 2726 */ 2727#define WM8996_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */ 2728#define WM8996_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */ 2729#define WM8996_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */ 2730#define WM8996_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */ 2731#define WM8996_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */ 2732#define WM8996_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */ 2733#define WM8996_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */ 2734#define WM8996_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */ 2735#define WM8996_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */ 2736#define WM8996_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */ 2737#define WM8996_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */ 2738#define WM8996_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */ 2739#define WM8996_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */ 2740#define WM8996_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */ 2741#define WM8996_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */ 2742#define WM8996_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */ 2743 2744/* 2745 * R1313 (0x521) - DSP2 RX Filters (2) 2746 */ 2747#define WM8996_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */ 2748#define WM8996_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */ 2749#define WM8996_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */ 2750#define WM8996_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */ 2751#define WM8996_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */ 2752#define WM8996_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */ 2753#define WM8996_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */ 2754 2755/* 2756 * R1344 (0x540) - DSP2 DRC (1) 2757 */ 2758#define WM8996_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */ 2759#define WM8996_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */ 2760#define WM8996_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */ 2761#define WM8996_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */ 2762#define WM8996_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */ 2763#define WM8996_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */ 2764#define WM8996_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */ 2765#define WM8996_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */ 2766#define WM8996_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */ 2767#define WM8996_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */ 2768#define WM8996_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */ 2769#define WM8996_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */ 2770#define WM8996_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */ 2771#define WM8996_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */ 2772#define WM8996_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */ 2773#define WM8996_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */ 2774#define WM8996_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */ 2775#define WM8996_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */ 2776#define WM8996_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ 2777#define WM8996_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ 2778#define WM8996_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */ 2779#define WM8996_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */ 2780#define WM8996_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */ 2781#define WM8996_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */ 2782#define WM8996_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */ 2783#define WM8996_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */ 2784#define WM8996_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */ 2785#define WM8996_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */ 2786#define WM8996_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */ 2787#define WM8996_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */ 2788#define WM8996_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */ 2789#define WM8996_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */ 2790#define WM8996_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */ 2791#define WM8996_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */ 2792#define WM8996_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */ 2793#define WM8996_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */ 2794#define WM8996_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */ 2795#define WM8996_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */ 2796#define WM8996_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */ 2797#define WM8996_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */ 2798#define WM8996_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */ 2799#define WM8996_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */ 2800 2801/* 2802 * R1345 (0x541) - DSP2 DRC (2) 2803 */ 2804#define WM8996_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */ 2805#define WM8996_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */ 2806#define WM8996_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */ 2807#define WM8996_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */ 2808#define WM8996_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */ 2809#define WM8996_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */ 2810#define WM8996_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */ 2811#define WM8996_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */ 2812#define WM8996_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */ 2813#define WM8996_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */ 2814#define WM8996_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */ 2815#define WM8996_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */ 2816 2817/* 2818 * R1346 (0x542) - DSP2 DRC (3) 2819 */ 2820#define WM8996_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */ 2821#define WM8996_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */ 2822#define WM8996_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */ 2823#define WM8996_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */ 2824#define WM8996_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */ 2825#define WM8996_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */ 2826#define WM8996_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */ 2827#define WM8996_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */ 2828#define WM8996_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */ 2829#define WM8996_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */ 2830#define WM8996_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */ 2831#define WM8996_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */ 2832#define WM8996_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */ 2833#define WM8996_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */ 2834#define WM8996_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */ 2835#define WM8996_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */ 2836#define WM8996_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */ 2837#define WM8996_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */ 2838 2839/* 2840 * R1347 (0x543) - DSP2 DRC (4) 2841 */ 2842#define WM8996_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */ 2843#define WM8996_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */ 2844#define WM8996_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */ 2845#define WM8996_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */ 2846#define WM8996_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */ 2847#define WM8996_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */ 2848 2849/* 2850 * R1348 (0x544) - DSP2 DRC (5) 2851 */ 2852#define WM8996_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */ 2853#define WM8996_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */ 2854#define WM8996_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */ 2855#define WM8996_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */ 2856#define WM8996_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */ 2857#define WM8996_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */ 2858 2859/* 2860 * R1408 (0x580) - DSP2 RX EQ Gains (1) 2861 */ 2862#define WM8996_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */ 2863#define WM8996_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */ 2864#define WM8996_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */ 2865#define WM8996_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */ 2866#define WM8996_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */ 2867#define WM8996_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */ 2868#define WM8996_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */ 2869#define WM8996_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */ 2870#define WM8996_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */ 2871#define WM8996_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */ 2872#define WM8996_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */ 2873#define WM8996_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */ 2874#define WM8996_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */ 2875 2876/* 2877 * R1409 (0x581) - DSP2 RX EQ Gains (2) 2878 */ 2879#define WM8996_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */ 2880#define WM8996_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */ 2881#define WM8996_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */ 2882#define WM8996_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */ 2883#define WM8996_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */ 2884#define WM8996_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */ 2885 2886/* 2887 * R1410 (0x582) - DSP2 RX EQ Band 1 A 2888 */ 2889#define WM8996_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */ 2890#define WM8996_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */ 2891#define WM8996_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */ 2892 2893/* 2894 * R1411 (0x583) - DSP2 RX EQ Band 1 B 2895 */ 2896#define WM8996_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */ 2897#define WM8996_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */ 2898#define WM8996_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */ 2899 2900/* 2901 * R1412 (0x584) - DSP2 RX EQ Band 1 PG 2902 */ 2903#define WM8996_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */ 2904#define WM8996_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */ 2905#define WM8996_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */ 2906 2907/* 2908 * R1413 (0x585) - DSP2 RX EQ Band 2 A 2909 */ 2910#define WM8996_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */ 2911#define WM8996_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */ 2912#define WM8996_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */ 2913 2914/* 2915 * R1414 (0x586) - DSP2 RX EQ Band 2 B 2916 */ 2917#define WM8996_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */ 2918#define WM8996_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */ 2919#define WM8996_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */ 2920 2921/* 2922 * R1415 (0x587) - DSP2 RX EQ Band 2 C 2923 */ 2924#define WM8996_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */ 2925#define WM8996_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */ 2926#define WM8996_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */ 2927 2928/* 2929 * R1416 (0x588) - DSP2 RX EQ Band 2 PG 2930 */ 2931#define WM8996_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */ 2932#define WM8996_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */ 2933#define WM8996_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */ 2934 2935/* 2936 * R1417 (0x589) - DSP2 RX EQ Band 3 A 2937 */ 2938#define WM8996_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */ 2939#define WM8996_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */ 2940#define WM8996_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */ 2941 2942/* 2943 * R1418 (0x58A) - DSP2 RX EQ Band 3 B 2944 */ 2945#define WM8996_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */ 2946#define WM8996_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */ 2947#define WM8996_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */ 2948 2949/* 2950 * R1419 (0x58B) - DSP2 RX EQ Band 3 C 2951 */ 2952#define WM8996_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */ 2953#define WM8996_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */ 2954#define WM8996_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */ 2955 2956/* 2957 * R1420 (0x58C) - DSP2 RX EQ Band 3 PG 2958 */ 2959#define WM8996_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */ 2960#define WM8996_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */ 2961#define WM8996_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */ 2962 2963/* 2964 * R1421 (0x58D) - DSP2 RX EQ Band 4 A 2965 */ 2966#define WM8996_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */ 2967#define WM8996_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */ 2968#define WM8996_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */ 2969 2970/* 2971 * R1422 (0x58E) - DSP2 RX EQ Band 4 B 2972 */ 2973#define WM8996_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */ 2974#define WM8996_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */ 2975#define WM8996_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */ 2976 2977/* 2978 * R1423 (0x58F) - DSP2 RX EQ Band 4 C 2979 */ 2980#define WM8996_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */ 2981#define WM8996_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */ 2982#define WM8996_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */ 2983 2984/* 2985 * R1424 (0x590) - DSP2 RX EQ Band 4 PG 2986 */ 2987#define WM8996_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */ 2988#define WM8996_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */ 2989#define WM8996_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */ 2990 2991/* 2992 * R1425 (0x591) - DSP2 RX EQ Band 5 A 2993 */ 2994#define WM8996_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */ 2995#define WM8996_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */ 2996#define WM8996_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */ 2997 2998/* 2999 * R1426 (0x592) - DSP2 RX EQ Band 5 B 3000 */
3001#define WM8996_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */ 3002#define WM8996_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */ 3003#define WM8996_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */ 3004 3005/* 3006 * R1427 (0x593) - DSP2 RX EQ Band 5 PG 3007 */ 3008#define WM8996_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */ 3009#define WM8996_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */ 3010#define WM8996_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */ 3011 3012/* 3013 * R1536 (0x600) - DAC1 Mixer Volumes 3014 */ 3015#define WM8996_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ 3016#define WM8996_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ 3017#define WM8996_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ 3018#define WM8996_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ 3019#define WM8996_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ 3020#define WM8996_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ 3021 3022/* 3023 * R1537 (0x601) - DAC1 Left Mixer Routing 3024 */ 3025#define WM8996_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 3026#define WM8996_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 3027#define WM8996_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 3028#define WM8996_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 3029#define WM8996_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 3030#define WM8996_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 3031#define WM8996_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 3032#define WM8996_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 3033#define WM8996_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */ 3034#define WM8996_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */ 3035#define WM8996_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */ 3036#define WM8996_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */ 3037#define WM8996_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */ 3038#define WM8996_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */ 3039#define WM8996_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */ 3040#define WM8996_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */ 3041 3042/* 3043 * R1538 (0x602) - DAC1 Right Mixer Routing 3044 */ 3045#define WM8996_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 3046#define WM8996_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 3047#define WM8996_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 3048#define WM8996_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 3049#define WM8996_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 3050#define WM8996_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 3051#define WM8996_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 3052#define WM8996_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 3053#define WM8996_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */ 3054#define WM8996_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */ 3055#define WM8996_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */ 3056#define WM8996_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */ 3057#define WM8996_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */ 3058#define WM8996_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */ 3059#define WM8996_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */ 3060#define WM8996_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */ 3061 3062/* 3063 * R1539 (0x603) - DAC2 Mixer Volumes 3064 */ 3065#define WM8996_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ 3066#define WM8996_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ 3067#define WM8996_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ 3068#define WM8996_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ 3069#define WM8996_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ 3070#define WM8996_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ 3071 3072/* 3073 * R1540 (0x604) - DAC2 Left Mixer Routing 3074 */ 3075#define WM8996_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 3076#define WM8996_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 3077#define WM8996_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 3078#define WM8996_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 3079#define WM8996_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 3080#define WM8996_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 3081#define WM8996_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 3082#define WM8996_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 3083#define WM8996_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */ 3084#define WM8996_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */ 3085#define WM8996_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */ 3086#define WM8996_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */ 3087#define WM8996_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */ 3088#define WM8996_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */ 3089#define WM8996_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */ 3090#define WM8996_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */ 3091 3092/* 3093 * R1541 (0x605) - DAC2 Right Mixer Routing 3094 */ 3095#define WM8996_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 3096#define WM8996_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 3097#define WM8996_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 3098#define WM8996_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 3099#define WM8996_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 3100#define WM8996_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 3101#define WM8996_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 3102#define WM8996_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 3103#define WM8996_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */ 3104#define WM8996_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */ 3105#define WM8996_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */ 3106#define WM8996_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */ 3107#define WM8996_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */ 3108#define WM8996_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */ 3109#define WM8996_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */ 3110#define WM8996_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */ 3111 3112/* 3113 * R1542 (0x606) - DSP1 TX Left Mixer Routing 3114 */ 3115#define WM8996_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */ 3116#define WM8996_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */ 3117#define WM8996_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */ 3118#define WM8996_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */ 3119#define WM8996_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */ 3120#define WM8996_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */ 3121#define WM8996_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */ 3122#define WM8996_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */ 3123 3124/* 3125 * R1543 (0x607) - DSP1 TX Right Mixer Routing 3126 */ 3127#define WM8996_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */ 3128#define WM8996_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */ 3129#define WM8996_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */ 3130#define WM8996_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */ 3131#define WM8996_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */ 3132#define WM8996_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */ 3133#define WM8996_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */ 3134#define WM8996_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */ 3135 3136/* 3137 * R1544 (0x608) - DSP2 TX Left Mixer Routing 3138 */ 3139#define WM8996_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */ 3140#define WM8996_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */ 3141#define WM8996_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */ 3142#define WM8996_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */ 3143#define WM8996_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */ 3144#define WM8996_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */ 3145#define WM8996_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */ 3146#define WM8996_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */ 3147 3148/* 3149 * R1545 (0x609) - DSP2 TX Right Mixer Routing 3150 */ 3151#define WM8996_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */ 3152#define WM8996_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */ 3153#define WM8996_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */ 3154#define WM8996_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */ 3155#define WM8996_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */ 3156#define WM8996_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */ 3157#define WM8996_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */ 3158#define WM8996_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */ 3159 3160/* 3161 * R1546 (0x60A) - DSP TX Mixer Select 3162 */ 3163#define WM8996_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */ 3164#define WM8996_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */ 3165#define WM8996_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */ 3166#define WM8996_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */ 3167 3168/* 3169 * R1552 (0x610) - DAC Softmute 3170 */ 3171#define WM8996_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 3172#define WM8996_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 3173#define WM8996_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 3174#define WM8996_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 3175#define WM8996_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 3176#define WM8996_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 3177#define WM8996_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 3178#define WM8996_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 3179 3180/* 3181 * R1568 (0x620) - Oversampling 3182 */ 3183#define WM8996_SPK_OSR128 0x0008 /* SPK_OSR128 */ 3184#define WM8996_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */ 3185#define WM8996_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */ 3186#define WM8996_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */ 3187#define WM8996_DMIC_OSR64 0x0004 /* DMIC_OSR64 */ 3188#define WM8996_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */ 3189#define WM8996_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */ 3190#define WM8996_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */ 3191#define WM8996_ADC_OSR128 0x0002 /* ADC_OSR128 */ 3192#define WM8996_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 3193#define WM8996_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 3194#define WM8996_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 3195#define WM8996_DAC_OSR128 0x0001 /* DAC_OSR128 */ 3196#define WM8996_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 3197#define WM8996_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 3198#define WM8996_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 3199 3200/* 3201 * R1569 (0x621) - Sidetone 3202 */ 3203#define WM8996_ST_LPF 0x1000 /* ST_LPF */ 3204#define WM8996_ST_LPF_MASK 0x1000 /* ST_LPF */ 3205#define WM8996_ST_LPF_SHIFT 12 /* ST_LPF */ 3206#define WM8996_ST_LPF_WIDTH 1 /* ST_LPF */ 3207#define WM8996_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 3208#define WM8996_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 3209#define WM8996_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 3210#define WM8996_ST_HPF 0x0040 /* ST_HPF */ 3211#define WM8996_ST_HPF_MASK 0x0040 /* ST_HPF */ 3212#define WM8996_ST_HPF_SHIFT 6 /* ST_HPF */ 3213#define WM8996_ST_HPF_WIDTH 1 /* ST_HPF */ 3214#define WM8996_STR_SEL 0x0002 /* STR_SEL */ 3215#define WM8996_STR_SEL_MASK 0x0002 /* STR_SEL */ 3216#define WM8996_STR_SEL_SHIFT 1 /* STR_SEL */ 3217#define WM8996_STR_SEL_WIDTH 1 /* STR_SEL */ 3218#define WM8996_STL_SEL 0x0001 /* STL_SEL */ 3219#define WM8996_STL_SEL_MASK 0x0001 /* STL_SEL */ 3220#define WM8996_STL_SEL_SHIFT 0 /* STL_SEL */ 3221#define WM8996_STL_SEL_WIDTH 1 /* STL_SEL */ 3222 3223/* 3224 * R1792 (0x700) - GPIO 1 3225 */ 3226#define WM8996_GP1_DIR 0x8000 /* GP1_DIR */ 3227#define WM8996_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 3228#define WM8996_GP1_DIR_SHIFT 15 /* GP1_DIR */ 3229#define WM8996_GP1_DIR_WIDTH 1 /* GP1_DIR */ 3230#define WM8996_GP1_PU 0x4000 /* GP1_PU */ 3231#define WM8996_GP1_PU_MASK 0x4000 /* GP1_PU */ 3232#define WM8996_GP1_PU_SHIFT 14 /* GP1_PU */ 3233#define WM8996_GP1_PU_WIDTH 1 /* GP1_PU */ 3234#define WM8996_GP1_PD 0x2000 /* GP1_PD */ 3235#define WM8996_GP1_PD_MASK 0x2000 /* GP1_PD */ 3236#define WM8996_GP1_PD_SHIFT 13 /* GP1_PD */ 3237#define WM8996_GP1_PD_WIDTH 1 /* GP1_PD */ 3238#define WM8996_GP1_POL 0x0400 /* GP1_POL */ 3239#define WM8996_GP1_POL_MASK 0x0400 /* GP1_POL */ 3240#define WM8996_GP1_POL_SHIFT 10 /* GP1_POL */ 3241#define WM8996_GP1_POL_WIDTH 1 /* GP1_POL */ 3242#define WM8996_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 3243#define WM8996_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 3244#define WM8996_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 3245#define WM8996_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 3246#define WM8996_GP1_DB 0x0100 /* GP1_DB */ 3247#define WM8996_GP1_DB_MASK 0x0100 /* GP1_DB */ 3248#define WM8996_GP1_DB_SHIFT 8 /* GP1_DB */ 3249#define WM8996_GP1_DB_WIDTH 1 /* GP1_DB */ 3250#define WM8996_GP1_LVL 0x0040 /* GP1_LVL */ 3251#define WM8996_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 3252#define WM8996_GP1_LVL_SHIFT 6 /* GP1_LVL */ 3253#define WM8996_GP1_LVL_WIDTH 1 /* GP1_LVL */ 3254#define WM8996_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */ 3255#define WM8996_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */ 3256#define WM8996_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */ 3257 3258/* 3259 * R1793 (0x701) - GPIO 2 3260 */ 3261#define WM8996_GP2_DIR 0x8000 /* GP2_DIR */ 3262#define WM8996_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 3263#define WM8996_GP2_DIR_SHIFT 15 /* GP2_DIR */ 3264#define WM8996_GP2_DIR_WIDTH 1 /* GP2_DIR */ 3265#define WM8996_GP2_PU 0x4000 /* GP2_PU */ 3266#define WM8996_GP2_PU_MASK 0x4000 /* GP2_PU */ 3267#define WM8996_GP2_PU_SHIFT 14 /* GP2_PU */ 3268#define WM8996_GP2_PU_WIDTH 1 /* GP2_PU */ 3269#define WM8996_GP2_PD 0x2000 /* GP2_PD */ 3270#define WM8996_GP2_PD_MASK 0x2000 /* GP2_PD */ 3271#define WM8996_GP2_PD_SHIFT 13 /* GP2_PD */ 3272#define WM8996_GP2_PD_WIDTH 1 /* GP2_PD */ 3273#define WM8996_GP2_POL 0x0400 /* GP2_POL */ 3274#define WM8996_GP2_POL_MASK 0x0400 /* GP2_POL */ 3275#define WM8996_GP2_POL_SHIFT 10 /* GP2_POL */ 3276#define WM8996_GP2_POL_WIDTH 1 /* GP2_POL */ 3277#define WM8996_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 3278#define WM8996_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 3279#define WM8996_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 3280#define WM8996_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 3281#define WM8996_GP2_DB 0x0100 /* GP2_DB */ 3282#define WM8996_GP2_DB_MASK 0x0100 /* GP2_DB */ 3283#define WM8996_GP2_DB_SHIFT 8 /* GP2_DB */ 3284#define WM8996_GP2_DB_WIDTH 1 /* GP2_DB */ 3285#define WM8996_GP2_LVL 0x0040 /* GP2_LVL */ 3286#define WM8996_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3287#define WM8996_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3288#define WM8996_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3289#define WM8996_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */ 3290#define WM8996_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */ 3291#define WM8996_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */ 3292 3293/* 3294 * R1794 (0x702) - GPIO 3 3295 */ 3296#define WM8996_GP3_DIR 0x8000 /* GP3_DIR */ 3297#define WM8996_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 3298#define WM8996_GP3_DIR_SHIFT 15 /* GP3_DIR */ 3299#define WM8996_GP3_DIR_WIDTH 1 /* GP3_DIR */ 3300#define WM8996_GP3_PU 0x4000 /* GP3_PU */ 3301#define WM8996_GP3_PU_MASK 0x4000 /* GP3_PU */ 3302#define WM8996_GP3_PU_SHIFT 14 /* GP3_PU */ 3303#define WM8996_GP3_PU_WIDTH 1 /* GP3_PU */ 3304#define WM8996_GP3_PD 0x2000 /* GP3_PD */ 3305#define WM8996_GP3_PD_MASK 0x2000 /* GP3_PD */ 3306#define WM8996_GP3_PD_SHIFT 13 /* GP3_PD */ 3307#define WM8996_GP3_PD_WIDTH 1 /* GP3_PD */ 3308#define WM8996_GP3_POL 0x0400 /* GP3_POL */ 3309#define WM8996_GP3_POL_MASK 0x0400 /* GP3_POL */ 3310#define WM8996_GP3_POL_SHIFT 10 /* GP3_POL */ 3311#define WM8996_GP3_POL_WIDTH 1 /* GP3_POL */ 3312#define WM8996_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3313#define WM8996_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3314#define WM8996_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3315#define WM8996_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3316#define WM8996_GP3_DB 0x0100 /* GP3_DB */ 3317#define WM8996_GP3_DB_MASK 0x0100 /* GP3_DB */ 3318#define WM8996_GP3_DB_SHIFT 8 /* GP3_DB */ 3319#define WM8996_GP3_DB_WIDTH 1 /* GP3_DB */ 3320#define WM8996_GP3_LVL 0x0040 /* GP3_LVL */ 3321#define WM8996_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3322#define WM8996_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3323#define WM8996_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3324#define WM8996_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */ 3325#define WM8996_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */ 3326#define WM8996_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */ 3327 3328/* 3329 * R1795 (0x703) - GPIO 4 3330 */ 3331#define WM8996_GP4_DIR 0x8000 /* GP4_DIR */ 3332#define WM8996_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3333#define WM8996_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3334#define WM8996_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3335#define WM8996_GP4_PU 0x4000 /* GP4_PU */ 3336#define WM8996_GP4_PU_MASK 0x4000 /* GP4_PU */ 3337#define WM8996_GP4_PU_SHIFT 14 /* GP4_PU */ 3338#define WM8996_GP4_PU_WIDTH 1 /* GP4_PU */ 3339#define WM8996_GP4_PD 0x2000 /* GP4_PD */ 3340#define WM8996_GP4_PD_MASK 0x2000 /* GP4_PD */ 3341#define WM8996_GP4_PD_SHIFT 13 /* GP4_PD */ 3342#define WM8996_GP4_PD_WIDTH 1 /* GP4_PD */ 3343#define WM8996_GP4_POL 0x0400 /* GP4_POL */ 3344#define WM8996_GP4_POL_MASK 0x0400 /* GP4_POL */ 3345#define WM8996_GP4_POL_SHIFT 10 /* GP4_POL */ 3346#define WM8996_GP4_POL_WIDTH 1 /* GP4_POL */ 3347#define WM8996_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3348#define WM8996_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3349#define WM8996_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3350#define WM8996_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3351#define WM8996_GP4_DB 0x0100 /* GP4_DB */ 3352#define WM8996_GP4_DB_MASK 0x0100 /* GP4_DB */ 3353#define WM8996_GP4_DB_SHIFT 8 /* GP4_DB */ 3354#define WM8996_GP4_DB_WIDTH 1 /* GP4_DB */ 3355#define WM8996_GP4_LVL 0x0040 /* GP4_LVL */ 3356#define WM8996_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3357#define WM8996_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3358#define WM8996_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3359#define WM8996_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */ 3360#define WM8996_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */ 3361#define WM8996_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */ 3362 3363/* 3364 * R1796 (0x704) - GPIO 5 3365 */ 3366#define WM8996_GP5_DIR 0x8000 /* GP5_DIR */ 3367#define WM8996_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3368#define WM8996_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3369#define WM8996_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3370#define WM8996_GP5_PU 0x4000 /* GP5_PU */ 3371#define WM8996_GP5_PU_MASK 0x4000 /* GP5_PU */ 3372#define WM8996_GP5_PU_SHIFT 14 /* GP5_PU */ 3373#define WM8996_GP5_PU_WIDTH 1 /* GP5_PU */ 3374#define WM8996_GP5_PD 0x2000 /* GP5_PD */ 3375#define WM8996_GP5_PD_MASK 0x2000 /* GP5_PD */ 3376#define WM8996_GP5_PD_SHIFT 13 /* GP5_PD */ 3377#define WM8996_GP5_PD_WIDTH 1 /* GP5_PD */ 3378#define WM8996_GP5_POL 0x0400 /* GP5_POL */ 3379#define WM8996_GP5_POL_MASK 0x0400 /* GP5_POL */ 3380#define WM8996_GP5_POL_SHIFT 10 /* GP5_POL */ 3381#define WM8996_GP5_POL_WIDTH 1 /* GP5_POL */ 3382#define WM8996_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3383#define WM8996_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3384#define WM8996_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3385#define WM8996_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3386#define WM8996_GP5_DB 0x0100 /* GP5_DB */ 3387#define WM8996_GP5_DB_MASK 0x0100 /* GP5_DB */ 3388#define WM8996_GP5_DB_SHIFT 8 /* GP5_DB */ 3389#define WM8996_GP5_DB_WIDTH 1 /* GP5_DB */ 3390#define WM8996_GP5_LVL 0x0040 /* GP5_LVL */ 3391#define WM8996_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3392#define WM8996_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3393#define WM8996_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3394#define WM8996_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */ 3395#define WM8996_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */ 3396#define WM8996_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */ 3397 3398/* 3399 * R1824 (0x720) - Pull Control (1) 3400 */ 3401#define WM8996_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ 3402#define WM8996_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ 3403#define WM8996_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ 3404#define WM8996_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3405#define WM8996_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ 3406#define WM8996_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ 3407#define WM8996_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ 3408#define WM8996_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3409#define WM8996_MCLK2_PU 0x0200 /* MCLK2_PU */ 3410#define WM8996_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ 3411#define WM8996_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ 3412#define WM8996_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ 3413#define WM8996_MCLK2_PD 0x0100 /* MCLK2_PD */ 3414#define WM8996_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ 3415#define WM8996_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ 3416#define WM8996_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3417#define WM8996_MCLK1_PU 0x0080 /* MCLK1_PU */ 3418#define WM8996_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 3419#define WM8996_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 3420#define WM8996_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 3421#define WM8996_MCLK1_PD 0x0040 /* MCLK1_PD */ 3422#define WM8996_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 3423#define WM8996_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 3424#define WM8996_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3425#define WM8996_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 3426#define WM8996_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 3427#define WM8996_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 3428#define WM8996_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 3429#define WM8996_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 3430#define WM8996_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 3431#define WM8996_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 3432#define WM8996_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 3433#define WM8996_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 3434#define WM8996_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 3435#define WM8996_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 3436#define WM8996_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 3437#define WM8996_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 3438#define WM8996_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 3439#define WM8996_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 3440#define WM8996_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 3441#define WM8996_BCLK1_PU 0x0002 /* BCLK1_PU */ 3442#define WM8996_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 3443#define WM8996_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 3444#define WM8996_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 3445#define WM8996_BCLK1_PD 0x0001 /* BCLK1_PD */ 3446#define WM8996_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 3447#define WM8996_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 3448#define WM8996_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 3449 3450/* 3451 * R1825 (0x721) - Pull Control (2) 3452 */ 3453#define WM8996_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */ 3454#define WM8996_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */ 3455#define WM8996_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */ 3456#define WM8996_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3457#define WM8996_ADDR_PD 0x0040 /* ADDR_PD */ 3458#define WM8996_ADDR_PD_MASK 0x0040 /* ADDR_PD */ 3459#define WM8996_ADDR_PD_SHIFT 6 /* ADDR_PD */ 3460#define WM8996_ADDR_PD_WIDTH 1 /* ADDR_PD */ 3461#define WM8996_DACDAT2_PU 0x0020 /* DACDAT2_PU */ 3462#define WM8996_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */ 3463#define WM8996_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */ 3464#define WM8996_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */ 3465#define WM8996_DACDAT2_PD 0x0010 /* DACDAT2_PD */ 3466#define WM8996_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */ 3467#define WM8996_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */ 3468#define WM8996_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */ 3469#define WM8996_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */ 3470#define WM8996_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */ 3471#define WM8996_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */ 3472#define WM8996_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */ 3473#define WM8996_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */ 3474#define WM8996_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */ 3475#define WM8996_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */ 3476#define WM8996_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */ 3477#define WM8996_BCLK2_PU 0x0002 /* BCLK2_PU */ 3478#define WM8996_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */ 3479#define WM8996_BCLK2_PU_SHIFT 1 /* BCLK2_PU */ 3480#define WM8996_BCLK2_PU_WIDTH 1 /* BCLK2_PU */ 3481#define WM8996_BCLK2_PD 0x0001 /* BCLK2_PD */ 3482#define WM8996_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */ 3483#define WM8996_BCLK2_PD_SHIFT 0 /* BCLK2_PD */ 3484#define WM8996_BCLK2_PD_WIDTH 1 /* BCLK2_PD */ 3485 3486/* 3487 * R1840 (0x730) - Interrupt Status 1 3488 */ 3489#define WM8996_GP5_EINT 0x0010 /* GP5_EINT */ 3490#define WM8996_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3491#define WM8996_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3492#define WM8996_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3493#define WM8996_GP4_EINT 0x0008 /* GP4_EINT */ 3494#define WM8996_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3495#define WM8996_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3496#define WM8996_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3497#define WM8996_GP3_EINT 0x0004 /* GP3_EINT */ 3498#define WM8996_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3499#define WM8996_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3500#define WM8996_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3501#define WM8996_GP2_EINT 0x0002 /* GP2_EINT */ 3502#define WM8996_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3503#define WM8996_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3504#define WM8996_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3505#define WM8996_GP1_EINT 0x0001 /* GP1_EINT */ 3506#define WM8996_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3507#define WM8996_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3508#define WM8996_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3509 3510/* 3511 * R1841 (0x731) - Interrupt Status 2 3512 */ 3513#define WM8996_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ 3514#define WM8996_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ 3515#define WM8996_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ 3516#define WM8996_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ 3517#define WM8996_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ 3518#define WM8996_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ 3519#define WM8996_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ 3520#define WM8996_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ 3521#define WM8996_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ 3522#define WM8996_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ 3523#define WM8996_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ 3524#define WM8996_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 3525#define WM8996_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ 3526#define WM8996_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ 3527#define WM8996_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ 3528#define WM8996_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 3529#define WM8996_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */ 3530#define WM8996_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */ 3531#define WM8996_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */ 3532#define WM8996_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */ 3533#define WM8996_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */ 3534#define WM8996_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */ 3535#define WM8996_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */ 3536#define WM8996_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */ 3537#define WM8996_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */ 3538#define WM8996_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */ 3539#define WM8996_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */ 3540#define WM8996_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */ 3541#define WM8996_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ 3542#define WM8996_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ 3543#define WM8996_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ 3544#define WM8996_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 3545#define WM8996_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ 3546#define WM8996_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ 3547#define WM8996_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ 3548#define WM8996_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ 3549#define WM8996_MICD_EINT 0x0001 /* MICD_EINT */ 3550#define WM8996_MICD_EINT_MASK 0x0001 /* MICD_EINT */ 3551#define WM8996_MICD_EINT_SHIFT 0 /* MICD_EINT */ 3552#define WM8996_MICD_EINT_WIDTH 1 /* MICD_EINT */ 3553 3554/* 3555 * R1842 (0x732) - Interrupt Raw Status 2 3556 */ 3557#define WM8996_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ 3558#define WM8996_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ 3559#define WM8996_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ 3560#define WM8996_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ 3561#define WM8996_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ 3562#define WM8996_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ 3563#define WM8996_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ 3564#define WM8996_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ 3565#define WM8996_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ 3566#define WM8996_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ 3567#define WM8996_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ 3568#define WM8996_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 3569#define WM8996_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ 3570#define WM8996_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ 3571#define WM8996_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ 3572#define WM8996_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 3573#define WM8996_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */ 3574#define WM8996_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */ 3575#define WM8996_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */ 3576#define WM8996_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */ 3577#define WM8996_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */ 3578#define WM8996_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */ 3579#define WM8996_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */ 3580#define WM8996_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */ 3581#define WM8996_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */ 3582#define WM8996_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */ 3583#define WM8996_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */ 3584#define WM8996_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ 3585 3586/* 3587 * R1848 (0x738) - Interrupt Status 1 Mask 3588 */ 3589#define WM8996_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3590#define WM8996_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3591#define WM8996_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3592#define WM8996_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3593#define WM8996_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 3594#define WM8996_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 3595#define WM8996_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 3596#define WM8996_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 3597#define WM8996_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 3598#define WM8996_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 3599#define WM8996_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 3600#define WM8996_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 3601#define WM8996_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 3602#define WM8996_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 3603#define WM8996_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 3604#define WM8996_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 3605#define WM8996_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 3606#define WM8996_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 3607#define WM8996_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 3608#define WM8996_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 3609 3610/* 3611 * R1849 (0x739) - Interrupt Status 2 Mask 3612 */ 3613#define WM8996_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ 3614#define WM8996_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ 3615#define WM8996_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ 3616#define WM8996_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ 3617#define WM8996_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ 3618#define WM8996_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ 3619#define WM8996_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ 3620#define WM8996_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ 3621#define WM8996_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ 3622#define WM8996_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ 3623#define WM8996_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ 3624#define WM8996_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 3625#define WM8996_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ 3626#define WM8996_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ 3627#define WM8996_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ 3628#define WM8996_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 3629#define WM8996_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ 3630#define WM8996_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ 3631#define WM8996_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */ 3632#define WM8996_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */ 3633#define WM8996_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ 3634#define WM8996_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ 3635#define WM8996_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */ 3636#define WM8996_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */ 3637#define WM8996_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ 3638#define WM8996_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ 3639#define WM8996_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */ 3640#define WM8996_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */ 3641#define WM8996_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ 3642#define WM8996_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ 3643#define WM8996_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ 3644#define WM8996_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 3645#define WM8996_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ 3646#define WM8996_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ 3647#define WM8996_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ 3648#define WM8996_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ 3649#define WM8996_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ 3650#define WM8996_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ 3651#define WM8996_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ 3652#define WM8996_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ 3653 3654/* 3655 * R1856 (0x740) - Interrupt Control 3656 */ 3657#define WM8996_IM_IRQ 0x0001 /* IM_IRQ */ 3658#define WM8996_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 3659#define WM8996_IM_IRQ_SHIFT 0 /* IM_IRQ */ 3660#define WM8996_IM_IRQ_WIDTH 1 /* IM_IRQ */ 3661 3662/* 3663 * R2048 (0x800) - Left PDM Speaker 3664 */ 3665#define WM8996_SPKL_ENA 0x0010 /* SPKL_ENA */ 3666#define WM8996_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */ 3667#define WM8996_SPKL_ENA_SHIFT 4 /* SPKL_ENA */ 3668#define WM8996_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 3669#define WM8996_SPKL_MUTE 0x0008 /* SPKL_MUTE */ 3670#define WM8996_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */ 3671#define WM8996_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */ 3672#define WM8996_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ 3673#define WM8996_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */ 3674#define WM8996_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */ 3675#define WM8996_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */ 3676#define WM8996_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */ 3677#define WM8996_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */ 3678#define WM8996_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */ 3679#define WM8996_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */ 3680 3681/* 3682 * R2049 (0x801) - Right PDM Speaker 3683 */ 3684#define WM8996_SPKR_ENA 0x0010 /* SPKR_ENA */ 3685#define WM8996_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */ 3686#define WM8996_SPKR_ENA_SHIFT 4 /* SPKR_ENA */ 3687#define WM8996_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 3688#define WM8996_SPKR_MUTE 0x0008 /* SPKR_MUTE */ 3689#define WM8996_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */ 3690#define WM8996_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */ 3691#define WM8996_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ 3692#define WM8996_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */ 3693#define WM8996_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */ 3694#define WM8996_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */ 3695#define WM8996_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */ 3696#define WM8996_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */ 3697#define WM8996_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */ 3698#define WM8996_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */ 3699 3700/* 3701 * R2050 (0x802) - PDM Speaker Mute Sequence 3702 */ 3703#define WM8996_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */ 3704#define WM8996_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */ 3705#define WM8996_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */ 3706#define WM8996_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */ 3707#define WM8996_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */ 3708#define WM8996_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */ 3709#define WM8996_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */ 3710 3711/* 3712 * R2051 (0x803) - PDM Speaker Volume 3713 */ 3714#define WM8996_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */ 3715#define WM8996_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */ 3716#define WM8996_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */ 3717#define WM8996_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */ 3718#define WM8996_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */ 3719#define WM8996_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */ 3720 3721#endif 3722