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33#include <linux/init.h>
34#include <linux/io.h>
35#include <linux/module.h>
36#include <linux/interrupt.h>
37#include <linux/clk.h>
38#include <linux/device.h>
39#include <linux/delay.h>
40#include <linux/slab.h>
41#include <linux/of_address.h>
42#include <linux/of_irq.h>
43#include <linux/of_platform.h>
44
45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/initval.h>
49#include <sound/soc.h>
50#include <sound/dmaengine_pcm.h>
51
52#include "fsl_ssi.h"
53#include "imx-pcm.h"
54
55#ifdef PPC
56#define read_ssi(addr) in_be32(addr)
57#define write_ssi(val, addr) out_be32(addr, val)
58#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
59#else
60#define read_ssi(addr) readl(addr)
61#define write_ssi(val, addr) writel(val, addr)
62
63
64
65
66static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
67{
68 u32 val = readl(addr);
69 val = (val & ~clear) | set;
70 writel(val, addr);
71}
72#endif
73
74
75
76
77
78
79
80
81
82#define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
83 SNDRV_PCM_RATE_CONTINUOUS)
84
85
86
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96
97
98
99#ifdef __BIG_ENDIAN
100#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
103#else
104#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
107#endif
108
109
110#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
111 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
112 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
113 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
114 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
115
116
117
118
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120
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126
127
128
129
130
131struct fsl_ssi_private {
132 struct ccsr_ssi __iomem *ssi;
133 dma_addr_t ssi_phys;
134 unsigned int irq;
135 struct snd_pcm_substream *first_stream;
136 struct snd_pcm_substream *second_stream;
137 unsigned int fifo_depth;
138 struct snd_soc_dai_driver cpu_dai_drv;
139 struct device_attribute dev_attr;
140 struct platform_device *pdev;
141
142 bool new_binding;
143 bool ssi_on_imx;
144 bool imx_ac97;
145 bool use_dma;
146 struct clk *clk;
147 struct snd_dmaengine_dai_dma_data dma_params_tx;
148 struct snd_dmaengine_dai_dma_data dma_params_rx;
149 struct imx_dma_data filter_data_tx;
150 struct imx_dma_data filter_data_rx;
151 struct imx_pcm_fiq_params fiq_params;
152
153 struct {
154 unsigned int rfrc;
155 unsigned int tfrc;
156 unsigned int cmdau;
157 unsigned int cmddu;
158 unsigned int rxt;
159 unsigned int rdr1;
160 unsigned int rdr0;
161 unsigned int tde1;
162 unsigned int tde0;
163 unsigned int roe1;
164 unsigned int roe0;
165 unsigned int tue1;
166 unsigned int tue0;
167 unsigned int tfs;
168 unsigned int rfs;
169 unsigned int tls;
170 unsigned int rls;
171 unsigned int rff1;
172 unsigned int rff0;
173 unsigned int tfe1;
174 unsigned int tfe0;
175 } stats;
176
177 char name[1];
178};
179
180
181
182
183
184
185
186
187
188
189
190
191
192static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
193{
194 struct fsl_ssi_private *ssi_private = dev_id;
195 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
196 irqreturn_t ret = IRQ_NONE;
197 __be32 sisr;
198 __be32 sisr2 = 0;
199
200
201
202
203
204 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
205
206 if (sisr & CCSR_SSI_SISR_RFRC) {
207 ssi_private->stats.rfrc++;
208 sisr2 |= CCSR_SSI_SISR_RFRC;
209 ret = IRQ_HANDLED;
210 }
211
212 if (sisr & CCSR_SSI_SISR_TFRC) {
213 ssi_private->stats.tfrc++;
214 sisr2 |= CCSR_SSI_SISR_TFRC;
215 ret = IRQ_HANDLED;
216 }
217
218 if (sisr & CCSR_SSI_SISR_CMDAU) {
219 ssi_private->stats.cmdau++;
220 ret = IRQ_HANDLED;
221 }
222
223 if (sisr & CCSR_SSI_SISR_CMDDU) {
224 ssi_private->stats.cmddu++;
225 ret = IRQ_HANDLED;
226 }
227
228 if (sisr & CCSR_SSI_SISR_RXT) {
229 ssi_private->stats.rxt++;
230 ret = IRQ_HANDLED;
231 }
232
233 if (sisr & CCSR_SSI_SISR_RDR1) {
234 ssi_private->stats.rdr1++;
235 ret = IRQ_HANDLED;
236 }
237
238 if (sisr & CCSR_SSI_SISR_RDR0) {
239 ssi_private->stats.rdr0++;
240 ret = IRQ_HANDLED;
241 }
242
243 if (sisr & CCSR_SSI_SISR_TDE1) {
244 ssi_private->stats.tde1++;
245 ret = IRQ_HANDLED;
246 }
247
248 if (sisr & CCSR_SSI_SISR_TDE0) {
249 ssi_private->stats.tde0++;
250 ret = IRQ_HANDLED;
251 }
252
253 if (sisr & CCSR_SSI_SISR_ROE1) {
254 ssi_private->stats.roe1++;
255 sisr2 |= CCSR_SSI_SISR_ROE1;
256 ret = IRQ_HANDLED;
257 }
258
259 if (sisr & CCSR_SSI_SISR_ROE0) {
260 ssi_private->stats.roe0++;
261 sisr2 |= CCSR_SSI_SISR_ROE0;
262 ret = IRQ_HANDLED;
263 }
264
265 if (sisr & CCSR_SSI_SISR_TUE1) {
266 ssi_private->stats.tue1++;
267 sisr2 |= CCSR_SSI_SISR_TUE1;
268 ret = IRQ_HANDLED;
269 }
270
271 if (sisr & CCSR_SSI_SISR_TUE0) {
272 ssi_private->stats.tue0++;
273 sisr2 |= CCSR_SSI_SISR_TUE0;
274 ret = IRQ_HANDLED;
275 }
276
277 if (sisr & CCSR_SSI_SISR_TFS) {
278 ssi_private->stats.tfs++;
279 ret = IRQ_HANDLED;
280 }
281
282 if (sisr & CCSR_SSI_SISR_RFS) {
283 ssi_private->stats.rfs++;
284 ret = IRQ_HANDLED;
285 }
286
287 if (sisr & CCSR_SSI_SISR_TLS) {
288 ssi_private->stats.tls++;
289 ret = IRQ_HANDLED;
290 }
291
292 if (sisr & CCSR_SSI_SISR_RLS) {
293 ssi_private->stats.rls++;
294 ret = IRQ_HANDLED;
295 }
296
297 if (sisr & CCSR_SSI_SISR_RFF1) {
298 ssi_private->stats.rff1++;
299 ret = IRQ_HANDLED;
300 }
301
302 if (sisr & CCSR_SSI_SISR_RFF0) {
303 ssi_private->stats.rff0++;
304 ret = IRQ_HANDLED;
305 }
306
307 if (sisr & CCSR_SSI_SISR_TFE1) {
308 ssi_private->stats.tfe1++;
309 ret = IRQ_HANDLED;
310 }
311
312 if (sisr & CCSR_SSI_SISR_TFE0) {
313 ssi_private->stats.tfe0++;
314 ret = IRQ_HANDLED;
315 }
316
317
318 if (sisr2)
319 write_ssi(sisr2, &ssi->sisr);
320
321 return ret;
322}
323
324static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
325{
326 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
327 u8 i2s_mode;
328 u8 wm;
329 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
330
331 if (ssi_private->imx_ac97)
332 i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
333 else
334 i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
335
336
337
338
339
340 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
341
342
343
344
345
346
347
348 write_ssi_mask(&ssi->scr,
349 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
350 CCSR_SSI_SCR_TFR_CLK_DIS |
351 i2s_mode |
352 (synchronous ? CCSR_SSI_SCR_SYN : 0));
353
354 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
355 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
356 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
357
358 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
359 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
360 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376 if (ssi_private->use_dma)
377 wm = ssi_private->fifo_depth - 2;
378 else
379 wm = ssi_private->fifo_depth;
380
381 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
382 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
383 &ssi->sfcsr);
384
385
386
387
388
389
390 if (ssi_private->imx_ac97) {
391
392
393
394 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
395 &ssi->stccr);
396 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
397 &ssi->srccr);
398
399
400
401
402 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
403 &ssi->sacnt);
404 write_ssi(0xff, &ssi->saccdis);
405 write_ssi(0x300, &ssi->saccen);
406
407
408
409
410 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
411 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
412
413 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
414 }
415
416 return 0;
417}
418
419
420
421
422
423
424
425
426
427
428static int fsl_ssi_startup(struct snd_pcm_substream *substream,
429 struct snd_soc_dai *dai)
430{
431 struct snd_soc_pcm_runtime *rtd = substream->private_data;
432 struct fsl_ssi_private *ssi_private =
433 snd_soc_dai_get_drvdata(rtd->cpu_dai);
434 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
435
436
437
438
439
440 if (!ssi_private->first_stream) {
441 ssi_private->first_stream = substream;
442
443
444
445
446
447 if (!ssi_private->imx_ac97)
448 fsl_ssi_setup(ssi_private);
449 } else {
450 if (synchronous) {
451 struct snd_pcm_runtime *first_runtime =
452 ssi_private->first_stream->runtime;
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472 if (first_runtime->sample_bits) {
473 snd_pcm_hw_constraint_minmax(substream->runtime,
474 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
475 first_runtime->sample_bits,
476 first_runtime->sample_bits);
477 }
478 }
479
480 ssi_private->second_stream = substream;
481 }
482
483 return 0;
484}
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
500 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
501{
502 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
503 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
504 unsigned int sample_size =
505 snd_pcm_format_width(params_format(hw_params));
506 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
507 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
508
509
510
511
512
513 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
514 return 0;
515
516
517
518
519
520
521
522
523
524
525
526
527 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
528 ssi_private->cpu_dai_drv.symmetric_rates)
529 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
530 else
531 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
532
533 return 0;
534}
535
536
537
538
539
540
541
542
543
544
545static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
546 struct snd_soc_dai *dai)
547{
548 struct snd_soc_pcm_runtime *rtd = substream->private_data;
549 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
550 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
551 unsigned int sier_bits;
552
553
554
555
556
557
558
559
560
561 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
562 if (ssi_private->use_dma)
563 sier_bits = SIER_FLAGS;
564 else
565 sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
566 } else {
567 if (ssi_private->use_dma)
568 sier_bits = SIER_FLAGS;
569 else
570 sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
571 }
572
573 switch (cmd) {
574 case SNDRV_PCM_TRIGGER_START:
575 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
576 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
577 write_ssi_mask(&ssi->scr, 0,
578 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
579 else
580 write_ssi_mask(&ssi->scr, 0,
581 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
582 break;
583
584 case SNDRV_PCM_TRIGGER_STOP:
585 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
586 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
587 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
588 else
589 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
590
591 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
592 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
593 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
594 break;
595
596 default:
597 return -EINVAL;
598 }
599
600 write_ssi(sier_bits, &ssi->sier);
601
602 return 0;
603}
604
605
606
607
608
609
610static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
611 struct snd_soc_dai *dai)
612{
613 struct snd_soc_pcm_runtime *rtd = substream->private_data;
614 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
615
616 if (ssi_private->first_stream == substream)
617 ssi_private->first_stream = ssi_private->second_stream;
618
619 ssi_private->second_stream = NULL;
620}
621
622static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
623{
624 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
625
626 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
627 dai->playback_dma_data = &ssi_private->dma_params_tx;
628 dai->capture_dma_data = &ssi_private->dma_params_rx;
629 }
630
631 return 0;
632}
633
634static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
635 .startup = fsl_ssi_startup,
636 .hw_params = fsl_ssi_hw_params,
637 .shutdown = fsl_ssi_shutdown,
638 .trigger = fsl_ssi_trigger,
639};
640
641
642static struct snd_soc_dai_driver fsl_ssi_dai_template = {
643 .probe = fsl_ssi_dai_probe,
644 .playback = {
645
646 .channels_min = 2,
647 .channels_max = 2,
648 .rates = FSLSSI_I2S_RATES,
649 .formats = FSLSSI_I2S_FORMATS,
650 },
651 .capture = {
652 .channels_min = 2,
653 .channels_max = 2,
654 .rates = FSLSSI_I2S_RATES,
655 .formats = FSLSSI_I2S_FORMATS,
656 },
657 .ops = &fsl_ssi_dai_ops,
658};
659
660static const struct snd_soc_component_driver fsl_ssi_component = {
661 .name = "fsl-ssi",
662};
663
664
665
666
667
668
669
670static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
671 struct snd_soc_dai *dai)
672{
673 struct snd_soc_pcm_runtime *rtd = substream->private_data;
674 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
675 rtd->cpu_dai);
676 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
677
678 switch (cmd) {
679 case SNDRV_PCM_TRIGGER_START:
680 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
681 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
682 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
683 CCSR_SSI_SIER_TFE0_EN);
684 else
685 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
686 CCSR_SSI_SIER_RFF0_EN);
687 break;
688
689 case SNDRV_PCM_TRIGGER_STOP:
690 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
691 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
692 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
693 CCSR_SSI_SIER_TFE0_EN, 0);
694 else
695 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
696 CCSR_SSI_SIER_RFF0_EN, 0);
697 break;
698
699 default:
700 return -EINVAL;
701 }
702
703 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
704 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
705 else
706 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
707
708 return 0;
709}
710
711static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
712 .startup = fsl_ssi_startup,
713 .shutdown = fsl_ssi_shutdown,
714 .trigger = fsl_ssi_ac97_trigger,
715};
716
717static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
718 .ac97_control = 1,
719 .playback = {
720 .stream_name = "AC97 Playback",
721 .channels_min = 2,
722 .channels_max = 2,
723 .rates = SNDRV_PCM_RATE_8000_48000,
724 .formats = SNDRV_PCM_FMTBIT_S16_LE,
725 },
726 .capture = {
727 .stream_name = "AC97 Capture",
728 .channels_min = 2,
729 .channels_max = 2,
730 .rates = SNDRV_PCM_RATE_48000,
731 .formats = SNDRV_PCM_FMTBIT_S16_LE,
732 },
733 .ops = &fsl_ssi_ac97_dai_ops,
734};
735
736
737static struct fsl_ssi_private *fsl_ac97_data;
738
739static void fsl_ssi_ac97_init(void)
740{
741 fsl_ssi_setup(fsl_ac97_data);
742}
743
744static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
745 unsigned short val)
746{
747 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
748 unsigned int lreg;
749 unsigned int lval;
750
751 if (reg > 0x7f)
752 return;
753
754
755 lreg = reg << 12;
756 write_ssi(lreg, &ssi->sacadd);
757
758 lval = val << 4;
759 write_ssi(lval , &ssi->sacdat);
760
761 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
762 CCSR_SSI_SACNT_WR);
763 udelay(100);
764}
765
766static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
767 unsigned short reg)
768{
769 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
770
771 unsigned short val = -1;
772 unsigned int lreg;
773
774 lreg = (reg & 0x7f) << 12;
775 write_ssi(lreg, &ssi->sacadd);
776 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
777 CCSR_SSI_SACNT_RD);
778
779 udelay(100);
780
781 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
782
783 return val;
784}
785
786static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
787 .read = fsl_ssi_ac97_read,
788 .write = fsl_ssi_ac97_write,
789};
790
791
792
793
794
795#define SIER_SHOW(flag, name) \
796 do { \
797 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
798 length += sprintf(buf + length, #name "=%u\n", \
799 ssi_private->stats.name); \
800 } while (0)
801
802
803
804
805
806
807
808
809static ssize_t fsl_sysfs_ssi_show(struct device *dev,
810 struct device_attribute *attr, char *buf)
811{
812 struct fsl_ssi_private *ssi_private =
813 container_of(attr, struct fsl_ssi_private, dev_attr);
814 ssize_t length = 0;
815
816 SIER_SHOW(RFRC_EN, rfrc);
817 SIER_SHOW(TFRC_EN, tfrc);
818 SIER_SHOW(CMDAU_EN, cmdau);
819 SIER_SHOW(CMDDU_EN, cmddu);
820 SIER_SHOW(RXT_EN, rxt);
821 SIER_SHOW(RDR1_EN, rdr1);
822 SIER_SHOW(RDR0_EN, rdr0);
823 SIER_SHOW(TDE1_EN, tde1);
824 SIER_SHOW(TDE0_EN, tde0);
825 SIER_SHOW(ROE1_EN, roe1);
826 SIER_SHOW(ROE0_EN, roe0);
827 SIER_SHOW(TUE1_EN, tue1);
828 SIER_SHOW(TUE0_EN, tue0);
829 SIER_SHOW(TFS_EN, tfs);
830 SIER_SHOW(RFS_EN, rfs);
831 SIER_SHOW(TLS_EN, tls);
832 SIER_SHOW(RLS_EN, rls);
833 SIER_SHOW(RFF1_EN, rff1);
834 SIER_SHOW(RFF0_EN, rff0);
835 SIER_SHOW(TFE1_EN, tfe1);
836 SIER_SHOW(TFE0_EN, tfe0);
837
838 return length;
839}
840
841
842
843
844static void make_lowercase(char *s)
845{
846 char *p = s;
847 char c;
848
849 while ((c = *p)) {
850 if ((c >= 'A') && (c <= 'Z'))
851 *p = c + ('a' - 'A');
852 p++;
853 }
854}
855
856static int fsl_ssi_probe(struct platform_device *pdev)
857{
858 struct fsl_ssi_private *ssi_private;
859 int ret = 0;
860 struct device_attribute *dev_attr = NULL;
861 struct device_node *np = pdev->dev.of_node;
862 const char *p, *sprop;
863 const uint32_t *iprop;
864 struct resource res;
865 char name[64];
866 bool shared;
867 bool ac97 = false;
868
869
870
871
872
873 if (!of_device_is_available(np))
874 return -ENODEV;
875
876
877 sprop = of_get_property(np, "fsl,mode", NULL);
878 if (!sprop) {
879 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
880 return -EINVAL;
881 }
882 if (!strcmp(sprop, "ac97-slave")) {
883 ac97 = true;
884 } else if (strcmp(sprop, "i2s-slave")) {
885 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
886 return -ENODEV;
887 }
888
889
890 p = strrchr(np->full_name, '/') + 1;
891 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
892 GFP_KERNEL);
893 if (!ssi_private) {
894 dev_err(&pdev->dev, "could not allocate DAI object\n");
895 return -ENOMEM;
896 }
897
898 strcpy(ssi_private->name, p);
899
900 ssi_private->use_dma = !of_property_read_bool(np,
901 "fsl,fiq-stream-filter");
902
903 if (ac97) {
904 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
905 sizeof(fsl_ssi_ac97_dai));
906
907 fsl_ac97_data = ssi_private;
908 ssi_private->imx_ac97 = true;
909
910 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
911 } else {
912
913 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
914 sizeof(fsl_ssi_dai_template));
915 }
916 ssi_private->cpu_dai_drv.name = ssi_private->name;
917
918
919 ret = of_address_to_resource(np, 0, &res);
920 if (ret) {
921 dev_err(&pdev->dev, "could not determine device resources\n");
922 return ret;
923 }
924 ssi_private->ssi = of_iomap(np, 0);
925 if (!ssi_private->ssi) {
926 dev_err(&pdev->dev, "could not map device resources\n");
927 return -ENOMEM;
928 }
929 ssi_private->ssi_phys = res.start;
930
931 ssi_private->irq = irq_of_parse_and_map(np, 0);
932 if (!ssi_private->irq) {
933 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
934 return -ENXIO;
935 }
936
937
938 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
939 ssi_private->cpu_dai_drv.symmetric_rates = 1;
940
941
942 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
943 if (iprop)
944 ssi_private->fifo_depth = be32_to_cpup(iprop);
945 else
946
947 ssi_private->fifo_depth = 8;
948
949 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
950 u32 dma_events[2];
951 ssi_private->ssi_on_imx = true;
952
953 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
954 if (IS_ERR(ssi_private->clk)) {
955 ret = PTR_ERR(ssi_private->clk);
956 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
957 goto error_irqmap;
958 }
959 ret = clk_prepare_enable(ssi_private->clk);
960 if (ret) {
961 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
962 ret);
963 goto error_irqmap;
964 }
965
966
967
968
969
970 ssi_private->dma_params_tx.maxburst =
971 ssi_private->fifo_depth - 2;
972 ssi_private->dma_params_rx.maxburst =
973 ssi_private->fifo_depth - 2;
974 ssi_private->dma_params_tx.addr =
975 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
976 ssi_private->dma_params_rx.addr =
977 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
978 ssi_private->dma_params_tx.filter_data =
979 &ssi_private->filter_data_tx;
980 ssi_private->dma_params_rx.filter_data =
981 &ssi_private->filter_data_rx;
982 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
983 ssi_private->use_dma) {
984
985
986
987
988
989 ret = of_property_read_u32_array(pdev->dev.of_node,
990 "fsl,ssi-dma-events", dma_events, 2);
991 if (ret && ssi_private->use_dma) {
992 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
993 goto error_clk;
994 }
995 }
996
997 shared = of_device_is_compatible(of_get_parent(np),
998 "fsl,spba-bus");
999
1000 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1001 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1002 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1003 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1004 } else if (ssi_private->use_dma) {
1005
1006 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1007 fsl_ssi_isr, 0, ssi_private->name,
1008 ssi_private);
1009 if (ret < 0) {
1010 dev_err(&pdev->dev, "could not claim irq %u\n",
1011 ssi_private->irq);
1012 goto error_irqmap;
1013 }
1014 }
1015
1016
1017 dev_attr = &ssi_private->dev_attr;
1018 sysfs_attr_init(&dev_attr->attr);
1019 dev_attr->attr.name = "statistics";
1020 dev_attr->attr.mode = S_IRUGO;
1021 dev_attr->show = fsl_sysfs_ssi_show;
1022
1023 ret = device_create_file(&pdev->dev, dev_attr);
1024 if (ret) {
1025 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1026 ssi_private->dev_attr.attr.name);
1027 goto error_clk;
1028 }
1029
1030
1031 dev_set_drvdata(&pdev->dev, ssi_private);
1032
1033 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1034 &ssi_private->cpu_dai_drv, 1);
1035 if (ret) {
1036 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1037 goto error_dev;
1038 }
1039
1040 if (ssi_private->ssi_on_imx) {
1041 if (!ssi_private->use_dma) {
1042
1043
1044
1045
1046
1047
1048
1049
1050 ssi_private->fiq_params.irq = ssi_private->irq;
1051 ssi_private->fiq_params.base = ssi_private->ssi;
1052 ssi_private->fiq_params.dma_params_rx =
1053 &ssi_private->dma_params_rx;
1054 ssi_private->fiq_params.dma_params_tx =
1055 &ssi_private->dma_params_tx;
1056
1057 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1058 if (ret)
1059 goto error_dev;
1060 } else {
1061 ret = imx_pcm_dma_init(pdev);
1062 if (ret)
1063 goto error_dev;
1064 }
1065 }
1066
1067
1068
1069
1070
1071
1072 if (!of_get_property(np, "codec-handle", NULL)) {
1073 ssi_private->new_binding = true;
1074 goto done;
1075 }
1076
1077
1078
1079
1080
1081
1082 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1083
1084 p = strrchr(sprop, ',');
1085 if (p)
1086 sprop = p + 1;
1087 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1088 make_lowercase(name);
1089
1090 ssi_private->pdev =
1091 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1092 if (IS_ERR(ssi_private->pdev)) {
1093 ret = PTR_ERR(ssi_private->pdev);
1094 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1095 goto error_dai;
1096 }
1097
1098done:
1099 if (ssi_private->imx_ac97)
1100 fsl_ssi_ac97_init();
1101
1102 return 0;
1103
1104error_dai:
1105 if (ssi_private->ssi_on_imx)
1106 imx_pcm_dma_exit(pdev);
1107 snd_soc_unregister_component(&pdev->dev);
1108
1109error_dev:
1110 device_remove_file(&pdev->dev, dev_attr);
1111
1112error_clk:
1113 if (ssi_private->ssi_on_imx)
1114 clk_disable_unprepare(ssi_private->clk);
1115
1116error_irqmap:
1117 irq_dispose_mapping(ssi_private->irq);
1118
1119 return ret;
1120}
1121
1122static int fsl_ssi_remove(struct platform_device *pdev)
1123{
1124 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1125
1126 if (!ssi_private->new_binding)
1127 platform_device_unregister(ssi_private->pdev);
1128 if (ssi_private->ssi_on_imx)
1129 imx_pcm_dma_exit(pdev);
1130 snd_soc_unregister_component(&pdev->dev);
1131 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1132 if (ssi_private->ssi_on_imx)
1133 clk_disable_unprepare(ssi_private->clk);
1134 irq_dispose_mapping(ssi_private->irq);
1135
1136 return 0;
1137}
1138
1139static const struct of_device_id fsl_ssi_ids[] = {
1140 { .compatible = "fsl,mpc8610-ssi", },
1141 { .compatible = "fsl,imx21-ssi", },
1142 {}
1143};
1144MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1145
1146static struct platform_driver fsl_ssi_driver = {
1147 .driver = {
1148 .name = "fsl-ssi-dai",
1149 .owner = THIS_MODULE,
1150 .of_match_table = fsl_ssi_ids,
1151 },
1152 .probe = fsl_ssi_probe,
1153 .remove = fsl_ssi_remove,
1154};
1155
1156module_platform_driver(fsl_ssi_driver);
1157
1158MODULE_ALIAS("platform:fsl-ssi-dai");
1159MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1160MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1161MODULE_LICENSE("GPL v2");
1162