LXR linux/arch/arc/include/asm/arcregs.h

   1/*
   2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 */
   8
   9#ifndef _ASM_ARC_ARCREGS_H
  10#define _ASM_ARC_ARCREGS_H
  11
  12#ifdef __KERNEL__
  13
  14/* Build Configuration Registers */
  15#define ARC_REG_DCCMBASE_BCR    0x61    /* DCCM Base Addr */
  16#define ARC_REG_CRC_BCR         0x62
  17#define ARC_REG_DVFB_BCR        0x64
  18#define ARC_REG_EXTARITH_BCR    0x65
  19#define ARC_REG_VECBASE_BCR     0x68
  20#define ARC_REG_PERIBASE_BCR    0x69
  21#define ARC_REG_FP_BCR          0x6B    /* Single-Precision FPU */
  22#define ARC_REG_DPFP_BCR        0x6C    /* Dbl Precision FPU */
  23#define ARC_REG_DCCM_BCR        0x74    /* DCCM Present + SZ */
  24#define ARC_REG_TIMERS_BCR      0x75
  25#define ARC_REG_ICCM_BCR        0x78
  26#define ARC_REG_XY_MEM_BCR      0x79
  27#define ARC_REG_MAC_BCR         0x7a
  28#define ARC_REG_MUL_BCR         0x7b
  29#define ARC_REG_SWAP_BCR        0x7c
  30#define ARC_REG_NORM_BCR        0x7d
  31#define ARC_REG_MIXMAX_BCR      0x7e
  32#define ARC_REG_BARREL_BCR      0x7f
  33#define ARC_REG_D_UNCACH_BCR    0x6A
  34
  35/* status32 Bits Positions */
  36#define STATUS_AE_BIT           5       /* Exception active */
  37#define STATUS_DE_BIT           6       /* PC is in delay slot */
  38#define STATUS_U_BIT            7       /* User/Kernel mode */
  39#define STATUS_L_BIT            12      /* Loop inhibit */
  40
  41/* These masks correspond to the status word(STATUS_32) bits */
  42#define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
  43#define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
  44#define STATUS_U_MASK           (1<<STATUS_U_BIT)
  45#define STATUS_L_MASK           (1<<STATUS_L_BIT)
  46
  47/*
  48 * ECR: Exception Cause Reg bits-n-pieces
  49 * [23:16] = Exception Vector
  50 * [15: 8] = Exception Cause Code
  51 * [ 7: 0] = Exception Parameters (for certain types only)
  52 */
  53#define ECR_VEC_MASK                    0xff0000
  54#define ECR_CODE_MASK                   0x00ff00
  55#define ECR_PARAM_MASK                  0x0000ff
  56
  57/* Exception Cause Vector Values */
  58#define ECR_V_INSN_ERR                  0x02
  59#define ECR_V_MACH_CHK                  0x20
  60#define ECR_V_ITLB_MISS                 0x21
  61#define ECR_V_DTLB_MISS                 0x22
  62#define ECR_V_PROTV                     0x23
  63#define ECR_V_TRAP                      0x25
  64
  65/* Protection Violation Exception Cause Code Values */
  66#define ECR_C_PROTV_INST_FETCH          0x00
  67#define ECR_C_PROTV_LOAD                0x01
  68#define ECR_C_PROTV_STORE               0x02
  69#define ECR_C_PROTV_XCHG                0x03
  70#define ECR_C_PROTV_MISALIG_DATA        0x04
  71
  72#define ECR_C_BIT_PROTV_MISALIG_DATA    10
  73
  74/* Machine Check Cause Code Values */
  75#define ECR_C_MCHK_DUP_TLB              0x01
  76
  77/* DTLB Miss Exception Cause Code Values */
  78#define ECR_C_BIT_DTLB_LD_MISS          8
  79#define ECR_C_BIT_DTLB_ST_MISS          9
  80
  81/* Dummy ECR values for Interrupts */
  82#define event_IRQ1              0x0031abcd
  83#define event_IRQ2              0x0032abcd
  84
  85/* Auxiliary registers */
  86#define AUX_IDENTITY            4
  87#define AUX_INTR_VEC_BASE       0x25
  88
  89
  90/*
  91 * Floating Pt Registers
  92 * Status regs are read-only (build-time) so need not be saved/restored
  93 */
  94#define ARC_AUX_FP_STAT         0x300
  95#define ARC_AUX_DPFP_1L         0x301
  96#define ARC_AUX_DPFP_1H         0x302
  97#define ARC_AUX_DPFP_2L         0x303
  98#define ARC_AUX_DPFP_2H         0x304
  99#define ARC_AUX_DPFP_STAT       0x305
 100
 101#ifndef __ASSEMBLY__
 102
 103/*
 104 ******************************************************************
 105 *      Inline ASM macros to read/write AUX Regs
 106 *      Essentially invocation of lr/sr insns from "C"
 107 */
 108
 109#if 1
 110
 111#define read_aux_reg(reg)       __builtin_arc_lr(reg)
 112
 113/* gcc builtin sr needs reg param to be long immediate */
 114#define write_aux_reg(reg_immed, val)           \
 115                __builtin_arc_sr((unsigned int)val, reg_immed)
 116
 117#else
 118
 119#define read_aux_reg(reg)               \
 120({                                      \
 121        unsigned int __ret;             \
 122        __asm__ __volatile__(           \
 123        "       lr    %0, [%1]"         \
 124        : "=r"(__ret)                   \
 125        : "i"(reg));                    \
 126        __ret;                          \
 127})
 128
 129/*
 130 * Aux Reg address is specified as long immediate by caller
 131 * e.g.
 132 *    write_aux_reg(0x69, some_val);
 133 * This generates tightest code.
 134 */
 135#define write_aux_reg(reg_imm, val)     \
 136({                                      \
 137        __asm__ __volatile__(           \
 138        "       sr   %0, [%1]   \n"     \
 139        :                               \
 140        : "ir"(val), "i"(reg_imm));     \
 141})
 142
 143/*
 144 * Aux Reg address is specified in a variable
 145 *  * e.g.
 146 *      reg_num = 0x69
 147 *      write_aux_reg2(reg_num, some_val);
 148 * This has to generate glue code to load the reg num from
 149 *  memory to a reg hence not recommended.
 150 */
 151#define write_aux_reg2(reg_in_var, val)         \
 152({                                              \
 153        unsigned int tmp;                       \
 154                                                \
 155        __asm__ __volatile__(                   \
 156        "       ld   %0, [%2]   \n\t"           \
 157        "       sr   %1, [%0]   \n\t"           \
 158        : "=&r"(tmp)                            \
 159        : "r"(val), "memory"(&reg_in_var));     \
 160})
 161
 162#endif
 163
 164#define READ_BCR(reg, into)                             \
 165{                                                       \
 166        unsigned int tmp;                               \
 167        tmp = read_aux_reg(reg);                        \
 168        if (sizeof(tmp) == sizeof(into)) {              \
 169                into = *((typeof(into) *)&tmp);         \
 170        } else {                                        \
 171                extern void bogus_undefined(void);      \
 172                bogus_undefined();                      \
 173        }                                               \
 174}
 175
 176#define WRITE_BCR(reg, into)                            \
 177{                                                       \
 178        unsigned int tmp;                               \
 179        if (sizeof(tmp) == sizeof(into)) {              \
 180                tmp = (*(unsigned int *)(into));        \
 181                write_aux_reg(reg, tmp);                \
 182        } else  {                                       \
 183                extern void bogus_undefined(void);      \
 184                bogus_undefined();                      \
 185        }                                               \
 186}
 187
 188/* Helpers */
 189#define TO_KB(bytes)            ((bytes) >> 10)
 190#define TO_MB(bytes)            (TO_KB(bytes) >> 10)
 191#define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
 192#define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
 193
 194#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
 195/* These DPFP regs need to be saved/restored across ctx-sw */
 196struct arc_fpu {
 197        struct {
 198                unsigned int l, h;
 199        } aux_dpfp[2];
 200};
 201#endif
 202
 203/*
 204 ***************************************************************
 205 * Build Configuration Registers, with encoded hardware config
 206 */
 207struct bcr_identity {
 208#ifdef CONFIG_CPU_BIG_ENDIAN
 209        unsigned int chip_id:16, cpu_id:8, family:8;
 210#else
 211        unsigned int family:8, cpu_id:8, chip_id:16;
 212#endif
 213};
 214
 215#define EXTN_SWAP_VALID     0x1
 216#define EXTN_NORM_VALID     0x2
 217#define EXTN_MINMAX_VALID   0x2
 218#define EXTN_BARREL_VALID   0x2
 219
 220struct bcr_extn {
 221#ifdef CONFIG_CPU_BIG_ENDIAN
 222        unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
 223                     norm:2, swap:1;
 224#else
 225        unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
 226                     crc:1, pad:20;
 227#endif
 228};
 229
 230/* DSP Options Ref Manual */
 231struct bcr_extn_mac_mul {
 232#ifdef CONFIG_CPU_BIG_ENDIAN
 233        unsigned int pad:16, type:8, ver:8;
 234#else
 235        unsigned int ver:8, type:8, pad:16;
 236#endif
 237};
 238
 239struct bcr_extn_xymem {
 240#ifdef CONFIG_CPU_BIG_ENDIAN
 241        unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
 242#else
 243        unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
 244#endif
 245};
 246
 247struct bcr_perip {
 248#ifdef CONFIG_CPU_BIG_ENDIAN
 249        unsigned int start:8, pad2:8, sz:8, pad:8;
 250#else
 251        unsigned int pad:8, sz:8, pad2:8, start:8;
 252#endif
 253};
 254struct bcr_iccm {
 255#ifdef CONFIG_CPU_BIG_ENDIAN
 256        unsigned int base:16, pad:5, sz:3, ver:8;
 257#else
 258        unsigned int ver:8, sz:3, pad:5, base:16;
 259#endif
 260};
 261
 262/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
 263struct bcr_dccm_base {
 264#ifdef CONFIG_CPU_BIG_ENDIAN
 265        unsigned int addr:24, ver:8;
 266#else
 267        unsigned int ver:8, addr:24;
 268#endif
 269};
 270
 271/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
 272struct bcr_dccm {
 273#ifdef CONFIG_CPU_BIG_ENDIAN
 274        unsigned int res:21, sz:3, ver:8;
 275#else
 276        unsigned int ver:8, sz:3, res:21;
 277#endif
 278};
 279
 280/* Both SP and DP FPU BCRs have same format */
 281struct bcr_fp {
 282#ifdef CONFIG_CPU_BIG_ENDIAN
 283        unsigned int fast:1, ver:8;
 284#else
 285        unsigned int ver:8, fast:1;
 286#endif
 287};
 288
 289/*
 290 *******************************************************************
 291 * Generic structures to hold build configuration used at runtime
 292 */
 293
 294struct cpuinfo_arc_mmu {
 295        unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
 296};
 297
 298struct cpuinfo_arc_cache {
 299        unsigned int sz, line_len, assoc, ver;
 300};
 301
 302struct cpuinfo_arc_ccm {
 303        unsigned int base_addr, sz;
 304};
 305
 306struct cpuinfo_arc {
 307        struct cpuinfo_arc_cache icache, dcache;
 308        struct cpuinfo_arc_mmu mmu;
 309        struct bcr_identity core;
 310        unsigned int timers;
 311        unsigned int vec_base;
 312        unsigned int uncached_base;
 313        struct cpuinfo_arc_ccm iccm, dccm;
 314        struct bcr_extn extn;
 315        struct bcr_extn_xymem extn_xymem;
 316        struct bcr_extn_mac_mul extn_mac_mul;
 317        struct bcr_fp fp, dpfp;
 318};
 319
 320extern struct cpuinfo_arc cpuinfo_arc700[];
 321
 322#endif /* __ASEMBLY__ */
 323
 324#endif /* __KERNEL__ */
 325
 326#endif /* _ASM_ARC_ARCREGS_H */
 327