linux/arch/arm/mach-imx/iomux-mx3.h
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   1/*
   2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
   3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License
   7 * as published by the Free Software Foundation; either version 2
   8 * of the License, or (at your option) any later version.
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software
  16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17 * MA 02110-1301, USA.
  18 */
  19#ifndef __MACH_IOMUX_MX3_H__
  20#define __MACH_IOMUX_MX3_H__
  21
  22#include <linux/types.h>
  23/*
  24 * various IOMUX output functions
  25 */
  26
  27#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
  28#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
  29#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
  30#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
  31#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
  32#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
  33#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
  34#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
  35#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
  36#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
  37#define IOMUX_ICONFIG_FUNC  2           /* used as function */
  38#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
  39#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
  40
  41#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
  42#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
  43#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
  44#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
  45
  46/*
  47 * various IOMUX pad functions
  48 */
  49enum iomux_pad_config {
  50        PAD_CTL_NOLOOPBACK      = 0x0 << 9,
  51        PAD_CTL_LOOPBACK        = 0x1 << 9,
  52        PAD_CTL_PKE_NONE        = 0x0 << 8,
  53        PAD_CTL_PKE_ENABLE      = 0x1 << 8,
  54        PAD_CTL_PUE_KEEPER      = 0x0 << 7,
  55        PAD_CTL_PUE_PUD         = 0x1 << 7,
  56        PAD_CTL_100K_PD         = 0x0 << 5,
  57        PAD_CTL_100K_PU         = 0x1 << 5,
  58        PAD_CTL_47K_PU          = 0x2 << 5,
  59        PAD_CTL_22K_PU          = 0x3 << 5,
  60        PAD_CTL_HYS_CMOS        = 0x0 << 4,
  61        PAD_CTL_HYS_SCHMITZ     = 0x1 << 4,
  62        PAD_CTL_ODE_CMOS        = 0x0 << 3,
  63        PAD_CTL_ODE_OpenDrain   = 0x1 << 3,
  64        PAD_CTL_DRV_NORMAL      = 0x0 << 1,
  65        PAD_CTL_DRV_HIGH        = 0x1 << 1,
  66        PAD_CTL_DRV_MAX         = 0x2 << 1,
  67        PAD_CTL_SRE_SLOW        = 0x0 << 0,
  68        PAD_CTL_SRE_FAST        = 0x1 << 0
  69};
  70
  71/*
  72 * various IOMUX general purpose functions
  73 */
  74enum iomux_gp_func {
  75        MUX_PGP_FIRI                    = 1 << 0,
  76        MUX_DDR_MODE                    = 1 << 1,
  77        MUX_PGP_CSPI_BB                 = 1 << 2,
  78        MUX_PGP_ATA_1                   = 1 << 3,
  79        MUX_PGP_ATA_2                   = 1 << 4,
  80        MUX_PGP_ATA_3                   = 1 << 5,
  81        MUX_PGP_ATA_4                   = 1 << 6,
  82        MUX_PGP_ATA_5                   = 1 << 7,
  83        MUX_PGP_ATA_6                   = 1 << 8,
  84        MUX_PGP_ATA_7                   = 1 << 9,
  85        MUX_PGP_ATA_8                   = 1 << 10,
  86        MUX_PGP_UH2                     = 1 << 11,
  87        MUX_SDCTL_CSD0_SEL              = 1 << 12,
  88        MUX_SDCTL_CSD1_SEL              = 1 << 13,
  89        MUX_CSPI1_UART3                 = 1 << 14,
  90        MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
  91        MUX_TAMPER_DETECT_EN            = 1 << 16,
  92        MUX_PGP_USB_4WIRE               = 1 << 17,
  93        MUX_PGP_USB_COMMON              = 1 << 18,
  94        MUX_SDHC_MEMSTICK1              = 1 << 19,
  95        MUX_SDHC_MEMSTICK2              = 1 << 20,
  96        MUX_PGP_SPLL_BYP                = 1 << 21,
  97        MUX_PGP_UPLL_BYP                = 1 << 22,
  98        MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
  99        MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
 100        MUX_CSPI3_UART5_SEL             = 1 << 25,
 101        MUX_PGP_ATA_9                   = 1 << 26,
 102        MUX_PGP_USB_SUSPEND             = 1 << 27,
 103        MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
 104        MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
 105        MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
 106        MUX_CLKO_DDR_MODE               = 1 << 31,
 107};
 108
 109/*
 110 * setups a single pin:
 111 *      - reserves the pin so that it is not claimed by another driver
 112 *      - setups the iomux according to the configuration
 113 *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
 114 */
 115int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
 116/*
 117 * setups mutliple pins
 118 * convenient way to call the above function with tables
 119 */
 120int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
 121                const char *label);
 122
 123/*
 124 * releases a single pin:
 125 *      - make it available for a future use by another driver
 126 *      - frees the GPIO if the pin was configured as GPIO
 127 *      - DOES NOT reconfigure the IOMUX in its reset state
 128 */
 129void mxc_iomux_release_pin(unsigned int pin);
 130/*
 131 * releases multiple pins
 132 * convenvient way to call the above function with tables
 133 */
 134void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
 135
 136/*
 137 * This function enables/disables the general purpose function for a particular
 138 * signal.
 139 */
 140void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
 141
 142/*
 143 * This function only configures the iomux hardware.
 144 * It is called by the setup functions and should not be called directly anymore.
 145 * It is here visible for backward compatibility
 146 */
 147int mxc_iomux_mode(unsigned int pin_mode);
 148
 149#define IOMUX_PADNUM_MASK       0x1ff
 150#define IOMUX_GPIONUM_SHIFT     9
 151#define IOMUX_GPIONUM_MASK      (0xff << IOMUX_GPIONUM_SHIFT)
 152#define IOMUX_MODE_SHIFT        17
 153#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
 154
 155#define IOMUX_PIN(gpionum, padnum) \
 156        (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
 157         (padnum & IOMUX_PADNUM_MASK))
 158
 159#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
 160
 161#define IOMUX_TO_GPIO(iomux_pin) \
 162        ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
 163
 164/*
 165 * This enumeration is constructed based on the Section
 166 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
 167 * value is constructed based on the rules described above.
 168 */
 169
 170enum iomux_pins {
 171        MX31_PIN_TTM_PAD        = IOMUX_PIN(0xff,   0),
 172        MX31_PIN_CSPI3_SPI_RDY  = IOMUX_PIN(0xff,   1),
 173        MX31_PIN_CSPI3_SCLK     = IOMUX_PIN(0xff,   2),
 174        MX31_PIN_CSPI3_MISO     = IOMUX_PIN(0xff,   3),
 175        MX31_PIN_CSPI3_MOSI     = IOMUX_PIN(0xff,   4),
 176        MX31_PIN_CLKSS          = IOMUX_PIN(0xff,   5),
 177        MX31_PIN_CE_CONTROL     = IOMUX_PIN(0xff,   6),
 178        MX31_PIN_ATA_RESET_B    = IOMUX_PIN(95,     7),
 179        MX31_PIN_ATA_DMACK      = IOMUX_PIN(94,     8),
 180        MX31_PIN_ATA_DIOW       = IOMUX_PIN(93,     9),
 181        MX31_PIN_ATA_DIOR       = IOMUX_PIN(92,    10),
 182        MX31_PIN_ATA_CS1        = IOMUX_PIN(91,    11),
 183        MX31_PIN_ATA_CS0        = IOMUX_PIN(90,    12),
 184        MX31_PIN_SD1_DATA3      = IOMUX_PIN(63,    13),
 185        MX31_PIN_SD1_DATA2      = IOMUX_PIN(62,    14),
 186        MX31_PIN_SD1_DATA1      = IOMUX_PIN(61,    15),
 187        MX31_PIN_SD1_DATA0      = IOMUX_PIN(60,    16),
 188        MX31_PIN_SD1_CLK        = IOMUX_PIN(59,    17),
 189        MX31_PIN_SD1_CMD        = IOMUX_PIN(58,    18),
 190        MX31_PIN_D3_SPL         = IOMUX_PIN(0xff,  19),
 191        MX31_PIN_D3_CLS         = IOMUX_PIN(0xff,  20),
 192        MX31_PIN_D3_REV         = IOMUX_PIN(0xff,  21),
 193        MX31_PIN_CONTRAST       = IOMUX_PIN(0xff,  22),
 194        MX31_PIN_VSYNC3         = IOMUX_PIN(0xff,  23),
 195        MX31_PIN_READ           = IOMUX_PIN(0xff,  24),
 196        MX31_PIN_WRITE          = IOMUX_PIN(0xff,  25),
 197        MX31_PIN_PAR_RS         = IOMUX_PIN(0xff,  26),
 198        MX31_PIN_SER_RS         = IOMUX_PIN(89,    27),
 199        MX31_PIN_LCS1           = IOMUX_PIN(88,    28),
 200        MX31_PIN_LCS0           = IOMUX_PIN(87,    29),
 201        MX31_PIN_SD_D_CLK       = IOMUX_PIN(86,    30),
 202        MX31_PIN_SD_D_IO        = IOMUX_PIN(85,    31),
 203        MX31_PIN_SD_D_I         = IOMUX_PIN(84,    32),
 204        MX31_PIN_DRDY0          = IOMUX_PIN(0xff,  33),
 205        MX31_PIN_FPSHIFT        = IOMUX_PIN(0xff,  34),
 206        MX31_PIN_HSYNC          = IOMUX_PIN(0xff,  35),
 207        MX31_PIN_VSYNC0         = IOMUX_PIN(0xff,  36),
 208        MX31_PIN_LD17           = IOMUX_PIN(0xff,  37),
 209        MX31_PIN_LD16           = IOMUX_PIN(0xff,  38),
 210        MX31_PIN_LD15           = IOMUX_PIN(0xff,  39),
 211        MX31_PIN_LD14           = IOMUX_PIN(0xff,  40),
 212        MX31_PIN_LD13           = IOMUX_PIN(0xff,  41),
 213        MX31_PIN_LD12           = IOMUX_PIN(0xff,  42),
 214        MX31_PIN_LD11           = IOMUX_PIN(0xff,  43),
 215        MX31_PIN_LD10           = IOMUX_PIN(0xff,  44),
 216        MX31_PIN_LD9            = IOMUX_PIN(0xff,  45),
 217        MX31_PIN_LD8            = IOMUX_PIN(0xff,  46),
 218        MX31_PIN_LD7            = IOMUX_PIN(0xff,  47),
 219        MX31_PIN_LD6            = IOMUX_PIN(0xff,  48),
 220        MX31_PIN_LD5            = IOMUX_PIN(0xff,  49),
 221        MX31_PIN_LD4            = IOMUX_PIN(0xff,  50),
 222        MX31_PIN_LD3            = IOMUX_PIN(0xff,  51),
 223        MX31_PIN_LD2            = IOMUX_PIN(0xff,  52),
 224        MX31_PIN_LD1            = IOMUX_PIN(0xff,  53),
 225        MX31_PIN_LD0            = IOMUX_PIN(0xff,  54),
 226        MX31_PIN_USBH2_DATA1    = IOMUX_PIN(0xff,  55),
 227        MX31_PIN_USBH2_DATA0    = IOMUX_PIN(0xff,  56),
 228        MX31_PIN_USBH2_NXT      = IOMUX_PIN(0xff,  57),
 229        MX31_PIN_USBH2_STP      = IOMUX_PIN(0xff,  58),
 230        MX31_PIN_USBH2_DIR      = IOMUX_PIN(0xff,  59),
 231        MX31_PIN_USBH2_CLK      = IOMUX_PIN(0xff,  60),
 232        MX31_PIN_USBOTG_DATA7   = IOMUX_PIN(0xff,  61),
 233        MX31_PIN_USBOTG_DATA6   = IOMUX_PIN(0xff,  62),
 234        MX31_PIN_USBOTG_DATA5   = IOMUX_PIN(0xff,  63),
 235        MX31_PIN_USBOTG_DATA4   = IOMUX_PIN(0xff,  64),
 236        MX31_PIN_USBOTG_DATA3   = IOMUX_PIN(0xff,  65),
 237        MX31_PIN_USBOTG_DATA2   = IOMUX_PIN(0xff,  66),
 238        MX31_PIN_USBOTG_DATA1   = IOMUX_PIN(0xff,  67),
 239        MX31_PIN_USBOTG_DATA0   = IOMUX_PIN(0xff,  68),
 240        MX31_PIN_USBOTG_NXT     = IOMUX_PIN(0xff,  69),
 241        MX31_PIN_USBOTG_STP     = IOMUX_PIN(0xff,  70),
 242        MX31_PIN_USBOTG_DIR     = IOMUX_PIN(0xff,  71),
 243        MX31_PIN_USBOTG_CLK     = IOMUX_PIN(0xff,  72),
 244        MX31_PIN_USB_BYP        = IOMUX_PIN(31,    73),
 245        MX31_PIN_USB_OC         = IOMUX_PIN(30,    74),
 246        MX31_PIN_USB_PWR        = IOMUX_PIN(29,    75),
 247        MX31_PIN_SJC_MOD        = IOMUX_PIN(0xff,  76),
 248        MX31_PIN_DE_B           = IOMUX_PIN(0xff,  77),
 249        MX31_PIN_TRSTB          = IOMUX_PIN(0xff,  78),
 250        MX31_PIN_TDO            = IOMUX_PIN(0xff,  79),
 251        MX31_PIN_TDI            = IOMUX_PIN(0xff,  80),
 252        MX31_PIN_TMS            = IOMUX_PIN(0xff,  81),
 253        MX31_PIN_TCK            = IOMUX_PIN(0xff,  82),
 254        MX31_PIN_RTCK           = IOMUX_PIN(0xff,  83),
 255        MX31_PIN_KEY_COL7       = IOMUX_PIN(57,    84),
 256        MX31_PIN_KEY_COL6       = IOMUX_PIN(56,    85),
 257        MX31_PIN_KEY_COL5       = IOMUX_PIN(55,    86),
 258        MX31_PIN_KEY_COL4       = IOMUX_PIN(54,    87),
 259        MX31_PIN_KEY_COL3       = IOMUX_PIN(0xff,  88),
 260        MX31_PIN_KEY_COL2       = IOMUX_PIN(0xff,  89),
 261        MX31_PIN_KEY_COL1       = IOMUX_PIN(0xff,  90),
 262        MX31_PIN_KEY_COL0       = IOMUX_PIN(0xff,  91),
 263        MX31_PIN_KEY_ROW7       = IOMUX_PIN(53,    92),
 264        MX31_PIN_KEY_ROW6       = IOMUX_PIN(52,    93),
 265        MX31_PIN_KEY_ROW5       = IOMUX_PIN(51,    94),
 266        MX31_PIN_KEY_ROW4       = IOMUX_PIN(50,    95),
 267        MX31_PIN_KEY_ROW3       = IOMUX_PIN(0xff,  96),
 268        MX31_PIN_KEY_ROW2       = IOMUX_PIN(0xff,  97),
 269        MX31_PIN_KEY_ROW1       = IOMUX_PIN(0xff,  98),
 270        MX31_PIN_KEY_ROW0       = IOMUX_PIN(0xff,  99),
 271        MX31_PIN_BATT_LINE      = IOMUX_PIN(49,   100),
 272        MX31_PIN_CTS2           = IOMUX_PIN(0xff, 101),
 273        MX31_PIN_RTS2           = IOMUX_PIN(0xff, 102),
 274        MX31_PIN_TXD2           = IOMUX_PIN(28,   103),
 275        MX31_PIN_RXD2           = IOMUX_PIN(27,   104),
 276        MX31_PIN_DTR_DCE2       = IOMUX_PIN(48,   105),
 277        MX31_PIN_DCD_DTE1       = IOMUX_PIN(47,   106),
 278        MX31_PIN_RI_DTE1        = IOMUX_PIN(46,   107),
 279        MX31_PIN_DSR_DTE1       = IOMUX_PIN(45,   108),
 280        MX31_PIN_DTR_DTE1       = IOMUX_PIN(44,   109),
 281        MX31_PIN_DCD_DCE1       = IOMUX_PIN(43,   110),
 282        MX31_PIN_RI_DCE1        = IOMUX_PIN(42,   111),
 283        MX31_PIN_DSR_DCE1       = IOMUX_PIN(41,   112),
 284        MX31_PIN_DTR_DCE1       = IOMUX_PIN(40,   113),
 285        MX31_PIN_CTS1           = IOMUX_PIN(39,   114),
 286        MX31_PIN_RTS1           = IOMUX_PIN(38,   115),
 287        MX31_PIN_TXD1           = IOMUX_PIN(37,   116),
 288        MX31_PIN_RXD1           = IOMUX_PIN(36,   117),
 289        MX31_PIN_CSPI2_SPI_RDY  = IOMUX_PIN(0xff, 118),
 290        MX31_PIN_CSPI2_SCLK     = IOMUX_PIN(0xff, 119),
 291        MX31_PIN_CSPI2_SS2      = IOMUX_PIN(0xff, 120),
 292        MX31_PIN_CSPI2_SS1      = IOMUX_PIN(0xff, 121),
 293        MX31_PIN_CSPI2_SS0      = IOMUX_PIN(0xff, 122),
 294        MX31_PIN_CSPI2_MISO     = IOMUX_PIN(0xff, 123),
 295        MX31_PIN_CSPI2_MOSI     = IOMUX_PIN(0xff, 124),
 296        MX31_PIN_CSPI1_SPI_RDY  = IOMUX_PIN(0xff, 125),
 297        MX31_PIN_CSPI1_SCLK     = IOMUX_PIN(0xff, 126),
 298        MX31_PIN_CSPI1_SS2      = IOMUX_PIN(0xff, 127),
 299        MX31_PIN_CSPI1_SS1      = IOMUX_PIN(0xff, 128),
 300        MX31_PIN_CSPI1_SS0      = IOMUX_PIN(0xff, 129),
 301        MX31_PIN_CSPI1_MISO     = IOMUX_PIN(0xff, 130),
 302        MX31_PIN_CSPI1_MOSI     = IOMUX_PIN(0xff, 131),
 303        MX31_PIN_SFS6           = IOMUX_PIN(26,   132),
 304        MX31_PIN_SCK6           = IOMUX_PIN(25,   133),
 305        MX31_PIN_SRXD6          = IOMUX_PIN(24,   134),
 306        MX31_PIN_STXD6          = IOMUX_PIN(23,   135),
 307        MX31_PIN_SFS5           = IOMUX_PIN(0xff, 136),
 308        MX31_PIN_SCK5           = IOMUX_PIN(0xff, 137),
 309        MX31_PIN_SRXD5          = IOMUX_PIN(22,   138),
 310        MX31_PIN_STXD5          = IOMUX_PIN(21,   139),
 311        MX31_PIN_SFS4           = IOMUX_PIN(0xff, 140),
 312        MX31_PIN_SCK4           = IOMUX_PIN(0xff, 141),
 313        MX31_PIN_SRXD4          = IOMUX_PIN(20,   142),
 314        MX31_PIN_STXD4          = IOMUX_PIN(19,   143),
 315        MX31_PIN_SFS3           = IOMUX_PIN(0xff, 144),
 316        MX31_PIN_SCK3           = IOMUX_PIN(0xff, 145),
 317        MX31_PIN_SRXD3          = IOMUX_PIN(18,   146),
 318        MX31_PIN_STXD3          = IOMUX_PIN(17,   147),
 319        MX31_PIN_I2C_DAT        = IOMUX_PIN(0xff, 148),
 320        MX31_PIN_I2C_CLK        = IOMUX_PIN(0xff, 149),
 321        MX31_PIN_CSI_PIXCLK     = IOMUX_PIN(83,   150),
 322        MX31_PIN_CSI_HSYNC      = IOMUX_PIN(82,   151),
 323        MX31_PIN_CSI_VSYNC      = IOMUX_PIN(81,   152),
 324        MX31_PIN_CSI_MCLK       = IOMUX_PIN(80,   153),
 325        MX31_PIN_CSI_D15        = IOMUX_PIN(79,   154),
 326        MX31_PIN_CSI_D14        = IOMUX_PIN(78,   155),
 327        MX31_PIN_CSI_D13        = IOMUX_PIN(77,   156),
 328        MX31_PIN_CSI_D12        = IOMUX_PIN(76,   157),
 329        MX31_PIN_CSI_D11        = IOMUX_PIN(75,   158),
 330        MX31_PIN_CSI_D10        = IOMUX_PIN(74,   159),
 331        MX31_PIN_CSI_D9         = IOMUX_PIN(73,   160),
 332        MX31_PIN_CSI_D8         = IOMUX_PIN(72,   161),
 333        MX31_PIN_CSI_D7         = IOMUX_PIN(71,   162),
 334        MX31_PIN_CSI_D6         = IOMUX_PIN(70,   163),
 335        MX31_PIN_CSI_D5         = IOMUX_PIN(69,   164),
 336        MX31_PIN_CSI_D4         = IOMUX_PIN(68,   165),
 337        MX31_PIN_M_GRANT        = IOMUX_PIN(0xff, 166),
 338        MX31_PIN_M_REQUEST      = IOMUX_PIN(0xff, 167),
 339        MX31_PIN_PC_POE         = IOMUX_PIN(0xff, 168),
 340        MX31_PIN_PC_RW_B        = IOMUX_PIN(0xff, 169),
 341        MX31_PIN_IOIS16         = IOMUX_PIN(0xff, 170),
 342        MX31_PIN_PC_RST         = IOMUX_PIN(0xff, 171),
 343        MX31_PIN_PC_BVD2        = IOMUX_PIN(0xff, 172),
 344        MX31_PIN_PC_BVD1        = IOMUX_PIN(0xff, 173),
 345        MX31_PIN_PC_VS2         = IOMUX_PIN(0xff, 174),
 346        MX31_PIN_PC_VS1         = IOMUX_PIN(0xff, 175),
 347        MX31_PIN_PC_PWRON       = IOMUX_PIN(0xff, 176),
 348        MX31_PIN_PC_READY       = IOMUX_PIN(0xff, 177),
 349        MX31_PIN_PC_WAIT_B      = IOMUX_PIN(0xff, 178),
 350        MX31_PIN_PC_CD2_B       = IOMUX_PIN(0xff, 179),
 351        MX31_PIN_PC_CD1_B       = IOMUX_PIN(0xff, 180),
 352        MX31_PIN_D0             = IOMUX_PIN(0xff, 181),
 353        MX31_PIN_D1             = IOMUX_PIN(0xff, 182),
 354        MX31_PIN_D2             = IOMUX_PIN(0xff, 183),
 355        MX31_PIN_D3             = IOMUX_PIN(0xff, 184),
 356        MX31_PIN_D4             = IOMUX_PIN(0xff, 185),
 357        MX31_PIN_D5             = IOMUX_PIN(0xff, 186),
 358        MX31_PIN_D6             = IOMUX_PIN(0xff, 187),
 359        MX31_PIN_D7             = IOMUX_PIN(0xff, 188),
 360        MX31_PIN_D8             = IOMUX_PIN(0xff, 189),
 361        MX31_PIN_D9             = IOMUX_PIN(0xff, 190),
 362        MX31_PIN_D10            = IOMUX_PIN(0xff, 191),
 363        MX31_PIN_D11            = IOMUX_PIN(0xff, 192),
 364        MX31_PIN_D12            = IOMUX_PIN(0xff, 193),
 365        MX31_PIN_D13            = IOMUX_PIN(0xff, 194),
 366        MX31_PIN_D14            = IOMUX_PIN(0xff, 195),
 367        MX31_PIN_D15            = IOMUX_PIN(0xff, 196),
 368        MX31_PIN_NFRB           = IOMUX_PIN(16,   197),
 369        MX31_PIN_NFCE_B         = IOMUX_PIN(15,   198),
 370        MX31_PIN_NFWP_B         = IOMUX_PIN(14,   199),
 371        MX31_PIN_NFCLE          = IOMUX_PIN(13,   200),
 372        MX31_PIN_NFALE          = IOMUX_PIN(12,   201),
 373        MX31_PIN_NFRE_B         = IOMUX_PIN(11,   202),
 374        MX31_PIN_NFWE_B         = IOMUX_PIN(10,   203),
 375        MX31_PIN_SDQS3          = IOMUX_PIN(0xff, 204),
 376        MX31_PIN_SDQS2          = IOMUX_PIN(0xff, 205),
 377        MX31_PIN_SDQS1          = IOMUX_PIN(0xff, 206),
 378        MX31_PIN_SDQS0          = IOMUX_PIN(0xff, 207),
 379        MX31_PIN_SDCLK_B        = IOMUX_PIN(0xff, 208),
 380        MX31_PIN_SDCLK          = IOMUX_PIN(0xff, 209),
 381        MX31_PIN_SDCKE1         = IOMUX_PIN(0xff, 210),
 382        MX31_PIN_SDCKE0         = IOMUX_PIN(0xff, 211),
 383        MX31_PIN_SDWE           = IOMUX_PIN(0xff, 212),
 384        MX31_PIN_CAS            = IOMUX_PIN(0xff, 213),
 385        MX31_PIN_RAS            = IOMUX_PIN(0xff, 214),
 386        MX31_PIN_RW             = IOMUX_PIN(0xff, 215),
 387        MX31_PIN_BCLK           = IOMUX_PIN(0xff, 216),
 388        MX31_PIN_LBA            = IOMUX_PIN(0xff, 217),
 389        MX31_PIN_ECB            = IOMUX_PIN(0xff, 218),
 390        MX31_PIN_CS5            = IOMUX_PIN(0xff, 219),
 391        MX31_PIN_CS4            = IOMUX_PIN(0xff, 220),
 392        MX31_PIN_CS3            = IOMUX_PIN(0xff, 221),
 393        MX31_PIN_CS2            = IOMUX_PIN(0xff, 222),
 394        MX31_PIN_CS1            = IOMUX_PIN(0xff, 223),
 395        MX31_PIN_CS0            = IOMUX_PIN(0xff, 224),
 396        MX31_PIN_OE             = IOMUX_PIN(0xff, 225),
 397        MX31_PIN_EB1            = IOMUX_PIN(0xff, 226),
 398        MX31_PIN_EB0            = IOMUX_PIN(0xff, 227),
 399        MX31_PIN_DQM3           = IOMUX_PIN(0xff, 228),
 400        MX31_PIN_DQM2           = IOMUX_PIN(0xff, 229),
 401        MX31_PIN_DQM1           = IOMUX_PIN(0xff, 230),
 402        MX31_PIN_DQM0           = IOMUX_PIN(0xff, 231),
 403        MX31_PIN_SD31           = IOMUX_PIN(0xff, 232),
 404        MX31_PIN_SD30           = IOMUX_PIN(0xff, 233),
 405        MX31_PIN_SD29           = IOMUX_PIN(0xff, 234),
 406        MX31_PIN_SD28           = IOMUX_PIN(0xff, 235),
 407        MX31_PIN_SD27           = IOMUX_PIN(0xff, 236),
 408        MX31_PIN_SD26           = IOMUX_PIN(0xff, 237),
 409        MX31_PIN_SD25           = IOMUX_PIN(0xff, 238),
 410        MX31_PIN_SD24           = IOMUX_PIN(0xff, 239),
 411        MX31_PIN_SD23           = IOMUX_PIN(0xff, 240),
 412        MX31_PIN_SD22           = IOMUX_PIN(0xff, 241),
 413        MX31_PIN_SD21           = IOMUX_PIN(0xff, 242),
 414        MX31_PIN_SD20           = IOMUX_PIN(0xff, 243),
 415        MX31_PIN_SD19           = IOMUX_PIN(0xff, 244),
 416        MX31_PIN_SD18           = IOMUX_PIN(0xff, 245),
 417        MX31_PIN_SD17           = IOMUX_PIN(0xff, 246),
 418        MX31_PIN_SD16           = IOMUX_PIN(0xff, 247),
 419        MX31_PIN_SD15           = IOMUX_PIN(0xff, 248),
 420        MX31_PIN_SD14           = IOMUX_PIN(0xff, 249),
 421        MX31_PIN_SD13           = IOMUX_PIN(0xff, 250),
 422        MX31_PIN_SD12           = IOMUX_PIN(0xff, 251),
 423        MX31_PIN_SD11           = IOMUX_PIN(0xff, 252),
 424        MX31_PIN_SD10           = IOMUX_PIN(0xff, 253),
 425        MX31_PIN_SD9            = IOMUX_PIN(0xff, 254),
 426        MX31_PIN_SD8            = IOMUX_PIN(0xff, 255),
 427        MX31_PIN_SD7            = IOMUX_PIN(0xff, 256),
 428        MX31_PIN_SD6            = IOMUX_PIN(0xff, 257),
 429        MX31_PIN_SD5            = IOMUX_PIN(0xff, 258),
 430        MX31_PIN_SD4            = IOMUX_PIN(0xff, 259),
 431        MX31_PIN_SD3            = IOMUX_PIN(0xff, 260),
 432        MX31_PIN_SD2            = IOMUX_PIN(0xff, 261),
 433        MX31_PIN_SD1            = IOMUX_PIN(0xff, 262),
 434        MX31_PIN_SD0            = IOMUX_PIN(0xff, 263),
 435        MX31_PIN_SDBA0          = IOMUX_PIN(0xff, 264),
 436        MX31_PIN_SDBA1          = IOMUX_PIN(0xff, 265),
 437        MX31_PIN_A25            = IOMUX_PIN(0xff, 266),
 438        MX31_PIN_A24            = IOMUX_PIN(0xff, 267),
 439        MX31_PIN_A23            = IOMUX_PIN(0xff, 268),
 440        MX31_PIN_A22            = IOMUX_PIN(0xff, 269),
 441        MX31_PIN_A21            = IOMUX_PIN(0xff, 270),
 442        MX31_PIN_A20            = IOMUX_PIN(0xff, 271),
 443        MX31_PIN_A19            = IOMUX_PIN(0xff, 272),
 444        MX31_PIN_A18            = IOMUX_PIN(0xff, 273),
 445        MX31_PIN_A17            = IOMUX_PIN(0xff, 274),
 446        MX31_PIN_A16            = IOMUX_PIN(0xff, 275),
 447        MX31_PIN_A14            = IOMUX_PIN(0xff, 276),
 448        MX31_PIN_A15            = IOMUX_PIN(0xff, 277),
 449        MX31_PIN_A13            = IOMUX_PIN(0xff, 278),
 450        MX31_PIN_A12            = IOMUX_PIN(0xff, 279),
 451        MX31_PIN_A11            = IOMUX_PIN(0xff, 280),
 452        MX31_PIN_MA10           = IOMUX_PIN(0xff, 281),
 453        MX31_PIN_A10            = IOMUX_PIN(0xff, 282),
 454        MX31_PIN_A9             = IOMUX_PIN(0xff, 283),
 455        MX31_PIN_A8             = IOMUX_PIN(0xff, 284),
 456        MX31_PIN_A7             = IOMUX_PIN(0xff, 285),
 457        MX31_PIN_A6             = IOMUX_PIN(0xff, 286),
 458        MX31_PIN_A5             = IOMUX_PIN(0xff, 287),
 459        MX31_PIN_A4             = IOMUX_PIN(0xff, 288),
 460        MX31_PIN_A3             = IOMUX_PIN(0xff, 289),
 461        MX31_PIN_A2             = IOMUX_PIN(0xff, 290),
 462        MX31_PIN_A1             = IOMUX_PIN(0xff, 291),
 463        MX31_PIN_A0             = IOMUX_PIN(0xff, 292),
 464        MX31_PIN_VPG1           = IOMUX_PIN(0xff, 293),
 465        MX31_PIN_VPG0           = IOMUX_PIN(0xff, 294),
 466        MX31_PIN_DVFS1          = IOMUX_PIN(0xff, 295),
 467        MX31_PIN_DVFS0          = IOMUX_PIN(0xff, 296),
 468        MX31_PIN_VSTBY          = IOMUX_PIN(0xff, 297),
 469        MX31_PIN_POWER_FAIL     = IOMUX_PIN(0xff, 298),
 470        MX31_PIN_CKIL           = IOMUX_PIN(0xff, 299),
 471        MX31_PIN_BOOT_MODE4     = IOMUX_PIN(0xff, 300),
 472        MX31_PIN_BOOT_MODE3     = IOMUX_PIN(0xff, 301),
 473        MX31_PIN_BOOT_MODE2     = IOMUX_PIN(0xff, 302),
 474        MX31_PIN_BOOT_MODE1     = IOMUX_PIN(0xff, 303),
 475        MX31_PIN_BOOT_MODE0     = IOMUX_PIN(0xff, 304),
 476        MX31_PIN_CLKO           = IOMUX_PIN(0xff, 305),
 477        MX31_PIN_POR_B          = IOMUX_PIN(0xff, 306),
 478        MX31_PIN_RESET_IN_B     = IOMUX_PIN(0xff, 307),
 479        MX31_PIN_CKIH           = IOMUX_PIN(0xff, 308),
 480        MX31_PIN_SIMPD0         = IOMUX_PIN(35,   309),
 481        MX31_PIN_SRX0           = IOMUX_PIN(34,   310),
 482        MX31_PIN_STX0           = IOMUX_PIN(33,   311),
 483        MX31_PIN_SVEN0          = IOMUX_PIN(32,   312),
 484        MX31_PIN_SRST0          = IOMUX_PIN(67,   313),
 485        MX31_PIN_SCLK0          = IOMUX_PIN(66,   314),
 486        MX31_PIN_GPIO3_1        = IOMUX_PIN(65,   315),
 487        MX31_PIN_GPIO3_0        = IOMUX_PIN(64,   316),
 488        MX31_PIN_GPIO1_6        = IOMUX_PIN( 6,   317),
 489        MX31_PIN_GPIO1_5        = IOMUX_PIN( 5,   318),
 490        MX31_PIN_GPIO1_4        = IOMUX_PIN( 4,   319),
 491        MX31_PIN_GPIO1_3        = IOMUX_PIN( 3,   320),
 492        MX31_PIN_GPIO1_2        = IOMUX_PIN( 2,   321),
 493        MX31_PIN_GPIO1_1        = IOMUX_PIN( 1,   322),
 494        MX31_PIN_GPIO1_0        = IOMUX_PIN( 0,   323),
 495        MX31_PIN_PWMO           = IOMUX_PIN( 9,   324),
 496        MX31_PIN_WATCHDOG_RST   = IOMUX_PIN(0xff, 325),
 497        MX31_PIN_COMPARE        = IOMUX_PIN( 8,   326),
 498        MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
 499};
 500
 501#define PIN_MAX 327
 502#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
 503
 504/*
 505 * Convenience values for use with mxc_iomux_mode()
 506 *
 507 * Format here is MX31_PIN_(pin name)__(function)
 508 */
 509#define MX31_PIN_CSPI3_MOSI__RXD3       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
 510#define MX31_PIN_CSPI3_MISO__TXD3       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
 511#define MX31_PIN_CSPI3_SCLK__RTS3       IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1)
 512#define MX31_PIN_CSPI3_SPI_RDY__CTS3    IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
 513#define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
 514#define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
 515#define MX31_PIN_RTS1__SFS              IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
 516#define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
 517#define MX31_PIN_TXD1__SCK              IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
 518#define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
 519#define MX31_PIN_RXD1__STXDA            IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
 520#define MX31_PIN_DCD_DCE1__DCD_DCE1     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
 521#define MX31_PIN_RI_DCE1__RI_DCE1       IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
 522#define MX31_PIN_DSR_DCE1__DSR_DCE1     IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
 523#define MX31_PIN_DTR_DCE1__DTR_DCE1     IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
 524#define MX31_PIN_DTR_DCE1__SRXDA        IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
 525#define MX31_PIN_CTS2__CTS2             IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
 526#define MX31_PIN_RTS2__RTS2             IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
 527#define MX31_PIN_TXD2__TXD2             IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
 528#define MX31_PIN_RXD2__RXD2             IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
 529#define MX31_PIN_DCD_DTE1__DCD_DTE2     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
 530#define MX31_PIN_RI_DTE1__RI_DTE2       IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
 531#define MX31_PIN_DSR_DTE1__DSR_DTE2     IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
 532#define MX31_PIN_DTR_DTE1__DTR_DTE2     IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
 533#define MX31_PIN_PC_RST__CTS5           IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
 534#define MX31_PIN_PC_VS2__RTS5           IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
 535#define MX31_PIN_PC_BVD2__TXD5          IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
 536#define MX31_PIN_PC_BVD1__RXD5          IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2)
 537#define MX31_PIN_CSPI1_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
 538#define MX31_PIN_CSPI1_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
 539#define MX31_PIN_CSPI1_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
 540#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
 541#define MX31_PIN_CSPI1_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
 542#define MX31_PIN_CSPI1_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
 543#define MX31_PIN_CSPI1_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
 544#define MX31_PIN_CSPI2_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
 545#define MX31_PIN_CSPI2_MOSI__SCL        IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
 546#define MX31_PIN_CSPI2_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
 547#define MX31_PIN_CSPI2_MISO__SDA        IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
 548#define MX31_PIN_CSPI2_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
 549#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
 550#define MX31_PIN_CSPI2_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
 551#define MX31_PIN_CSPI2_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
 552#define MX31_PIN_CSPI2_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
 553#define MX31_PIN_CSPI3_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
 554#define MX31_PIN_CSPI3_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
 555#define MX31_PIN_CSPI3_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
 556#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
 557#define MX31_PIN_BATT_LINE__OWIRE       IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC)
 558#define MX31_PIN_CS4__CS4               IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC)
 559#define MX31_PIN_SD1_DATA3__SD1_DATA3   IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC)
 560#define MX31_PIN_SD1_DATA2__SD1_DATA2   IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC)
 561#define MX31_PIN_SD1_DATA1__SD1_DATA1   IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC)
 562#define MX31_PIN_SD1_DATA0__SD1_DATA0   IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
 563#define MX31_PIN_SD1_CLK__SD1_CLK       IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
 564#define MX31_PIN_SD1_CMD__SD1_CMD       IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
 565#define MX31_PIN_ATA_CS0__GPIO3_26      IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
 566#define MX31_PIN_ATA_CS1__GPIO3_27      IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
 567#define MX31_PIN_PC_PWRON__SD2_DATA3    IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
 568#define MX31_PIN_PC_VS1__SD2_DATA2      IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
 569#define MX31_PIN_PC_READY__SD2_DATA1    IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
 570#define MX31_PIN_PC_WAIT_B__SD2_DATA0   IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
 571#define MX31_PIN_PC_CD2_B__SD2_CLK      IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
 572#define MX31_PIN_PC_CD1_B__SD2_CMD      IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
 573#define MX31_PIN_ATA_DIOR__GPIO3_28     IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
 574#define MX31_PIN_ATA_DIOW__GPIO3_29     IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
 575#define MX31_PIN_LD0__LD0               IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
 576#define MX31_PIN_LD1__LD1               IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
 577#define MX31_PIN_LD2__LD2               IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
 578#define MX31_PIN_LD3__LD3               IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
 579#define MX31_PIN_LD4__LD4               IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
 580#define MX31_PIN_LD5__LD5               IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
 581#define MX31_PIN_LD6__LD6               IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
 582#define MX31_PIN_LD7__LD7               IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
 583#define MX31_PIN_LD8__LD8               IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
 584#define MX31_PIN_LD9__LD9               IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
 585#define MX31_PIN_LD10__LD10             IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
 586#define MX31_PIN_LD11__LD11             IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
 587#define MX31_PIN_LD12__LD12             IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
 588#define MX31_PIN_LD13__LD13             IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
 589#define MX31_PIN_LD14__LD14             IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
 590#define MX31_PIN_LD15__LD15             IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
 591#define MX31_PIN_LD16__LD16             IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
 592#define MX31_PIN_LD17__LD17             IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
 593#define MX31_PIN_VSYNC3__VSYNC3         IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
 594#define MX31_PIN_HSYNC__HSYNC           IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
 595#define MX31_PIN_FPSHIFT__FPSHIFT       IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
 596#define MX31_PIN_DRDY0__DRDY0           IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
 597#define MX31_PIN_D3_REV__D3_REV         IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
 598#define MX31_PIN_CONTRAST__CONTRAST     IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
 599#define MX31_PIN_D3_SPL__D3_SPL         IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
 600#define MX31_PIN_D3_CLS__D3_CLS         IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
 601#define MX31_PIN_LCS0__GPI03_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
 602#define MX31_PIN_GPIO1_1__GPIO          IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
 603#define MX31_PIN_I2C_CLK__SCL           IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
 604#define MX31_PIN_I2C_DAT__SDA           IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 605#define MX31_PIN_DCD_DTE1__I2C2_SDA     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
 606#define MX31_PIN_RI_DTE1__I2C2_SCL      IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
 607#define MX31_PIN_CSPI2_SS2__I2C3_SDA    IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
 608#define MX31_PIN_CSPI2_SCLK__I2C3_SCL   IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1)
 609#define MX31_PIN_CSI_D4__CSI_D4         IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
 610#define MX31_PIN_CSI_D5__CSI_D5         IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
 611#define MX31_PIN_CSI_D6__CSI_D6         IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
 612#define MX31_PIN_CSI_D7__CSI_D7         IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
 613#define MX31_PIN_CSI_D8__CSI_D8         IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
 614#define MX31_PIN_CSI_D9__CSI_D9         IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
 615#define MX31_PIN_CSI_D10__CSI_D10       IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
 616#define MX31_PIN_CSI_D11__CSI_D11       IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
 617#define MX31_PIN_CSI_D12__CSI_D12       IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
 618#define MX31_PIN_CSI_D13__CSI_D13       IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
 619#define MX31_PIN_CSI_D14__CSI_D14       IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
 620#define MX31_PIN_CSI_D15__CSI_D15       IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
 621#define MX31_PIN_CSI_HSYNC__CSI_HSYNC   IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
 622#define MX31_PIN_CSI_MCLK__CSI_MCLK     IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
 623#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
 624#define MX31_PIN_CSI_VSYNC__CSI_VSYNC   IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
 625#define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 626#define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 627#define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
 628#define MX31_PIN_CSI_D4__GPIO3_4        IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
 629#define MX31_PIN_CSI_D5__GPIO3_5        IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
 630#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0     IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
 631#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1     IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
 632#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2     IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
 633#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3     IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
 634#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4     IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
 635#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5     IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
 636#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6     IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
 637#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7     IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
 638#define MX31_PIN_USBOTG_CLK__USBOTG_CLK         IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
 639#define MX31_PIN_USBOTG_DIR__USBOTG_DIR         IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
 640#define MX31_PIN_USBOTG_NXT__USBOTG_NXT         IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
 641#define MX31_PIN_USBOTG_STP__USBOTG_STP         IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
 642#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM         IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
 643#define MX31_PIN_CSPI1_MISO__USBH1_RXDP         IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
 644#define MX31_PIN_CSPI1_SS0__USBH1_TXDM          IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
 645#define MX31_PIN_CSPI1_SS1__USBH1_TXDP          IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
 646#define MX31_PIN_CSPI1_SS2__USBH1_RCV           IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
 647#define MX31_PIN_CSPI1_SCLK__USBH1_OEB          IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
 648#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS        IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
 649#define MX31_PIN_SFS6__USBH1_SUSPEND    IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
 650#define MX31_PIN_NFRE_B__GPIO1_11       IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
 651#define MX31_PIN_NFALE__GPIO1_12        IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
 652#define MX31_PIN_USBH2_DATA0__USBH2_DATA0       IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
 653#define MX31_PIN_USBH2_DATA1__USBH2_DATA1       IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
 654#define MX31_PIN_STXD3__USBH2_DATA2     IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
 655#define MX31_PIN_SRXD3__USBH2_DATA3     IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
 656#define MX31_PIN_SCK3__USBH2_DATA4      IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
 657#define MX31_PIN_SFS3__USBH2_DATA5      IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
 658#define MX31_PIN_STXD6__USBH2_DATA6     IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
 659#define MX31_PIN_SRXD6__USBH2_DATA7     IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
 660#define MX31_PIN_USBH2_CLK__USBH2_CLK           IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
 661#define MX31_PIN_USBH2_DIR__USBH2_DIR           IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
 662#define MX31_PIN_USBH2_NXT__USBH2_NXT           IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
 663#define MX31_PIN_USBH2_STP__USBH2_STP           IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
 664#define MX31_PIN_SCK6__GPIO1_25         IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
 665#define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
 666#define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 667#define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
 668#define MX31_PIN_DCD_DTE1__I2C2_SDA     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
 669#define MX31_PIN_RI_DTE1__I2C2_SCL      IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
 670#define MX31_PIN_ATA_CS0__GPIO3_26      IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
 671#define MX31_PIN_ATA_CS1__GPIO3_27      IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
 672#define MX31_PIN_PC_PWRON__SD2_DATA3    IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
 673#define MX31_PIN_PC_VS1__SD2_DATA2      IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
 674#define MX31_PIN_PC_READY__SD2_DATA1    IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
 675#define MX31_PIN_PC_WAIT_B__SD2_DATA0   IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
 676#define MX31_PIN_PC_CD2_B__SD2_CLK      IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
 677#define MX31_PIN_PC_CD1_B__SD2_CMD      IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
 678#define MX31_PIN_ATA_DIOR__GPIO3_28     IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
 679#define MX31_PIN_ATA_DIOW__GPIO3_29     IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
 680#define MX31_PIN_CSI_D4__CSI_D4         IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
 681#define MX31_PIN_CSI_D5__CSI_D5         IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
 682#define MX31_PIN_CSI_D6__CSI_D6         IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
 683#define MX31_PIN_CSI_D7__CSI_D7         IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
 684#define MX31_PIN_CSI_D8__CSI_D8         IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
 685#define MX31_PIN_CSI_D9__CSI_D9         IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
 686#define MX31_PIN_CSI_D10__CSI_D10       IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
 687#define MX31_PIN_CSI_D11__CSI_D11       IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
 688#define MX31_PIN_CSI_D12__CSI_D12       IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
 689#define MX31_PIN_CSI_D13__CSI_D13       IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
 690#define MX31_PIN_CSI_D14__CSI_D14       IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
 691#define MX31_PIN_CSI_D15__CSI_D15       IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
 692#define MX31_PIN_CSI_HSYNC__CSI_HSYNC   IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
 693#define MX31_PIN_CSI_MCLK__CSI_MCLK     IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
 694#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
 695#define MX31_PIN_CSI_VSYNC__CSI_VSYNC   IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
 696#define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 697#define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 698#define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
 699#define MX31_PIN_GPIO1_0__GPIO1_0       IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
 700#define MX31_PIN_SVEN0__GPIO2_0         IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
 701#define MX31_PIN_STX0__GPIO2_1          IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
 702#define MX31_PIN_SRX0__GPIO2_2          IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
 703#define MX31_PIN_SIMPD0__GPIO2_3        IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
 704#define MX31_PIN_DTR_DCE1__GPIO2_8      IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
 705#define MX31_PIN_DSR_DCE1__GPIO2_9      IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
 706#define MX31_PIN_RI_DCE1__GPIO2_10      IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
 707#define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
 708#define MX31_PIN_STXD5__GPIO1_21        IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
 709#define MX31_PIN_SRXD5__GPIO1_22        IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
 710#define MX31_PIN_GPIO1_3__GPIO1_3       IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
 711#define MX31_PIN_CSPI2_SS1__CSPI3_SS1   IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
 712#define MX31_PIN_RTS1__GPIO2_6          IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
 713#define MX31_PIN_CTS1__GPIO2_7          IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
 714#define MX31_PIN_LCS0__GPIO3_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
 715#define MX31_PIN_STXD4__STXD4           IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
 716#define MX31_PIN_SRXD4__SRXD4           IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
 717#define MX31_PIN_SCK4__SCK4             IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
 718#define MX31_PIN_SFS4__SFS4             IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
 719#define MX31_PIN_STXD5__STXD5           IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
 720#define MX31_PIN_SRXD5__SRXD5           IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
 721#define MX31_PIN_SCK5__SCK5             IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
 722#define MX31_PIN_SFS5__SFS5             IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
 723#define MX31_PIN_KEY_ROW0_KEY_ROW0      IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
 724#define MX31_PIN_KEY_ROW1_KEY_ROW1      IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
 725#define MX31_PIN_KEY_ROW2_KEY_ROW2      IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
 726#define MX31_PIN_KEY_ROW3_KEY_ROW3      IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
 727#define MX31_PIN_KEY_ROW4_KEY_ROW4      IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
 728#define MX31_PIN_KEY_ROW4_GPIO          IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
 729#define MX31_PIN_KEY_ROW5_KEY_ROW5      IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
 730#define MX31_PIN_KEY_ROW6_KEY_ROW6      IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
 731#define MX31_PIN_KEY_ROW7_KEY_ROW7      IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
 732#define MX31_PIN_KEY_COL0_KEY_COL0      IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
 733#define MX31_PIN_KEY_COL1_KEY_COL1      IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
 734#define MX31_PIN_KEY_COL2_KEY_COL2      IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
 735#define MX31_PIN_KEY_COL3_KEY_COL3      IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
 736#define MX31_PIN_KEY_COL4_KEY_COL4      IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
 737#define MX31_PIN_KEY_COL5_KEY_COL5      IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
 738#define MX31_PIN_KEY_COL6_KEY_COL6      IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
 739#define MX31_PIN_KEY_COL7_KEY_COL7      IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
 740#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST     IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
 741
 742
 743/*
 744 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
 745 * cspi2_ss1, cspi1_ss0 cspi1_ss1
 746 */
 747
 748/*
 749 * This function configures the pad value for a IOMUX pin.
 750 */
 751void mxc_iomux_set_pad(enum iomux_pins, u32);
 752
 753#endif /* ifndef __MACH_IOMUX_MX3_H__ */
 754
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.