1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/clock.h>
26#include <mach/common.h>
27
28#define CPG_BASE 0xe6150000
29#define CPG_LEN 0x270
30
31#define SMSTPCR2 0xe6150138
32#define SMSTPCR3 0xe615013c
33#define SMSTPCR4 0xe6150140
34#define SMSTPCR5 0xe6150144
35
36#define FRQCRA 0xE6150000
37#define FRQCRB 0xE6150004
38#define FRQCRC 0xE61500E0
39#define VCLKCR1 0xE6150008
40#define VCLKCR2 0xE615000C
41#define VCLKCR3 0xE615001C
42#define VCLKCR4 0xE6150014
43#define VCLKCR5 0xE6150034
44#define ZBCKCR 0xE6150010
45#define SD0CKCR 0xE6150074
46#define SD1CKCR 0xE6150078
47#define SD2CKCR 0xE615007C
48#define MMC0CKCR 0xE6150240
49#define MMC1CKCR 0xE6150244
50#define FSIACKCR 0xE6150018
51#define FSIBCKCR 0xE6150090
52#define MPCKCR 0xe6150080
53#define SPUVCKCR 0xE6150094
54#define HSICKCR 0xE615026C
55#define M4CKCR 0xE6150098
56#define PLLECR 0xE61500D0
57#define PLL0CR 0xE61500D8
58#define PLL1CR 0xE6150028
59#define PLL2CR 0xE615002C
60#define PLL2SCR 0xE61501F4
61#define PLL2HCR 0xE61501E4
62#define CKSCR 0xE61500C0
63
64#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
65
66static struct clk_mapping cpg_mapping = {
67 .phys = CPG_BASE,
68 .len = CPG_LEN,
69};
70
71static struct clk extalr_clk = {
72 .rate = 32768,
73 .mapping = &cpg_mapping,
74};
75
76static struct clk extal1_clk = {
77 .rate = 26000000,
78 .mapping = &cpg_mapping,
79};
80
81static struct clk extal2_clk = {
82 .rate = 48000000,
83 .mapping = &cpg_mapping,
84};
85
86static struct sh_clk_ops followparent_clk_ops = {
87 .recalc = followparent_recalc,
88};
89
90static struct clk main_clk = {
91
92 .ops = &followparent_clk_ops,
93};
94
95SH_CLK_RATIO(div2, 1, 2);
96SH_CLK_RATIO(div4, 1, 4);
97
98SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
99SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
100SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
101SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
102
103
104static struct clk fsiack_clk = {
105};
106
107static struct clk fsibck_clk = {
108};
109
110
111
112
113static struct clk *pll_parent_main[] = {
114 [0] = &main_clk,
115 [1] = &main_div2_clk
116};
117
118static struct clk *pll_parent_main_extal[8] = {
119 [0] = &main_div2_clk,
120 [1] = &extal2_div2_clk,
121 [3] = &extal2_div4_clk,
122 [4] = &main_clk,
123 [5] = &extal2_clk,
124};
125
126static unsigned long pll_recalc(struct clk *clk)
127{
128 unsigned long mult = 1;
129
130 if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
131 mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
132
133 return clk->parent->rate * mult;
134}
135
136static int pll_set_parent(struct clk *clk, struct clk *parent)
137{
138 u32 val;
139 int i, ret;
140
141 if (!clk->parent_table || !clk->parent_num)
142 return -EINVAL;
143
144
145 for (i = 0; i < clk->parent_num; i++)
146 if (clk->parent_table[i] == parent)
147 break;
148
149 if (i == clk->parent_num)
150 return -ENODEV;
151
152 ret = clk_reparent(clk, parent);
153 if (ret < 0)
154 return ret;
155
156 val = ioread32(clk->mapped_reg) &
157 ~(((1 << clk->src_width) - 1) << clk->src_shift);
158
159 iowrite32(val | i << clk->src_shift, clk->mapped_reg);
160
161 return 0;
162}
163
164static struct sh_clk_ops pll_clk_ops = {
165 .recalc = pll_recalc,
166 .set_parent = pll_set_parent,
167};
168
169#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
170 static struct clk name = { \
171 .ops = &pll_clk_ops, \
172 .flags = CLK_ENABLE_ON_INIT, \
173 .parent = p, \
174 .parent_table = pt, \
175 .parent_num = ARRAY_SIZE(pt), \
176 .src_width = w, \
177 .src_shift = s, \
178 .enable_reg = (void __iomem *)reg, \
179 .enable_bit = e, \
180 .mapping = &cpg_mapping, \
181 }
182
183PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
184PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
185PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
186PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
187PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
188
189SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
190
191static atomic_t frqcr_lock;
192
193
194static bool frqcr_kick_check(struct clk *clk)
195{
196 return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
197}
198
199static int frqcr_kick_do(struct clk *clk)
200{
201 int i;
202
203
204 iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
205 for (i = 1000; i; i--)
206 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
207 cpu_relax();
208 else
209 return 0;
210
211 return -ETIMEDOUT;
212}
213
214static int zclk_set_rate(struct clk *clk, unsigned long rate)
215{
216 void __iomem *frqcrc;
217 int ret;
218 unsigned long step, p_rate;
219 u32 val;
220
221 if (!clk->parent || !__clk_get(clk->parent))
222 return -ENODEV;
223
224 if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
225 ret = -EBUSY;
226 goto done;
227 }
228
229
230
231
232
233
234
235 p_rate = clk_get_rate(clk->parent);
236 if (rate == p_rate) {
237 val = 0;
238 } else {
239 step = DIV_ROUND_CLOSEST(p_rate, 32);
240
241 if (rate > p_rate || rate < step) {
242 ret = -EINVAL;
243 goto done;
244 }
245
246 val = 32 - rate / step;
247 }
248
249 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
250
251 iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
252 (val << clk->enable_bit), frqcrc);
253
254 ret = frqcr_kick_do(clk);
255
256done:
257 atomic_dec(&frqcr_lock);
258 __clk_put(clk->parent);
259 return ret;
260}
261
262static long zclk_round_rate(struct clk *clk, unsigned long rate)
263{
264
265
266
267
268
269
270
271
272
273
274 unsigned long step, mul_min, mul_max, rate_min, rate_max;
275
276 rate_max = clk_get_rate(clk->parent);
277
278
279 if (rate >= rate_max)
280 return rate_max;
281
282 step = DIV_ROUND_CLOSEST(rate_max, 32);
283
284 if (step >= rate)
285 return step;
286
287 mul_min = rate / step;
288 mul_max = DIV_ROUND_UP(rate, step);
289 rate_min = step * mul_min;
290 if (mul_max == mul_min)
291 return rate_min;
292
293 rate_max = step * mul_max;
294
295 if (rate_max - rate < rate - rate_min)
296 return rate_max;
297
298 return rate_min;
299}
300
301static unsigned long zclk_recalc(struct clk *clk)
302{
303 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
304 unsigned int max = clk->div_mask + 1;
305 unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
306 clk->div_mask);
307
308 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
309 (max - val);
310}
311
312static struct sh_clk_ops zclk_ops = {
313 .recalc = zclk_recalc,
314 .set_rate = zclk_set_rate,
315 .round_rate = zclk_round_rate,
316};
317
318static struct clk z_clk = {
319 .parent = &pll0_clk,
320 .div_mask = 0x1f,
321 .enable_bit = 8,
322
323 .enable_reg = (void __iomem *)FRQCRB,
324 .ops = &zclk_ops,
325};
326
327
328
329
330
331SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
332
333static struct clk z2_clk = {
334 .parent = &pll0_div2_clk,
335 .div_mask = 0x1f,
336 .enable_bit = 0,
337
338 .enable_reg = (void __iomem *)FRQCRB,
339 .ops = &zclk_ops,
340};
341
342static struct clk *main_clks[] = {
343 &extalr_clk,
344 &extal1_clk,
345 &extal1_div2_clk,
346 &extal2_clk,
347 &extal2_div2_clk,
348 &extal2_div4_clk,
349 &main_clk,
350 &main_div2_clk,
351 &fsiack_clk,
352 &fsibck_clk,
353 &pll0_clk,
354 &pll1_clk,
355 &pll1_div2_clk,
356 &pll2_clk,
357 &pll2s_clk,
358 &pll2h_clk,
359 &z_clk,
360 &pll0_div2_clk,
361 &z2_clk,
362};
363
364
365static void div4_kick(struct clk *clk)
366{
367 if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
368 frqcr_kick_do(clk);
369 atomic_dec(&frqcr_lock);
370}
371
372static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
373
374static struct clk_div_mult_table div4_div_mult_table = {
375 .divisors = divisors,
376 .nr_divisors = ARRAY_SIZE(divisors),
377};
378
379static struct clk_div4_table div4_table = {
380 .div_mult_table = &div4_div_mult_table,
381 .kick = div4_kick,
382};
383
384enum {
385 DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
386 DIV4_ZX, DIV4_ZS, DIV4_HP,
387 DIV4_NR };
388
389static struct clk div4_clks[DIV4_NR] = {
390 [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
391 [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
392 [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
393 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
394 [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
395 [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
396 [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
397 [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
398};
399
400enum {
401 DIV6_ZB,
402 DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
403 DIV6_MMC0, DIV6_MMC1,
404 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
405 DIV6_FSIA, DIV6_FSIB,
406 DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
407 DIV6_NR };
408
409static struct clk *div6_parents[8] = {
410 [0] = &pll1_div2_clk,
411 [1] = &pll2s_clk,
412 [3] = &extal2_clk,
413 [4] = &main_div2_clk,
414 [6] = &extalr_clk,
415};
416
417static struct clk *fsia_parents[4] = {
418 [0] = &pll1_div2_clk,
419 [1] = &pll2s_clk,
420 [2] = &fsiack_clk,
421};
422
423static struct clk *fsib_parents[4] = {
424 [0] = &pll1_div2_clk,
425 [1] = &pll2s_clk,
426 [2] = &fsibck_clk,
427};
428
429static struct clk *mp_parents[4] = {
430 [0] = &pll1_div2_clk,
431 [1] = &pll2s_clk,
432 [2] = &extal2_clk,
433 [3] = &extal2_clk,
434};
435
436static struct clk *m4_parents[2] = {
437 [0] = &pll2s_clk,
438};
439
440static struct clk *hsi_parents[4] = {
441 [0] = &pll2h_clk,
442 [1] = &pll1_div2_clk,
443 [3] = &pll2s_clk,
444};
445
446
447
448
449
450
451
452
453#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
454 _num_parents, _src_shift, _src_width) \
455{ \
456 .enable_reg = (void __iomem *)_reg, \
457 .enable_bit = 0, \
458 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
459 .div_mask = SH_CLK_DIV6_MSK, \
460 .parent_table = _parents, \
461 .parent_num = _num_parents, \
462 .src_shift = _src_shift, \
463 .src_width = _src_width, \
464 .mapping = &cpg_mapping, \
465}
466
467static struct clk div6_clks[DIV6_NR] = {
468 [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
469 div6_parents, 2, 7, 1),
470 [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
471 div6_parents, 2, 6, 2),
472 [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
473 div6_parents, 2, 6, 2),
474 [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
475 div6_parents, 2, 6, 2),
476 [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
477 div6_parents, 2, 6, 2),
478 [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
479 div6_parents, 2, 6, 2),
480 [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0,
481 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
482 [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0,
483 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
484 [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0,
485 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
486 [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0,
487 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
488 [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0,
489 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
490 [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
491 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
492 [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
493 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
494 [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0,
495 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
496
497 [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0,
498 m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
499 [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0,
500 hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
501 [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
502 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
503};
504
505
506enum {
507 MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
508 MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
509 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
510 MSTP411, MSTP410, MSTP409,
511 MSTP522, MSTP515,
512 MSTP_NR
513};
514
515static struct clk mstp_clks[MSTP_NR] = {
516 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0),
517 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0),
518 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0),
519 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0),
520 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0),
521 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0),
522 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0),
523 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0),
524 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0),
525 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0),
526 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0),
527 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0),
528 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0),
529 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0),
530 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0),
531 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0),
532 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0),
533 [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0),
534 [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0),
535 [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0),
536 [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0),
537 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0),
538 [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0),
539};
540
541static struct clk_lookup lookups[] = {
542
543 CLKDEV_CON_ID("extal1", &extal1_clk),
544 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
545 CLKDEV_CON_ID("extal2", &extal2_clk),
546 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
547 CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
548 CLKDEV_CON_ID("fsiack", &fsiack_clk),
549 CLKDEV_CON_ID("fsibck", &fsibck_clk),
550
551
552 CLKDEV_CON_ID("pll1", &pll1_clk),
553 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
554 CLKDEV_CON_ID("pll2", &pll2_clk),
555 CLKDEV_CON_ID("pll2s", &pll2s_clk),
556 CLKDEV_CON_ID("pll2h", &pll2h_clk),
557
558
559 CLKDEV_DEV_ID("cpu0", &z_clk),
560
561
562 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
563 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
564 CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]),
565 CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]),
566 CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]),
567 CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]),
568 CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]),
569 CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]),
570 CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]),
571 CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]),
572 CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]),
573 CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]),
574
575
576 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
577 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
578 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
579 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
580 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
581 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
582 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
583 CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
584 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
585 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
586 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
587 CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
588 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
589 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
590 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
591 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
592 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
593 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
594 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
595 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
596 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
597 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
598 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
599 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
600 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
601 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
602 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
603 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
604 CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
605
606
607 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
608};
609
610void __init r8a73a4_clock_init(void)
611{
612 void __iomem *reg;
613 int k, ret = 0;
614 u32 ckscr;
615
616 atomic_set(&frqcr_lock, -1);
617
618 reg = ioremap_nocache(CKSCR, PAGE_SIZE);
619 BUG_ON(!reg);
620 ckscr = ioread32(reg);
621 iounmap(reg);
622
623 switch ((ckscr >> 28) & 0x3) {
624 case 0:
625 main_clk.parent = &extal1_clk;
626 break;
627 case 1:
628 main_clk.parent = &extal1_div2_clk;
629 break;
630 case 2:
631 main_clk.parent = &extal2_clk;
632 break;
633 case 3:
634 main_clk.parent = &extal2_div2_clk;
635 break;
636 }
637
638 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
639 ret = clk_register(main_clks[k]);
640
641 if (!ret)
642 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
643
644 if (!ret)
645 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
646
647 if (!ret)
648 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
649
650 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
651
652 if (!ret)
653 shmobile_clk_init();
654 else
655 panic("failed to setup r8a73a4 clocks\n");
656}
657
