1/* arch/arm/mach-s3c2410/include/mach/regs-adc.h 2 * 3 * Copyright (c) 2004 Shannon Holland <holland@loser.net> 4 * 5 * This program is free software; yosu can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * S3C2410 ADC registers 10*/ 11 12#ifndef __ASM_ARCH_REGS_ADC_H 13#define __ASM_ARCH_REGS_ADC_H "regs-adc.h" 14 15#define S3C2410_ADCREG(x) (x) 16 17#define S3C2410_ADCCON S3C2410_ADCREG(0x00) 18#define S3C2410_ADCTSC S3C2410_ADCREG(0x04) 19#define S3C2410_ADCDLY S3C2410_ADCREG(0x08) 20#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) 21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) 22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) 23#define S3C2443_ADCMUX S3C2410_ADCREG(0x18) 24#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) 25#define S5P_ADCMUX S3C2410_ADCREG(0x1C) 26#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) 27 28 29/* ADCCON Register Bits */ 30#define S3C64XX_ADCCON_RESSEL (1<<16) 31#define S3C2410_ADCCON_ECFLG (1<<15) 32#define S3C2410_ADCCON_PRSCEN (1<<14) 33#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) 34#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) 35#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) 36#define S3C2410_ADCCON_MUXMASK (0x7<<3) 37#define S3C2416_ADCCON_RESSEL (1 << 3) 38#define S3C2410_ADCCON_STDBM (1<<2) 39#define S3C2410_ADCCON_READ_START (1<<1) 40#define S3C2410_ADCCON_ENABLE_START (1<<0) 41#define S3C2410_ADCCON_STARTMASK (0x3<<0) 42 43 44/* ADCTSC Register Bits */ 45#define S3C2443_ADCTSC_UD_SEN (1 << 8) 46#define S3C2410_ADCTSC_YM_SEN (1<<7) 47#define S3C2410_ADCTSC_YP_SEN (1<<6) 48#define S3C2410_ADCTSC_XM_SEN (1<<5) 49#define S3C2410_ADCTSC_XP_SEN (1<<4) 50#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) 51#define S3C2410_ADCTSC_AUTO_PST (1<<2) 52#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) 53 54/* ADCDAT0 Bits */ 55#define S3C2410_ADCDAT0_UPDOWN (1<<15) 56#define S3C2410_ADCDAT0_AUTO_PST (1<<14) 57#define S3C2410_ADCDAT0_XY_PST (0x3<<12) 58#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) 59 60/* ADCDAT1 Bits */ 61#define S3C2410_ADCDAT1_UPDOWN (1<<15) 62#define S3C2410_ADCDAT1_AUTO_PST (1<<14) 63#define S3C2410_ADCDAT1_XY_PST (0x3<<12) 64#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) 65 66#endif /* __ASM_ARCH_REGS_ADC_H */ 67 68 69