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8#include <linux/timex.h>
9#include <linux/time.h>
10#include <linux/clocksource.h>
11#include <linux/interrupt.h>
12#include <linux/swap.h>
13#include <linux/sched.h>
14#include <linux/init.h>
15#include <linux/threads.h>
16#include <linux/cpufreq.h>
17#include <asm/types.h>
18#include <asm/signal.h>
19#include <asm/io.h>
20#include <asm/delay.h>
21#include <asm/irq.h>
22#include <asm/irq_regs.h>
23
24#include <hwregs/reg_map.h>
25#include <hwregs/reg_rdwr.h>
26#include <hwregs/timer_defs.h>
27#include <hwregs/intr_vect_defs.h>
28#ifdef CONFIG_CRIS_MACH_ARTPEC3
29#include <hwregs/clkgen_defs.h>
30#endif
31
32
33#define ETRAX_WD_KEY_MASK 0x7F
34#define ETRAX_WD_HZ 763
35
36#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
37
38
39static cycle_t read_cont_rotime(struct clocksource *cs)
40{
41 return (u32)REG_RD(timer, regi_timer0, r_time);
42}
43
44static struct clocksource cont_rotime = {
45 .name = "crisv32_rotime",
46 .rating = 300,
47 .read = read_cont_rotime,
48 .mask = CLOCKSOURCE_MASK(32),
49 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
50};
51
52static int __init etrax_init_cont_rotime(void)
53{
54 clocksource_register_khz(&cont_rotime, 100000);
55 return 0;
56}
57arch_initcall(etrax_init_cont_rotime);
58
59
60unsigned long timer_regs[NR_CPUS] =
61{
62 regi_timer0,
63#ifdef CONFIG_SMP
64 regi_timer2
65#endif
66};
67
68extern int set_rtc_mmss(unsigned long nowtime);
69
70#ifdef CONFIG_CPU_FREQ
71static int
72cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
73 void *data);
74
75static struct notifier_block cris_time_freq_notifier_block = {
76 .notifier_call = cris_time_freq_notifier,
77};
78#endif
79
80unsigned long get_ns_in_jiffie(void)
81{
82 reg_timer_r_tmr0_data data;
83 unsigned long ns;
84
85 data = REG_RD(timer, regi_timer0, r_tmr0_data);
86 ns = (TIMER0_DIV - data) * 10;
87 return ns;
88}
89
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100
101
102#define start_watchdog reset_watchdog
103
104#if defined(CONFIG_ETRAX_WATCHDOG)
105static short int watchdog_key = 42;
106#endif
107
108
109
110#define WATCHDOG_MIN_FREE_PAGES 8
111
112void reset_watchdog(void)
113{
114#if defined(CONFIG_ETRAX_WATCHDOG)
115 reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
116
117
118 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
119
120
121 watchdog_key ^= ETRAX_WD_KEY_MASK;
122 wd_ctrl.cnt = ETRAX_WD_CNT;
123 wd_ctrl.cmd = regk_timer_start;
124 wd_ctrl.key = watchdog_key;
125 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
126 }
127#endif
128}
129
130
131
132void stop_watchdog(void)
133{
134#if defined(CONFIG_ETRAX_WATCHDOG)
135 reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
136 watchdog_key ^= ETRAX_WD_KEY_MASK;
137 wd_ctrl.cnt = ETRAX_WD_CNT;
138 wd_ctrl.cmd = regk_timer_stop;
139 wd_ctrl.key = watchdog_key;
140 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
141#endif
142}
143
144extern void show_registers(struct pt_regs *regs);
145
146void handle_watchdog_bite(struct pt_regs *regs)
147{
148#if defined(CONFIG_ETRAX_WATCHDOG)
149 extern int cause_of_death;
150
151 oops_in_progress = 1;
152 printk(KERN_WARNING "Watchdog bite\n");
153
154
155 if (cause_of_death == 0xbedead) {
156#ifdef CONFIG_CRIS_MACH_ARTPEC3
157
158
159
160 reg_clkgen_rw_clk_ctrl ctrl =
161 REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
162 ctrl.pll = 0;
163 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
164#endif
165 while(1);
166 }
167
168
169 stop_watchdog();
170 printk(KERN_WARNING "Oops: bitten by watchdog\n");
171 show_registers(regs);
172 oops_in_progress = 0;
173#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
174 reset_watchdog();
175#endif
176 while(1) ;
177#endif
178}
179
180
181
182
183
184extern void cris_do_profile(struct pt_regs *regs);
185
186static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
187{
188 struct pt_regs *regs = get_irq_regs();
189 int cpu = smp_processor_id();
190 reg_timer_r_masked_intr masked_intr;
191 reg_timer_rw_ack_intr ack_intr = { 0 };
192
193
194 masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
195 if (!masked_intr.tmr0)
196 return IRQ_NONE;
197
198
199 ack_intr.tmr0 = 1;
200 REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
201
202
203 reset_watchdog();
204
205
206 update_process_times(user_mode(regs));
207
208 cris_do_profile(regs);
209
210
211 if (cpu != 0)
212 return IRQ_HANDLED;
213
214
215 xtime_update(1);
216 return IRQ_HANDLED;
217}
218
219
220static struct irqaction irq_timer = {
221 .handler = timer_interrupt,
222 .flags = IRQF_SHARED,
223 .name = "timer"
224};
225
226void __init cris_timer_init(void)
227{
228 int cpu = smp_processor_id();
229 reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
230 reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
231 reg_timer_rw_intr_mask timer_intr_mask;
232
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238
239 tmr0_ctrl.op = regk_timer_ld;
240 tmr0_ctrl.freq = regk_timer_f100;
241 REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
242 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl);
243 tmr0_ctrl.op = regk_timer_run;
244 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl);
245
246
247 timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
248 timer_intr_mask.tmr0 = 1;
249 REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
250}
251
252void __init time_init(void)
253{
254 reg_intr_vect_rw_mask intr_mask;
255
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260
261
262 loops_per_usec = 50;
263
264
265 cris_timer_init();
266
267
268 intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
269 intr_mask.timer0 = 1;
270 REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
271
272
273
274 setup_irq(TIMER0_INTR_VECT, &irq_timer);
275
276
277
278#if defined(CONFIG_ETRAX_WATCHDOG)
279 printk(KERN_INFO "Enabling watchdog...\n");
280 start_watchdog();
281
282
283
284
285
286 {
287 unsigned long flags;
288 local_save_flags(flags);
289 flags |= (1<<30);
290 local_irq_restore(flags);
291 }
292#endif
293
294#ifdef CONFIG_CPU_FREQ
295 cpufreq_register_notifier(&cris_time_freq_notifier_block,
296 CPUFREQ_TRANSITION_NOTIFIER);
297#endif
298}
299
300#ifdef CONFIG_CPU_FREQ
301static int
302cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
303 void *data)
304{
305 struct cpufreq_freqs *freqs = data;
306 if (val == CPUFREQ_POSTCHANGE) {
307 reg_timer_r_tmr0_data data;
308 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
309 do {
310 data = REG_RD(timer, timer_regs[freqs->cpu],
311 r_tmr0_data);
312 } while (data > 20);
313 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
314 }
315 return 0;
316}
317#endif
318