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11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17
18enum {
19 UNUSED = 0,
20
21
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24
25 ADC_ADI,
26
27 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
28 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
29
30 RTC, WDT,
31
32 IIC30, IIC31, IIC32,
33
34 DMAC0_DMINT0, DMAC1_DMINT1,
35 DMAC2_DMINT2, DMAC3_DMINT3,
36
37 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
38
39 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
40 DMAC7_DMINT7,
41
42 RCAN0, RCAN1,
43
44 SSI0_SSII, SSI1_SSII,
45
46 TMR0, TMR1,
47
48
49 PINT,
50};
51
52static struct intc_vect vectors[] __initdata = {
53 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
54 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
55 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
56 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
57
58 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
59 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
60 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
61 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
62
63 INTC_IRQ(ADC_ADI, 92),
64
65 INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
66 INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
67
68 INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
69 INTC_IRQ(MTU20_VEF, 114),
70
71 INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
72 INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
73
74 INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
75 INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
76
77 INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
78 INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
79
80 INTC_IRQ(MTU2_TCI3V, 136),
81
82 INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
83 INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
84
85 INTC_IRQ(MTU2_TCI4V, 144),
86
87 INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
88 INTC_IRQ(MTU25_UVW, 150),
89
90 INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
91 INTC_IRQ(RTC, 154),
92
93 INTC_IRQ(WDT, 156),
94
95 INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
96 INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
97 INTC_IRQ(IIC30, 161),
98
99 INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
100 INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
101 INTC_IRQ(IIC31, 168),
102
103 INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
104 INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
105 INTC_IRQ(IIC32, 174),
106
107 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
108 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
109
110 INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
111 INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
112 INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
113 INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
114 INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
115 INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
116 INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
117 INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
118 INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
119 INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
120 INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
121 INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
122 INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
123 INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
124 INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
125 INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
126
127 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
128 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
129 INTC_IRQ(DMAC7_DMINT7, 219),
130
131 INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
132 INTC_IRQ(RCAN0, 230),
133 INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
134
135 INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
136 INTC_IRQ(RCAN1, 236),
137 INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
138
139 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
140
141 INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
142 INTC_IRQ(TMR0, 248),
143
144 INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
145 INTC_IRQ(TMR1, 254),
146};
147
148static struct intc_group groups[] __initdata = {
149 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
150 PINT4, PINT5, PINT6, PINT7),
151};
152
153static struct intc_prio_reg prio_registers[] __initdata = {
154 { 0xfffe9418, 0, 16, 4, { IRQ0, IRQ1, IRQ2, IRQ3 } },
155 { 0xfffe941a, 0, 16, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
156 { 0xfffe9420, 0, 16, 4, { PINT, 0, ADC_ADI, 0 } },
157 { 0xfffe9800, 0, 16, 4, { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
158 { 0xfffe9802, 0, 16, 4, { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
159 { 0xfffe9804, 0, 16, 4, { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
160
161 { 0xfffe9806, 0, 16, 4, { RTC, WDT, IIC30, 0 } },
162 { 0xfffe9808, 0, 16, 4, { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
163 { 0xfffe980a, 0, 16, 4, { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
164 { 0xfffe980c, 0, 16, 4, { SCIF2, SCIF3, SCIF4, SCIF5 } },
165 { 0xfffe980e, 0, 16, 4, { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
166 { 0xfffe9810, 0, 16, 4, { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
167 { 0xfffe9812, 0, 16, 4, { 0, RCAN0, RCAN1, 0 } },
168 { 0xfffe9814, 0, 16, 4, { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
169};
170
171static struct intc_mask_reg mask_registers[] __initdata = {
172 { 0xfffe9408, 0, 16,
173 { 0, 0, 0, 0, 0, 0, 0, 0,
174 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
175};
176
177static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
178 mask_registers, prio_registers, NULL);
179
180static struct plat_sci_port scif0_platform_data = {
181 .flags = UPF_BOOT_AUTOCONF,
182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
183 .type = PORT_SCIF,
184};
185
186static struct resource scif0_resources[] = {
187 DEFINE_RES_MEM(0xfffe8000, 0x100),
188 DEFINE_RES_IRQ(180),
189};
190
191static struct platform_device scif0_device = {
192 .name = "sh-sci",
193 .id = 0,
194 .resource = scif0_resources,
195 .num_resources = ARRAY_SIZE(scif0_resources),
196 .dev = {
197 .platform_data = &scif0_platform_data,
198 },
199};
200
201static struct plat_sci_port scif1_platform_data = {
202 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
204 .type = PORT_SCIF,
205};
206
207static struct resource scif1_resources[] = {
208 DEFINE_RES_MEM(0xfffe8800, 0x100),
209 DEFINE_RES_IRQ(184),
210};
211
212static struct platform_device scif1_device = {
213 .name = "sh-sci",
214 .id = 1,
215 .resource = scif1_resources,
216 .num_resources = ARRAY_SIZE(scif1_resources),
217 .dev = {
218 .platform_data = &scif1_platform_data,
219 },
220};
221
222static struct plat_sci_port scif2_platform_data = {
223 .flags = UPF_BOOT_AUTOCONF,
224 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
225 .type = PORT_SCIF,
226};
227
228static struct resource scif2_resources[] = {
229 DEFINE_RES_MEM(0xfffe9000, 0x100),
230 DEFINE_RES_IRQ(188),
231};
232
233static struct platform_device scif2_device = {
234 .name = "sh-sci",
235 .id = 2,
236 .resource = scif2_resources,
237 .num_resources = ARRAY_SIZE(scif2_resources),
238 .dev = {
239 .platform_data = &scif2_platform_data,
240 },
241};
242
243static struct plat_sci_port scif3_platform_data = {
244 .flags = UPF_BOOT_AUTOCONF,
245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
246 .type = PORT_SCIF,
247};
248
249static struct resource scif3_resources[] = {
250 DEFINE_RES_MEM(0xfffe9800, 0x100),
251 DEFINE_RES_IRQ(192),
252};
253
254static struct platform_device scif3_device = {
255 .name = "sh-sci",
256 .id = 3,
257 .resource = scif3_resources,
258 .num_resources = ARRAY_SIZE(scif3_resources),
259 .dev = {
260 .platform_data = &scif3_platform_data,
261 },
262};
263
264static struct plat_sci_port scif4_platform_data = {
265 .flags = UPF_BOOT_AUTOCONF,
266 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
267 .type = PORT_SCIF,
268};
269
270static struct resource scif4_resources[] = {
271 DEFINE_RES_MEM(0xfffea000, 0x100),
272 DEFINE_RES_IRQ(196),
273};
274
275static struct platform_device scif4_device = {
276 .name = "sh-sci",
277 .id = 4,
278 .resource = scif4_resources,
279 .num_resources = ARRAY_SIZE(scif4_resources),
280 .dev = {
281 .platform_data = &scif4_platform_data,
282 },
283};
284
285static struct plat_sci_port scif5_platform_data = {
286 .flags = UPF_BOOT_AUTOCONF,
287 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
288 .type = PORT_SCIF,
289};
290
291static struct resource scif5_resources[] = {
292 DEFINE_RES_MEM(0xfffea800, 0x100),
293 DEFINE_RES_IRQ(200),
294};
295
296static struct platform_device scif5_device = {
297 .name = "sh-sci",
298 .id = 5,
299 .resource = scif5_resources,
300 .num_resources = ARRAY_SIZE(scif5_resources),
301 .dev = {
302 .platform_data = &scif5_platform_data,
303 },
304};
305
306static struct plat_sci_port scif6_platform_data = {
307 .flags = UPF_BOOT_AUTOCONF,
308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
309 .type = PORT_SCIF,
310};
311
312static struct resource scif6_resources[] = {
313 DEFINE_RES_MEM(0xfffeb000, 0x100),
314 DEFINE_RES_IRQ(204),
315};
316
317static struct platform_device scif6_device = {
318 .name = "sh-sci",
319 .id = 6,
320 .resource = scif6_resources,
321 .num_resources = ARRAY_SIZE(scif6_resources),
322 .dev = {
323 .platform_data = &scif6_platform_data,
324 },
325};
326
327static struct plat_sci_port scif7_platform_data = {
328 .flags = UPF_BOOT_AUTOCONF,
329 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
330 .type = PORT_SCIF,
331};
332
333static struct resource scif7_resources[] = {
334 DEFINE_RES_MEM(0xfffeb800, 0x100),
335 DEFINE_RES_IRQ(208),
336};
337
338static struct platform_device scif7_device = {
339 .name = "sh-sci",
340 .id = 7,
341 .resource = scif7_resources,
342 .num_resources = ARRAY_SIZE(scif7_resources),
343 .dev = {
344 .platform_data = &scif7_platform_data,
345 },
346};
347
348static struct resource rtc_resources[] = {
349 [0] = {
350 .start = 0xffff0800,
351 .end = 0xffff2000 + 0x58 - 1,
352 .flags = IORESOURCE_IO,
353 },
354 [1] = {
355
356 .start = 152,
357 .flags = IORESOURCE_IRQ,
358 },
359};
360
361static struct platform_device rtc_device = {
362 .name = "sh-rtc",
363 .id = -1,
364 .num_resources = ARRAY_SIZE(rtc_resources),
365 .resource = rtc_resources,
366};
367
368static struct sh_timer_config mtu2_0_platform_data = {
369 .channel_offset = -0x80,
370 .timer_bit = 0,
371 .clockevent_rating = 200,
372};
373
374static struct resource mtu2_0_resources[] = {
375 [0] = {
376 .start = 0xfffe4300,
377 .end = 0xfffe4326,
378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
381 .start = 108,
382 .flags = IORESOURCE_IRQ,
383 },
384};
385
386static struct platform_device mtu2_0_device = {
387 .name = "sh_mtu2",
388 .id = 0,
389 .dev = {
390 .platform_data = &mtu2_0_platform_data,
391 },
392 .resource = mtu2_0_resources,
393 .num_resources = ARRAY_SIZE(mtu2_0_resources),
394};
395
396static struct sh_timer_config mtu2_1_platform_data = {
397 .channel_offset = -0x100,
398 .timer_bit = 1,
399 .clockevent_rating = 200,
400};
401
402static struct resource mtu2_1_resources[] = {
403 [0] = {
404 .start = 0xfffe4380,
405 .end = 0xfffe4390,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = 116,
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device mtu2_1_device = {
415 .name = "sh_mtu2",
416 .id = 1,
417 .dev = {
418 .platform_data = &mtu2_1_platform_data,
419 },
420 .resource = mtu2_1_resources,
421 .num_resources = ARRAY_SIZE(mtu2_1_resources),
422};
423
424static struct sh_timer_config mtu2_2_platform_data = {
425 .channel_offset = 0x80,
426 .timer_bit = 2,
427 .clockevent_rating = 200,
428};
429
430static struct resource mtu2_2_resources[] = {
431 [0] = {
432 .start = 0xfffe4000,
433 .end = 0xfffe400a,
434 .flags = IORESOURCE_MEM,
435 },
436 [1] = {
437 .start = 124,
438 .flags = IORESOURCE_IRQ,
439 },
440};
441
442static struct platform_device mtu2_2_device = {
443 .name = "sh_mtu2",
444 .id = 2,
445 .dev = {
446 .platform_data = &mtu2_2_platform_data,
447 },
448 .resource = mtu2_2_resources,
449 .num_resources = ARRAY_SIZE(mtu2_2_resources),
450};
451
452static struct platform_device *sh7201_devices[] __initdata = {
453 &scif0_device,
454 &scif1_device,
455 &scif2_device,
456 &scif3_device,
457 &scif4_device,
458 &scif5_device,
459 &scif6_device,
460 &scif7_device,
461 &rtc_device,
462 &mtu2_0_device,
463 &mtu2_1_device,
464 &mtu2_2_device,
465};
466
467static int __init sh7201_devices_setup(void)
468{
469 return platform_add_devices(sh7201_devices,
470 ARRAY_SIZE(sh7201_devices));
471}
472arch_initcall(sh7201_devices_setup);
473
474void __init plat_irq_setup(void)
475{
476 register_intc_controller(&intc_desc);
477}
478
479static struct platform_device *sh7201_early_devices[] __initdata = {
480 &scif0_device,
481 &scif1_device,
482 &scif2_device,
483 &scif3_device,
484 &scif4_device,
485 &scif5_device,
486 &scif6_device,
487 &scif7_device,
488 &mtu2_0_device,
489 &mtu2_1_device,
490 &mtu2_2_device,
491};
492
493#define STBCR3 0xfffe0408
494
495void __init plat_early_device_setup(void)
496{
497
498 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
499
500 early_platform_add_devices(sh7201_early_devices,
501 ARRAY_SIZE(sh7201_early_devices));
502}
503
