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25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc))
30#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31
32#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
33
34#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
35#define _MASKED_BIT_DISABLE(a) ((a) << 16)
36
37
38
39#define HPLLCC 0xc0
40#define GC_CLOCK_CONTROL_MASK (0xf << 0)
41#define GC_CLOCK_133_200 (0 << 0)
42#define GC_CLOCK_100_200 (1 << 0)
43#define GC_CLOCK_100_133 (2 << 0)
44#define GC_CLOCK_166_250 (3 << 0)
45#define GCFGC2 0xda
46#define GCFGC 0xf0
47#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
48#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
49#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
50#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
52#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
53#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
54#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
55#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
56#define GC_DISPLAY_CLOCK_MASK (7 << 4)
57#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
58#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
59#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
60#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
61#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
62#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
63#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
64#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
65#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
66#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
67#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
68#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
69#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
70#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
71#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
72#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
73#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
74#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
75#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
76#define LBB 0xf4
77
78
79#define I965_GDRST 0xc0
80#define ILK_GDSR 0x2ca4
81#define GRDOM_FULL (0<<2)
82#define GRDOM_RENDER (1<<2)
83#define GRDOM_MEDIA (3<<2)
84#define GRDOM_MASK (3<<2)
85#define GRDOM_RESET_ENABLE (1<<0)
86
87#define GEN6_MBCUNIT_SNPCR 0x900c
88#define GEN6_MBC_SNPCR_SHIFT 21
89#define GEN6_MBC_SNPCR_MASK (3<<21)
90#define GEN6_MBC_SNPCR_MAX (0<<21)
91#define GEN6_MBC_SNPCR_MED (1<<21)
92#define GEN6_MBC_SNPCR_LOW (2<<21)
93#define GEN6_MBC_SNPCR_MIN (3<<21)
94
95#define GEN6_MBCTL 0x0907c
96#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
97#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
98#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
99#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
100#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
101
102#define GEN6_GDRST 0x941c
103#define GEN6_GRDOM_FULL (1 << 0)
104#define GEN6_GRDOM_RENDER (1 << 1)
105#define GEN6_GRDOM_MEDIA (1 << 2)
106#define GEN6_GRDOM_BLT (1 << 3)
107
108#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
109#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
110#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
111#define PP_DIR_DCLV_2G 0xffffffff
112
113#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
114#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
115
116#define GAM_ECOCHK 0x4090
117#define ECOCHK_SNB_BIT (1<<10)
118#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
119#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
120#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
121#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
122#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
123#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
124#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
125#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
126
127#define GAC_ECO_BITS 0x14090
128#define ECOBITS_SNB_BIT (1<<13)
129#define ECOBITS_PPGTT_CACHE64B (3<<8)
130#define ECOBITS_PPGTT_CACHE4B (0<<8)
131
132#define GAB_CTL 0x24000
133#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
134
135
136
137#define VGA_ST01_MDA 0x3ba
138#define VGA_ST01_CGA 0x3da
139
140#define VGA_MSR_WRITE 0x3c2
141#define VGA_MSR_READ 0x3cc
142#define VGA_MSR_MEM_EN (1<<1)
143#define VGA_MSR_CGA_MODE (1<<0)
144
145#define VGA_SR_INDEX 0x3c4
146#define SR01 1
147#define VGA_SR_DATA 0x3c5
148
149#define VGA_AR_INDEX 0x3c0
150#define VGA_AR_VID_EN (1<<5)
151#define VGA_AR_DATA_WRITE 0x3c0
152#define VGA_AR_DATA_READ 0x3c1
153
154#define VGA_GR_INDEX 0x3ce
155#define VGA_GR_DATA 0x3cf
156
157#define VGA_GR_MEM_READ_MODE_SHIFT 3
158#define VGA_GR_MEM_READ_MODE_PLANE 1
159
160#define VGA_GR_MEM_MODE_MASK 0xc
161#define VGA_GR_MEM_MODE_SHIFT 2
162#define VGA_GR_MEM_A0000_AFFFF 0
163#define VGA_GR_MEM_A0000_BFFFF 1
164#define VGA_GR_MEM_B0000_B7FFF 2
165#define VGA_GR_MEM_B0000_BFFFF 3
166
167#define VGA_DACMASK 0x3c6
168#define VGA_DACRX 0x3c7
169#define VGA_DACWX 0x3c8
170#define VGA_DACDATA 0x3c9
171
172#define VGA_CR_INDEX_MDA 0x3b4
173#define VGA_CR_DATA_MDA 0x3b5
174#define VGA_CR_INDEX_CGA 0x3d4
175#define VGA_CR_DATA_CGA 0x3d5
176
177
178
179
180#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
181
182#define MI_NOOP MI_INSTR(0, 0)
183#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
184#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
185#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
186#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
187#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
188#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
189#define MI_FLUSH MI_INSTR(0x04, 0)
190#define MI_READ_FLUSH (1 << 0)
191#define MI_EXE_FLUSH (1 << 1)
192#define MI_NO_WRITE_FLUSH (1 << 2)
193#define MI_SCENE_COUNT (1 << 3)
194#define MI_END_SCENE (1 << 4)
195#define MI_INVALIDATE_ISP (1 << 5)
196#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
197#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
198#define MI_ARB_ENABLE (1<<0)
199#define MI_ARB_DISABLE (0<<0)
200#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
201#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
202#define MI_SUSPEND_FLUSH_EN (1<<0)
203#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
204#define MI_OVERLAY_CONTINUE (0x0<<21)
205#define MI_OVERLAY_ON (0x1<<21)
206#define MI_OVERLAY_OFF (0x2<<21)
207#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
208#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
209#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
210#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
211
212#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
213#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
214#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
215#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
216#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
217#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
218#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1)
219#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
220#define MI_SEMAPHORE_UPDATE (1<<21)
221#define MI_SEMAPHORE_COMPARE (1<<20)
222#define MI_SEMAPHORE_REGISTER (1<<18)
223#define MI_SEMAPHORE_SYNC_VR (0<<16)
224#define MI_SEMAPHORE_SYNC_VER (1<<16)
225#define MI_SEMAPHORE_SYNC_BR (2<<16)
226#define MI_SEMAPHORE_SYNC_BV (0<<16)
227#define MI_SEMAPHORE_SYNC_VEV (1<<16)
228#define MI_SEMAPHORE_SYNC_RV (2<<16)
229#define MI_SEMAPHORE_SYNC_RB (0<<16)
230#define MI_SEMAPHORE_SYNC_VEB (1<<16)
231#define MI_SEMAPHORE_SYNC_VB (2<<16)
232#define MI_SEMAPHORE_SYNC_BVE (0<<16)
233#define MI_SEMAPHORE_SYNC_VVE (1<<16)
234#define MI_SEMAPHORE_SYNC_RVE (2<<16)
235#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
236#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
237#define MI_MM_SPACE_GTT (1<<8)
238#define MI_MM_SPACE_PHYSICAL (0<<8)
239#define MI_SAVE_EXT_STATE_EN (1<<3)
240#define MI_RESTORE_EXT_STATE_EN (1<<2)
241#define MI_FORCE_RESTORE (1<<1)
242#define MI_RESTORE_INHIBIT (1<<0)
243#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
244#define MI_MEM_VIRTUAL (1 << 22)
245#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
246#define MI_STORE_DWORD_INDEX_SHIFT 2
247
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249
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251
252
253#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
254#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
255#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
256#define MI_FLUSH_DW MI_INSTR(0x26, 1)
257#define MI_FLUSH_DW_STORE_INDEX (1<<21)
258#define MI_INVALIDATE_TLB (1<<18)
259#define MI_FLUSH_DW_OP_STOREDW (1<<14)
260#define MI_INVALIDATE_BSD (1<<7)
261#define MI_FLUSH_DW_USE_GTT (1<<2)
262#define MI_FLUSH_DW_USE_PPGTT (0<<2)
263#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
264#define MI_BATCH_NON_SECURE (1)
265
266#define MI_BATCH_NON_SECURE_I965 (1<<8)
267#define MI_BATCH_PPGTT_HSW (1<<8)
268#define MI_BATCH_NON_SECURE_HSW (1<<13)
269#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
270#define MI_BATCH_GTT (2<<6)
271#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
272
273
274#define MI_PREDICATE_RESULT_2 (0x2214)
275#define LOWER_SLICE_ENABLED (1<<0)
276#define LOWER_SLICE_DISABLED (0<<0)
277
278
279
280
281#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
282
283#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
284#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
285#define SC_UPDATE_SCISSOR (0x1<<1)
286#define SC_ENABLE_MASK (0x1<<0)
287#define SC_ENABLE (0x1<<0)
288#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
289#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
290#define SCI_YMIN_MASK (0xffff<<16)
291#define SCI_XMIN_MASK (0xffff<<0)
292#define SCI_YMAX_MASK (0xffff<<16)
293#define SCI_XMAX_MASK (0xffff<<0)
294#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
295#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
296#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
297#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
298#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
299#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
300#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
301#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
302#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
303#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
304#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
305#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
306#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
307#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
308#define BLT_DEPTH_8 (0<<24)
309#define BLT_DEPTH_16_565 (1<<24)
310#define BLT_DEPTH_16_1555 (2<<24)
311#define BLT_DEPTH_32 (3<<24)
312#define BLT_ROP_GXCOPY (0xcc<<16)
313#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
314#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
315#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
316#define ASYNC_FLIP (1<<22)
317#define DISPLAY_PLANE_A (0<<20)
318#define DISPLAY_PLANE_B (1<<20)
319#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
320#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24)
321#define PIPE_CONTROL_CS_STALL (1<<20)
322#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
323#define PIPE_CONTROL_QW_WRITE (1<<14)
324#define PIPE_CONTROL_DEPTH_STALL (1<<13)
325#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
326#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)
327#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11)
328#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10)
329#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
330#define PIPE_CONTROL_NOTIFY (1<<8)
331#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
332#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
333#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
334#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
335#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
336#define PIPE_CONTROL_GLOBAL_GTT (1<<2)
337
338
339
340
341
342#define DEBUG_RESET_I830 0x6070
343#define DEBUG_RESET_FULL (1<<7)
344#define DEBUG_RESET_RENDER (1<<8)
345#define DEBUG_RESET_DISPLAY (1<<9)
346
347
348
349
350#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
351#define IOSF_DEVFN_SHIFT 24
352#define IOSF_OPCODE_SHIFT 16
353#define IOSF_PORT_SHIFT 8
354#define IOSF_BYTE_ENABLES_SHIFT 4
355#define IOSF_BAR_SHIFT 1
356#define IOSF_SB_BUSY (1<<0)
357#define IOSF_PORT_BUNIT 0x3
358#define IOSF_PORT_PUNIT 0x4
359#define IOSF_PORT_NC 0x11
360#define IOSF_PORT_DPIO 0x12
361#define IOSF_PORT_GPIO_NC 0x13
362#define IOSF_PORT_CCK 0x14
363#define IOSF_PORT_CCU 0xA9
364#define IOSF_PORT_GPS_CORE 0x48
365#define IOSF_PORT_FLISDSI 0x1B
366#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
367#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
368
369
370#define BUNIT_REG_BISOC 0x11
371
372#define PUNIT_OPCODE_REG_READ 6
373#define PUNIT_OPCODE_REG_WRITE 7
374
375#define PUNIT_REG_DSPFREQ 0x36
376#define DSPFREQSTAT_SHIFT 30
377#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
378#define DSPFREQGUAR_SHIFT 14
379#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
380#define PUNIT_REG_PWRGT_CTRL 0x60
381#define PUNIT_REG_PWRGT_STATUS 0x61
382#define PUNIT_CLK_GATE 1
383#define PUNIT_PWR_RESET 2
384#define PUNIT_PWR_GATE 3
385#define RENDER_PWRGT (PUNIT_PWR_GATE << 0)
386#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2)
387#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6)
388
389#define PUNIT_REG_GPU_LFM 0xd3
390#define PUNIT_REG_GPU_FREQ_REQ 0xd4
391#define PUNIT_REG_GPU_FREQ_STS 0xd8
392#define GENFREQSTATUS (1<<0)
393#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
394
395#define PUNIT_FUSE_BUS2 0xf6
396#define PUNIT_FUSE_BUS1 0xf5
397
398#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
399#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
400#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
401#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
402#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
403#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
404#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
405#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
406#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
407#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
408
409
410#define CCK_FUSE_REG 0x8
411#define CCK_FUSE_HPLL_FREQ_MASK 0x3
412#define CCK_REG_DSI_PLL_FUSE 0x44
413#define CCK_REG_DSI_PLL_CONTROL 0x48
414#define DSI_PLL_VCO_EN (1 << 31)
415#define DSI_PLL_LDO_GATE (1 << 30)
416#define DSI_PLL_P1_POST_DIV_SHIFT 17
417#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
418#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
419#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
420#define DSI_PLL_MUX_MASK (3 << 9)
421#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
422#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
423#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
424#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
425#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
426#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
427#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
428#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
429#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
430#define DSI_PLL_LOCK (1 << 0)
431#define CCK_REG_DSI_PLL_DIVIDER 0x4c
432#define DSI_PLL_LFSR (1 << 31)
433#define DSI_PLL_FRACTION_EN (1 << 30)
434#define DSI_PLL_FRAC_COUNTER_SHIFT 27
435#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
436#define DSI_PLL_USYNC_CNT_SHIFT 18
437#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
438#define DSI_PLL_N1_DIV_SHIFT 16
439#define DSI_PLL_N1_DIV_MASK (3 << 16)
440#define DSI_PLL_M1_DIV_SHIFT 0
441#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
442#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
443
444
445
446
447
448
449
450
451#define DPIO_DEVFN 0
452#define DPIO_OPCODE_REG_WRITE 1
453#define DPIO_OPCODE_REG_READ 0
454
455#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
456#define DPIO_MODSEL1 (1<<3)
457#define DPIO_MODSEL0 (1<<2)
458#define DPIO_SFR_BYPASS (1<<1)
459#define DPIO_CMNRST (1<<0)
460
461#define DPIO_PHY(pipe) ((pipe) >> 1)
462#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
463
464
465
466
467#define _VLV_PLL_DW3_CH0 0x800c
468#define DPIO_POST_DIV_SHIFT (28)
469#define DPIO_POST_DIV_DAC 0
470#define DPIO_POST_DIV_HDMIDP 1
471#define DPIO_POST_DIV_LVDS1 2
472#define DPIO_POST_DIV_LVDS2 3
473#define DPIO_K_SHIFT (24)
474#define DPIO_P1_SHIFT (21)
475#define DPIO_P2_SHIFT (16)
476#define DPIO_N_SHIFT (12)
477#define DPIO_ENABLE_CALIBRATION (1<<11)
478#define DPIO_M1DIV_SHIFT (8)
479#define DPIO_M2DIV_MASK 0xff
480#define _VLV_PLL_DW3_CH1 0x802c
481#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
482
483#define _VLV_PLL_DW5_CH0 0x8014
484#define DPIO_REFSEL_OVERRIDE 27
485#define DPIO_PLL_MODESEL_SHIFT 24
486#define DPIO_BIAS_CURRENT_CTL_SHIFT 21
487#define DPIO_PLL_REFCLK_SEL_SHIFT 16
488#define DPIO_PLL_REFCLK_SEL_MASK 3
489#define DPIO_DRIVER_CTL_SHIFT 12
490#define DPIO_CLK_BIAS_CTL_SHIFT 8
491#define _VLV_PLL_DW5_CH1 0x8034
492#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
493
494#define _VLV_PLL_DW7_CH0 0x801c
495#define _VLV_PLL_DW7_CH1 0x803c
496#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
497
498#define _VLV_PLL_DW8_CH0 0x8040
499#define _VLV_PLL_DW8_CH1 0x8060
500#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
501
502#define VLV_PLL_DW9_BCAST 0xc044
503#define _VLV_PLL_DW9_CH0 0x8044
504#define _VLV_PLL_DW9_CH1 0x8064
505#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
506
507#define _VLV_PLL_DW10_CH0 0x8048
508#define _VLV_PLL_DW10_CH1 0x8068
509#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
510
511#define _VLV_PLL_DW11_CH0 0x804c
512#define _VLV_PLL_DW11_CH1 0x806c
513#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
514
515
516#define VLV_REF_DW13 0x80ac
517
518#define VLV_CMN_DW0 0x8100
519
520
521
522
523
524#define _VLV_PCS_DW0_CH0 0x8200
525#define _VLV_PCS_DW0_CH1 0x8400
526#define DPIO_PCS_TX_LANE2_RESET (1<<16)
527#define DPIO_PCS_TX_LANE1_RESET (1<<7)
528#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
529
530#define _VLV_PCS_DW1_CH0 0x8204
531#define _VLV_PCS_DW1_CH1 0x8404
532#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
533#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
534#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
535#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
536#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
537
538#define _VLV_PCS_DW8_CH0 0x8220
539#define _VLV_PCS_DW8_CH1 0x8420
540#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
541
542#define _VLV_PCS01_DW8_CH0 0x0220
543#define _VLV_PCS23_DW8_CH0 0x0420
544#define _VLV_PCS01_DW8_CH1 0x2620
545#define _VLV_PCS23_DW8_CH1 0x2820
546#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
547#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
548
549#define _VLV_PCS_DW9_CH0 0x8224
550#define _VLV_PCS_DW9_CH1 0x8424
551#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
552
553#define _VLV_PCS_DW11_CH0 0x822c
554#define _VLV_PCS_DW11_CH1 0x842c
555#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
556
557#define _VLV_PCS_DW12_CH0 0x8230
558#define _VLV_PCS_DW12_CH1 0x8430
559#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
560
561#define _VLV_PCS_DW14_CH0 0x8238
562#define _VLV_PCS_DW14_CH1 0x8438
563#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
564
565#define _VLV_PCS_DW23_CH0 0x825c
566#define _VLV_PCS_DW23_CH1 0x845c
567#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
568
569#define _VLV_TX_DW2_CH0 0x8288
570#define _VLV_TX_DW2_CH1 0x8488
571#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
572
573#define _VLV_TX_DW3_CH0 0x828c
574#define _VLV_TX_DW3_CH1 0x848c
575#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
576
577#define _VLV_TX_DW4_CH0 0x8290
578#define _VLV_TX_DW4_CH1 0x8490
579#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
580
581#define _VLV_TX3_DW4_CH0 0x690
582#define _VLV_TX3_DW4_CH1 0x2a90
583#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
584
585#define _VLV_TX_DW5_CH0 0x8294
586#define _VLV_TX_DW5_CH1 0x8494
587#define DPIO_TX_OCALINIT_EN (1<<31)
588#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
589
590#define _VLV_TX_DW11_CH0 0x82ac
591#define _VLV_TX_DW11_CH1 0x84ac
592#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
593
594#define _VLV_TX_DW14_CH0 0x82b8
595#define _VLV_TX_DW14_CH1 0x84b8
596#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
597
598
599
600
601#define FENCE_REG_830_0 0x2000
602#define FENCE_REG_945_8 0x3000
603#define I830_FENCE_START_MASK 0x07f80000
604#define I830_FENCE_TILING_Y_SHIFT 12
605#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
606#define I830_FENCE_PITCH_SHIFT 4
607#define I830_FENCE_REG_VALID (1<<0)
608#define I915_FENCE_MAX_PITCH_VAL 4
609#define I830_FENCE_MAX_PITCH_VAL 6
610#define I830_FENCE_MAX_SIZE_VAL (1<<8)
611
612#define I915_FENCE_START_MASK 0x0ff00000
613#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
614
615#define FENCE_REG_965_0 0x03000
616#define I965_FENCE_PITCH_SHIFT 2
617#define I965_FENCE_TILING_Y_SHIFT 1
618#define I965_FENCE_REG_VALID (1<<0)
619#define I965_FENCE_MAX_PITCH_VAL 0x0400
620
621#define FENCE_REG_SANDYBRIDGE_0 0x100000
622#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
623#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
624
625
626#define TILECTL 0x101000
627#define TILECTL_SWZCTL (1 << 0)
628#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
629#define TILECTL_BACKSNOOP_DIS (1 << 3)
630
631
632
633
634#define PGTBL_ER 0x02024
635#define RENDER_RING_BASE 0x02000
636#define BSD_RING_BASE 0x04000
637#define GEN6_BSD_RING_BASE 0x12000
638#define VEBOX_RING_BASE 0x1a000
639#define BLT_RING_BASE 0x22000
640#define RING_TAIL(base) ((base)+0x30)
641#define RING_HEAD(base) ((base)+0x34)
642#define RING_START(base) ((base)+0x38)
643#define RING_CTL(base) ((base)+0x3c)
644#define RING_SYNC_0(base) ((base)+0x40)
645#define RING_SYNC_1(base) ((base)+0x44)
646#define RING_SYNC_2(base) ((base)+0x48)
647#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
648#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
649#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
650#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
651#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
652#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
653#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
654#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
655#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
656#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
657#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
658#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
659#define GEN6_NOSYNC 0
660#define RING_MAX_IDLE(base) ((base)+0x54)
661#define RING_HWS_PGA(base) ((base)+0x80)
662#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
663#define ARB_MODE 0x04030
664#define ARB_MODE_SWIZZLE_SNB (1<<4)
665#define ARB_MODE_SWIZZLE_IVB (1<<5)
666#define GAMTARBMODE 0x04a08
667#define ARB_MODE_BWGTLB_DISABLE (1<<9)
668#define ARB_MODE_SWIZZLE_BDW (1<<1)
669#define RENDER_HWS_PGA_GEN7 (0x04080)
670#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
671#define RING_FAULT_GTTSEL_MASK (1<<11)
672#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
673#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
674#define RING_FAULT_VALID (1<<0)
675#define DONE_REG 0x40b0
676#define GEN8_PRIVATE_PAT 0x40e0
677#define BSD_HWS_PGA_GEN7 (0x04180)
678#define BLT_HWS_PGA_GEN7 (0x04280)
679#define VEBOX_HWS_PGA_GEN7 (0x04380)
680#define RING_ACTHD(base) ((base)+0x74)
681#define RING_NOPID(base) ((base)+0x94)
682#define RING_IMR(base) ((base)+0xa8)
683#define RING_TIMESTAMP(base) ((base)+0x358)
684#define TAIL_ADDR 0x001FFFF8
685#define HEAD_WRAP_COUNT 0xFFE00000
686#define HEAD_WRAP_ONE 0x00200000
687#define HEAD_ADDR 0x001FFFFC
688#define RING_NR_PAGES 0x001FF000
689#define RING_REPORT_MASK 0x00000006
690#define RING_REPORT_64K 0x00000002
691#define RING_REPORT_128K 0x00000004
692#define RING_NO_REPORT 0x00000000
693#define RING_VALID_MASK 0x00000001
694#define RING_VALID 0x00000001
695#define RING_INVALID 0x00000000
696#define RING_WAIT_I8XX (1<<0)
697#define RING_WAIT (1<<11)
698#define RING_WAIT_SEMAPHORE (1<<10)
699#if 0
700#define PRB0_TAIL 0x02030
701#define PRB0_HEAD 0x02034
702#define PRB0_START 0x02038
703#define PRB0_CTL 0x0203c
704#define PRB1_TAIL 0x02040
705#define PRB1_HEAD 0x02044
706#define PRB1_START 0x02048
707#define PRB1_CTL 0x0204c
708#endif
709#define IPEIR_I965 0x02064
710#define IPEHR_I965 0x02068
711#define INSTDONE_I965 0x0206c
712#define GEN7_INSTDONE_1 0x0206c
713#define GEN7_SC_INSTDONE 0x07100
714#define GEN7_SAMPLER_INSTDONE 0x0e160
715#define GEN7_ROW_INSTDONE 0x0e164
716#define I915_NUM_INSTDONE_REG 4
717#define RING_IPEIR(base) ((base)+0x64)
718#define RING_IPEHR(base) ((base)+0x68)
719#define RING_INSTDONE(base) ((base)+0x6c)
720#define RING_INSTPS(base) ((base)+0x70)
721#define RING_DMA_FADD(base) ((base)+0x78)
722#define RING_INSTPM(base) ((base)+0xc0)
723#define INSTPS 0x02070
724#define INSTDONE1 0x0207c
725#define ACTHD_I965 0x02074
726#define HWS_PGA 0x02080
727#define HWS_ADDRESS_MASK 0xfffff000
728#define HWS_START_ADDRESS_SHIFT 4
729#define PWRCTXA 0x2088
730#define PWRCTX_EN (1<<0)
731#define IPEIR 0x02088
732#define IPEHR 0x0208c
733#define INSTDONE 0x02090
734#define NOPID 0x02094
735#define HWSTAM 0x02098
736#define DMA_FADD_I8XX 0x020d0
737#define RING_BBSTATE(base) ((base)+0x110)
738#define RING_BBADDR(base) ((base)+0x140)
739#define RING_BBADDR_UDW(base) ((base)+0x168)
740
741#define ERROR_GEN6 0x040a0
742#define GEN7_ERR_INT 0x44040
743#define ERR_INT_POISON (1<<31)
744#define ERR_INT_MMIO_UNCLAIMED (1<<13)
745#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
746#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
747#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
748#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
749#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
750#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
751#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
752#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
753
754#define FPGA_DBG 0x42300
755#define FPGA_DBG_RM_NOCLAIM (1<<31)
756
757#define DERRMR 0x44050
758
759#define DERRMR_PIPEA_SCANLINE (1<<0)
760#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
761#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
762#define DERRMR_PIPEA_VBLANK (1<<3)
763#define DERRMR_PIPEA_HBLANK (1<<5)
764#define DERRMR_PIPEB_SCANLINE (1<<8)
765#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
766#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
767#define DERRMR_PIPEB_VBLANK (1<<11)
768#define DERRMR_PIPEB_HBLANK (1<<13)
769
770#define DERRMR_PIPEC_SCANLINE (1<<14)
771#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
772#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
773#define DERRMR_PIPEC_VBLANK (1<<21)
774#define DERRMR_PIPEC_HBLANK (1<<22)
775
776
777
778
779
780
781#define _3D_CHICKEN 0x02084
782#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
783#define _3D_CHICKEN2 0x0208c
784
785
786
787
788# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
789#define _3D_CHICKEN3 0x02090
790#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
791#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
792#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1)
793
794#define MI_MODE 0x0209c
795# define VS_TIMER_DISPATCH (1 << 6)
796# define MI_FLUSH_ENABLE (1 << 12)
797# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
798
799#define GEN6_GT_MODE 0x20d0
800#define GEN6_GT_MODE_HI (1 << 9)
801#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
802
803#define GFX_MODE 0x02520
804#define GFX_MODE_GEN7 0x0229c
805#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
806#define GFX_RUN_LIST_ENABLE (1<<15)
807#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
808#define GFX_SURFACE_FAULT_ENABLE (1<<12)
809#define GFX_REPLAY_MODE (1<<11)
810#define GFX_PSMI_GRANULARITY (1<<10)
811#define GFX_PPGTT_ENABLE (1<<9)
812
813#define VLV_DISPLAY_BASE 0x180000
814
815#define SCPD0 0x0209c
816#define IER 0x020a0
817#define IIR 0x020a4
818#define IMR 0x020a8
819#define ISR 0x020ac
820#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
821#define GCFG_DIS (1<<8)
822#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
823#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
824#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
825#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
826#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
827#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
828#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane)))
829#define EIR 0x020b0
830#define EMR 0x020b4
831#define ESR 0x020b8
832#define GM45_ERROR_PAGE_TABLE (1<<5)
833#define GM45_ERROR_MEM_PRIV (1<<4)
834#define I915_ERROR_PAGE_TABLE (1<<4)
835#define GM45_ERROR_CP_PRIV (1<<3)
836#define I915_ERROR_MEMORY_REFRESH (1<<1)
837#define I915_ERROR_INSTRUCTION (1<<0)
838#define INSTPM 0x020c0
839#define INSTPM_SELF_EN (1<<12)
840#define INSTPM_AGPBUSY_DIS (1<<11)
841
842
843#define INSTPM_FORCE_ORDERING (1<<7)
844#define INSTPM_TLB_INVALIDATE (1<<9)
845#define INSTPM_SYNC_FLUSH (1<<5)
846#define ACTHD 0x020c8
847#define FW_BLC 0x020d8
848#define FW_BLC2 0x020dc
849#define FW_BLC_SELF 0x020e0
850#define FW_BLC_SELF_EN_MASK (1<<31)
851#define FW_BLC_SELF_FIFO_MASK (1<<16)
852#define FW_BLC_SELF_EN (1<<15)
853#define MM_BURST_LENGTH 0x00700000
854#define MM_FIFO_WATERMARK 0x0001F000
855#define LM_BURST_LENGTH 0x00000700
856#define LM_FIFO_WATERMARK 0x0000001F
857#define MI_ARB_STATE 0x020e4
858
859
860
861
862#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
863
864
865
866
867
868#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
869
870
871
872
873#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
874#define MI_ARB_BLOCK_GRANT_8 (0 << 12)
875#define MI_ARB_BLOCK_GRANT_4 (1 << 12)
876#define MI_ARB_BLOCK_GRANT_2 (2 << 12)
877#define MI_ARB_BLOCK_GRANT_0 (3 << 12)
878
879
880
881
882
883#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
884
885
886
887
888#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
889
890
891
892#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
893
894
895
896
897#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
898
899
900#define MI_ARB_TIME_SLICE_MASK (7 << 5)
901#define MI_ARB_TIME_SLICE_1 (0 << 5)
902#define MI_ARB_TIME_SLICE_2 (1 << 5)
903#define MI_ARB_TIME_SLICE_4 (2 << 5)
904#define MI_ARB_TIME_SLICE_6 (3 << 5)
905#define MI_ARB_TIME_SLICE_8 (4 << 5)
906#define MI_ARB_TIME_SLICE_10 (5 << 5)
907#define MI_ARB_TIME_SLICE_14 (6 << 5)
908#define MI_ARB_TIME_SLICE_16 (7 << 5)
909
910
911#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4)
912#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
913
914
915#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
916
917
918#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0)
919#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0)
920
921#define CACHE_MODE_0 0x02120
922#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
923#define CM0_IZ_OPT_DISABLE (1<<6)
924#define CM0_ZR_OPT_DISABLE (1<<5)
925#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
926#define CM0_DEPTH_EVICT_DISABLE (1<<4)
927#define CM0_COLOR_EVICT_DISABLE (1<<3)
928#define CM0_DEPTH_WRITE_DISABLE (1<<1)
929#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
930#define GFX_FLSH_CNTL 0x02170
931#define GFX_FLSH_CNTL_GEN6 0x101008
932#define GFX_FLSH_CNTL_EN (1<<0)
933#define ECOSKPD 0x021d0
934#define ECO_GATING_CX_ONLY (1<<3)
935#define ECO_FLIP_DONE (1<<0)
936
937#define CACHE_MODE_1 0x7004
938#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
939
940#define GEN6_BLITTER_ECOSKPD 0x221d0
941#define GEN6_BLITTER_LOCK_SHIFT 16
942#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
943
944#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
945#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
946#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
947#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
948#define GEN6_BSD_GO_INDICATOR (1 << 4)
949
950
951
952
953
954
955
956
957
958
959
960
961#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
962#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
963#define GT_BLT_USER_INTERRUPT (1 << 22)
964#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
965#define GT_BSD_USER_INTERRUPT (1 << 12)
966#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11)
967#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5)
968#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
969#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
970#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
971#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
972#define GT_RENDER_USER_INTERRUPT (1 << 0)
973
974#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12)
975#define PM_VEBOX_USER_INTERRUPT (1 << 10)
976
977#define GT_PARITY_ERROR(dev) \
978 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
979 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
980
981
982#define ILK_BSD_USER_INTERRUPT (1<<5)
983#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
984#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
985#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
986#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
987#define I915_HWB_OOM_INTERRUPT (1<<13)
988#define I915_SYNC_STATUS_INTERRUPT (1<<12)
989#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
990#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
991#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
992#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
993#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
994#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
995#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
996#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
997#define I915_DEBUG_INTERRUPT (1<<2)
998#define I915_USER_INTERRUPT (1<<1)
999#define I915_ASLE_INTERRUPT (1<<0)
1000#define I915_BSD_USER_INTERRUPT (1 << 25)
1001
1002#define GEN6_BSD_RNCID 0x12198
1003
1004#define GEN7_FF_THREAD_MODE 0x20a0
1005#define GEN7_FF_SCHED_MASK 0x0077070
1006#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1007#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1008#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1009#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1010#define GEN7_FF_TS_SCHED_HW (0x0<<16)
1011#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1012#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1013#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1014#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12)
1015#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1016#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1017#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1018#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4)
1019#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1020
1021
1022
1023
1024
1025#define FBC_CFB_BASE 0x03200
1026#define FBC_LL_BASE 0x03204
1027#define FBC_CONTROL 0x03208
1028#define FBC_CTL_EN (1<<31)
1029#define FBC_CTL_PERIODIC (1<<30)
1030#define FBC_CTL_INTERVAL_SHIFT (16)
1031#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1032#define FBC_CTL_C3_IDLE (1<<13)
1033#define FBC_CTL_STRIDE_SHIFT (5)
1034#define FBC_CTL_FENCENO_SHIFT (0)
1035#define FBC_COMMAND 0x0320c
1036#define FBC_CMD_COMPRESS (1<<0)
1037#define FBC_STATUS 0x03210
1038#define FBC_STAT_COMPRESSING (1<<31)
1039#define FBC_STAT_COMPRESSED (1<<30)
1040#define FBC_STAT_MODIFIED (1<<29)
1041#define FBC_STAT_CURRENT_LINE_SHIFT (0)
1042#define FBC_CONTROL2 0x03214
1043#define FBC_CTL_FENCE_DBL (0<<4)
1044#define FBC_CTL_IDLE_IMM (0<<2)
1045#define FBC_CTL_IDLE_FULL (1<<2)
1046#define FBC_CTL_IDLE_LINE (2<<2)
1047#define FBC_CTL_IDLE_DEBUG (3<<2)
1048#define FBC_CTL_CPU_FENCE (1<<1)
1049#define FBC_CTL_PLANEA (0<<0)
1050#define FBC_CTL_PLANEB (1<<0)
1051#define FBC_FENCE_OFF 0x0321b
1052#define FBC_TAG 0x03300
1053
1054#define FBC_LL_SIZE (1536)
1055
1056
1057#define DPFC_CB_BASE 0x3200
1058#define DPFC_CONTROL 0x3208
1059#define DPFC_CTL_EN (1<<31)
1060#define DPFC_CTL_PLANEA (0<<30)
1061#define DPFC_CTL_PLANEB (1<<30)
1062#define IVB_DPFC_CTL_PLANE_SHIFT (29)
1063#define DPFC_CTL_FENCE_EN (1<<29)
1064#define IVB_DPFC_CTL_FENCE_EN (1<<28)
1065#define DPFC_CTL_PERSISTENT_MODE (1<<25)
1066#define DPFC_SR_EN (1<<10)
1067#define DPFC_CTL_LIMIT_1X (0<<6)
1068#define DPFC_CTL_LIMIT_2X (1<<6)
1069#define DPFC_CTL_LIMIT_4X (2<<6)
1070#define DPFC_RECOMP_CTL 0x320c
1071#define DPFC_RECOMP_STALL_EN (1<<27)
1072#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1073#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1074#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1075#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1076#define DPFC_STATUS 0x3210
1077#define DPFC_INVAL_SEG_SHIFT (16)
1078#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1079#define DPFC_COMP_SEG_SHIFT (0)
1080#define DPFC_COMP_SEG_MASK (0x000003ff)
1081#define DPFC_STATUS2 0x3214
1082#define DPFC_FENCE_YOFF 0x3218
1083#define DPFC_CHICKEN 0x3224
1084#define DPFC_HT_MODIFY (1<<31)
1085
1086
1087#define ILK_DPFC_CB_BASE 0x43200
1088#define ILK_DPFC_CONTROL 0x43208
1089
1090#define DPFC_RESERVED (0x1FFFFF00)
1091#define ILK_DPFC_RECOMP_CTL 0x4320c
1092#define ILK_DPFC_STATUS 0x43210
1093#define ILK_DPFC_FENCE_YOFF 0x43218
1094#define ILK_DPFC_CHICKEN 0x43224
1095#define ILK_FBC_RT_BASE 0x2128
1096#define ILK_FBC_RT_VALID (1<<0)
1097#define SNB_FBC_FRONT_BUFFER (1<<1)
1098
1099#define ILK_DISPLAY_CHICKEN1 0x42000
1100#define ILK_FBCQ_DIS (1<<22)
1101#define ILK_PABSTRETCH_DIS (1<<21)
1102
1103
1104
1105
1106
1107
1108
1109#define SNB_DPFC_CTL_SA 0x100100
1110#define SNB_CPU_FENCE_ENABLE (1<<29)
1111#define DPFC_CPU_FENCE_OFFSET 0x100104
1112
1113
1114#define IVB_FBC_RT_BASE 0x7020
1115
1116#define IPS_CTL 0x43408
1117#define IPS_ENABLE (1 << 31)
1118
1119#define MSG_FBC_REND_STATE 0x50380
1120#define FBC_REND_NUKE (1<<2)
1121#define FBC_REND_CACHE_CLEAN (1<<1)
1122
1123#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
1124#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
1125#define HSW_BYPASS_FBC_QUEUE (1<<22)
1126#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
1127 _HSW_PIPE_SLICE_CHICKEN_1_A, + \
1128 _HSW_PIPE_SLICE_CHICKEN_1_B)
1129
1130
1131
1132
1133#define GPIOA 0x5010
1134#define GPIOB 0x5014
1135#define GPIOC 0x5018
1136#define GPIOD 0x501c
1137#define GPIOE 0x5020
1138#define GPIOF 0x5024
1139#define GPIOG 0x5028
1140#define GPIOH 0x502c
1141# define GPIO_CLOCK_DIR_MASK (1 << 0)
1142# define GPIO_CLOCK_DIR_IN (0 << 1)
1143# define GPIO_CLOCK_DIR_OUT (1 << 1)
1144# define GPIO_CLOCK_VAL_MASK (1 << 2)
1145# define GPIO_CLOCK_VAL_OUT (1 << 3)
1146# define GPIO_CLOCK_VAL_IN (1 << 4)
1147# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1148# define GPIO_DATA_DIR_MASK (1 << 8)
1149# define GPIO_DATA_DIR_IN (0 << 9)
1150# define GPIO_DATA_DIR_OUT (1 << 9)
1151# define GPIO_DATA_VAL_MASK (1 << 10)
1152# define GPIO_DATA_VAL_OUT (1 << 11)
1153# define GPIO_DATA_VAL_IN (1 << 12)
1154# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1155
1156#define GMBUS0 0x5100
1157#define GMBUS_RATE_100KHZ (0<<8)
1158#define GMBUS_RATE_50KHZ (1<<8)
1159#define GMBUS_RATE_400KHZ (2<<8)
1160#define GMBUS_RATE_1MHZ (3<<8)
1161#define GMBUS_HOLD_EXT (1<<7)
1162#define GMBUS_PORT_DISABLED 0
1163#define GMBUS_PORT_SSC 1
1164#define GMBUS_PORT_VGADDC 2
1165#define GMBUS_PORT_PANEL 3
1166#define GMBUS_PORT_DPC 4
1167#define GMBUS_PORT_DPB 5
1168#define GMBUS_PORT_DPD 6
1169#define GMBUS_PORT_RESERVED 7
1170#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1171#define GMBUS1 0x5104
1172#define GMBUS_SW_CLR_INT (1<<31)
1173#define GMBUS_SW_RDY (1<<30)
1174#define GMBUS_ENT (1<<29)
1175#define GMBUS_CYCLE_NONE (0<<25)
1176#define GMBUS_CYCLE_WAIT (1<<25)
1177#define GMBUS_CYCLE_INDEX (2<<25)
1178#define GMBUS_CYCLE_STOP (4<<25)
1179#define GMBUS_BYTE_COUNT_SHIFT 16
1180#define GMBUS_SLAVE_INDEX_SHIFT 8
1181#define GMBUS_SLAVE_ADDR_SHIFT 1
1182#define GMBUS_SLAVE_READ (1<<0)
1183#define GMBUS_SLAVE_WRITE (0<<0)
1184#define GMBUS2 0x5108
1185#define GMBUS_INUSE (1<<15)
1186#define GMBUS_HW_WAIT_PHASE (1<<14)
1187#define GMBUS_STALL_TIMEOUT (1<<13)
1188#define GMBUS_INT (1<<12)
1189#define GMBUS_HW_RDY (1<<11)
1190#define GMBUS_SATOER (1<<10)
1191#define GMBUS_ACTIVE (1<<9)
1192#define GMBUS3 0x510c
1193#define GMBUS4 0x5110
1194#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1195#define GMBUS_NAK_EN (1<<3)
1196#define GMBUS_IDLE_EN (1<<2)
1197#define GMBUS_HW_WAIT_EN (1<<1)
1198#define GMBUS_HW_RDY_EN (1<<0)
1199#define GMBUS5 0x5120
1200#define GMBUS_2BYTE_INDEX_EN (1<<31)
1201
1202
1203
1204
1205
1206#define VGA0 0x6000
1207#define VGA1 0x6004
1208#define VGA_PD 0x6010
1209#define VGA0_PD_P2_DIV_4 (1 << 7)
1210#define VGA0_PD_P1_DIV_2 (1 << 5)
1211#define VGA0_PD_P1_SHIFT 0
1212#define VGA0_PD_P1_MASK (0x1f << 0)
1213#define VGA1_PD_P2_DIV_4 (1 << 15)
1214#define VGA1_PD_P1_DIV_2 (1 << 13)
1215#define VGA1_PD_P1_SHIFT 8
1216#define VGA1_PD_P1_MASK (0x1f << 8)
1217#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
1218#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
1219#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
1220#define DPLL_VCO_ENABLE (1 << 31)
1221#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1222#define DPLL_DVO_2X_MODE (1 << 30)
1223#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1224#define DPLL_SYNCLOCK_ENABLE (1 << 29)
1225#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
1226#define DPLL_VGA_MODE_DIS (1 << 28)
1227#define DPLLB_MODE_DAC_SERIAL (1 << 26)
1228#define DPLLB_MODE_LVDS (2 << 26)
1229#define DPLL_MODE_MASK (3 << 26)
1230#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24)
1231#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24)
1232#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24)
1233#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24)
1234#define DPLL_P2_CLOCK_DIV_MASK 0x03000000
1235#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000
1236#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000
1237#define DPLL_LOCK_VLV (1<<15)
1238#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
1239#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
1240#define DPLL_PORTC_READY_MASK (0xf << 4)
1241#define DPLL_PORTB_READY_MASK (0xf)
1242
1243#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1244
1245
1246
1247
1248#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1249#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1250#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1251
1252#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1253#define PLL_P1_DIVIDE_BY_TWO (1 << 21)
1254#define PLL_REF_INPUT_DREFCLK (0 << 13)
1255#define PLL_REF_INPUT_TVCLKINA (1 << 13)
1256#define PLL_REF_INPUT_TVCLKINBC (2 << 13)
1257#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1258#define PLL_REF_INPUT_MASK (3 << 13)
1259#define PLL_LOAD_PULSE_PHASE_SHIFT 9
1260
1261# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1262# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1263# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1264# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1265# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1266
1267
1268
1269
1270
1271
1272
1273#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1274#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1275
1276
1277
1278#define SDVO_MULTIPLIER_MASK 0x000000ff
1279#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1280#define SDVO_MULTIPLIER_SHIFT_VGA 0
1281#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c)
1282
1283
1284
1285
1286
1287#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1288#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1289
1290#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1291#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1310#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1311
1312
1313
1314
1315
1316#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1317#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1318#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020)
1319#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1320
1321#define _FPA0 0x06040
1322#define _FPA1 0x06044
1323#define _FPB0 0x06048
1324#define _FPB1 0x0604c
1325#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1326#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1327#define FP_N_DIV_MASK 0x003f0000
1328#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1329#define FP_N_DIV_SHIFT 16
1330#define FP_M1_DIV_MASK 0x00003f00
1331#define FP_M1_DIV_SHIFT 8
1332#define FP_M2_DIV_MASK 0x0000003f
1333#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1334#define FP_M2_DIV_SHIFT 0
1335#define DPLL_TEST 0x606c
1336#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1337#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1338#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1339#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1340#define DPLLB_TEST_N_BYPASS (1 << 19)
1341#define DPLLB_TEST_M_BYPASS (1 << 18)
1342#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1343#define DPLLA_TEST_N_BYPASS (1 << 3)
1344#define DPLLA_TEST_M_BYPASS (1 << 2)
1345#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1346#define D_STATE 0x6104
1347#define DSTATE_GFX_RESET_I830 (1<<6)
1348#define DSTATE_PLL_D3_OFF (1<<3)
1349#define DSTATE_GFX_CLOCK_GATING (1<<1)
1350#define DSTATE_DOT_CLOCK_GATING (1<<0)
1351#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
1352# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30)
1353# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29)
1354# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
1355# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27)
1356# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26)
1357# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25)
1358# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
1359# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23)
1360# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22)
1361# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21)
1362# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20)
1363# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19)
1364# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18)
1365# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17)
1366# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16)
1367# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15)
1368# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14)
1369# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)
1370# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12)
1371# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1372# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1373# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1374# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1375# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7)
1376# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6)
1377# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
1378# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1379# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1380
1381
1382
1383
1384# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1385# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1386# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1387# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0)
1388# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0)
1389
1390#define RENCLK_GATE_D1 0x6204
1391# define BLITTER_CLOCK_GATE_DISABLE (1 << 13)
1392# define MPEG_CLOCK_GATE_DISABLE (1 << 12)
1393# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1394# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1395# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1396# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1397# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1398# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1399# define MAG_CLOCK_GATE_DISABLE (1 << 5)
1400
1401# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1402# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1403# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1404# define MECO_CLOCK_GATE_DISABLE (1 << 1)
1405
1406# define SV_CLOCK_GATE_DISABLE (1 << 0)
1407# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1408# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1409# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1410# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1411# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1412# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1413# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1414# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1415# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1416# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1417# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1418# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1419# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1420# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1421# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1422# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1423# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1424
1425# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1426
1427# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1428# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1429# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1430# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1431# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1432# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1433
1434# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1435# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1436# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1437# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1438# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1439# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1440# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1441# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1442# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1443# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1444# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1445# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1446# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1447# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1448# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1449# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1450# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1451# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1452# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1453
1454#define RENCLK_GATE_D2 0x6208
1455#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1456#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1457#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1458#define RAMCLK_GATE_D 0x6210
1459#define DEUC 0x6214
1460
1461#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
1462#define FW_CSPWRDWNEN (1<<15)
1463
1464#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1465
1466#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1467#define CDCLK_FREQ_SHIFT 4
1468#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1469#define CZCLK_FREQ_MASK 0xf
1470#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1471
1472
1473
1474
1475
1476#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
1477#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
1478#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492#define MCHBAR_MIRROR_BASE 0x10000
1493
1494#define MCHBAR_MIRROR_BASE_SNB 0x140000
1495
1496
1497#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
1498
1499
1500#define DCC 0x10200
1501#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1502#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1503#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1504#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1505#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1506#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1507
1508
1509#define CSHRDDR3CTL 0x101a8
1510#define CSHRDDR3CTL_DDR3 (1 << 2)
1511
1512
1513#define C0DRB3 0x10206
1514#define C1DRB3 0x10606
1515
1516
1517#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1518#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1519#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1520#define MAD_DIMM_ECC_MASK (0x3 << 24)
1521#define MAD_DIMM_ECC_OFF (0x0 << 24)
1522#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1523#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1524#define MAD_DIMM_ECC_ON (0x3 << 24)
1525#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1526#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1527#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20)
1528#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19)
1529#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1530#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1531#define MAD_DIMM_A_SELECT (0x1 << 16)
1532
1533#define MAD_DIMM_B_SIZE_SHIFT 8
1534#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1535#define MAD_DIMM_A_SIZE_SHIFT 0
1536#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1537
1538
1539#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1540#define MCH_SSKPD_WM0_MASK 0x3f
1541#define MCH_SSKPD_WM0_VAL 0xc
1542
1543#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
1544
1545
1546#define CLKCFG 0x10c00
1547#define CLKCFG_FSB_400 (5 << 0)
1548#define CLKCFG_FSB_533 (1 << 0)
1549#define CLKCFG_FSB_667 (3 << 0)
1550#define CLKCFG_FSB_800 (2 << 0)
1551#define CLKCFG_FSB_1067 (6 << 0)
1552#define CLKCFG_FSB_1333 (7 << 0)
1553
1554#define CLKCFG_FSB_1600 (4 << 0)
1555#define CLKCFG_FSB_1600_ALT (0 << 0)
1556#define CLKCFG_FSB_MASK (7 << 0)
1557#define CLKCFG_MEM_533 (1 << 4)
1558#define CLKCFG_MEM_667 (2 << 4)
1559#define CLKCFG_MEM_800 (3 << 4)
1560#define CLKCFG_MEM_MASK (7 << 4)
1561
1562#define TSC1 0x11001
1563#define TSE (1<<0)
1564#define TR1 0x11006
1565#define TSFS 0x11020
1566#define TSFS_SLOPE_MASK 0x0000ff00
1567#define TSFS_SLOPE_SHIFT 8
1568#define TSFS_INTR_MASK 0x000000ff
1569
1570#define CRSTANDVID 0x11100
1571#define PXVFREQ_BASE 0x11110
1572#define PXVFREQ_PX_MASK 0x7f000000
1573#define PXVFREQ_PX_SHIFT 24
1574#define VIDFREQ_BASE 0x11110
1575#define VIDFREQ1 0x11110
1576#define VIDFREQ2 0x11114
1577#define VIDFREQ3 0x11118
1578#define VIDFREQ4 0x1111c
1579#define VIDFREQ_P0_MASK 0x1f000000
1580#define VIDFREQ_P0_SHIFT 24
1581#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1582#define VIDFREQ_P0_CSCLK_SHIFT 20
1583#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1584#define VIDFREQ_P0_CRCLK_SHIFT 16
1585#define VIDFREQ_P1_MASK 0x00001f00
1586#define VIDFREQ_P1_SHIFT 8
1587#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1588#define VIDFREQ_P1_CSCLK_SHIFT 4
1589#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1590#define INTTOEXT_BASE_ILK 0x11300
1591#define INTTOEXT_BASE 0x11120
1592#define INTTOEXT_MAP3_SHIFT 24
1593#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1594#define INTTOEXT_MAP2_SHIFT 16
1595#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1596#define INTTOEXT_MAP1_SHIFT 8
1597#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1598#define INTTOEXT_MAP0_SHIFT 0
1599#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1600#define MEMSWCTL 0x11170
1601#define MEMCTL_CMD_MASK 0xe000
1602#define MEMCTL_CMD_SHIFT 13
1603#define MEMCTL_CMD_RCLK_OFF 0
1604#define MEMCTL_CMD_RCLK_ON 1
1605#define MEMCTL_CMD_CHFREQ 2
1606#define MEMCTL_CMD_CHVID 3
1607#define MEMCTL_CMD_VMMOFF 4
1608#define MEMCTL_CMD_VMMON 5
1609#define MEMCTL_CMD_STS (1<<12)
1610
1611#define MEMCTL_FREQ_MASK 0x0f00
1612#define MEMCTL_FREQ_SHIFT 8
1613#define MEMCTL_SFCAVM (1<<7)
1614#define MEMCTL_TGT_VID_MASK 0x007f
1615#define MEMIHYST 0x1117c
1616#define MEMINTREN 0x11180
1617#define MEMINT_RSEXIT_EN (1<<8)
1618#define MEMINT_CX_SUPR_EN (1<<7)
1619#define MEMINT_CONT_BUSY_EN (1<<6)
1620#define MEMINT_AVG_BUSY_EN (1<<5)
1621#define MEMINT_EVAL_CHG_EN (1<<4)
1622#define MEMINT_MON_IDLE_EN (1<<3)
1623#define MEMINT_UP_EVAL_EN (1<<2)
1624#define MEMINT_DOWN_EVAL_EN (1<<1)
1625#define MEMINT_SW_CMD_EN (1<<0)
1626#define MEMINTRSTR 0x11182
1627#define MEM_RSEXIT_MASK 0xc000
1628#define MEM_RSEXIT_SHIFT 14
1629#define MEM_CONT_BUSY_MASK 0x3000
1630#define MEM_CONT_BUSY_SHIFT 12
1631#define MEM_AVG_BUSY_MASK 0x0c00
1632#define MEM_AVG_BUSY_SHIFT 10
1633#define MEM_EVAL_CHG_MASK 0x0300
1634#define MEM_EVAL_BUSY_SHIFT 8
1635#define MEM_MON_IDLE_MASK 0x00c0
1636#define MEM_MON_IDLE_SHIFT 6
1637#define MEM_UP_EVAL_MASK 0x0030
1638#define MEM_UP_EVAL_SHIFT 4
1639#define MEM_DOWN_EVAL_MASK 0x000c
1640#define MEM_DOWN_EVAL_SHIFT 2
1641#define MEM_SW_CMD_MASK 0x0003
1642#define MEM_INT_STEER_GFX 0
1643#define MEM_INT_STEER_CMR 1
1644#define MEM_INT_STEER_SMI 2
1645#define MEM_INT_STEER_SCI 3
1646#define MEMINTRSTS 0x11184
1647#define MEMINT_RSEXIT (1<<7)
1648#define MEMINT_CONT_BUSY (1<<6)
1649#define MEMINT_AVG_BUSY (1<<5)
1650#define MEMINT_EVAL_CHG (1<<4)
1651#define MEMINT_MON_IDLE (1<<3)
1652#define MEMINT_UP_EVAL (1<<2)
1653#define MEMINT_DOWN_EVAL (1<<1)
1654#define MEMINT_SW_CMD (1<<0)
1655#define MEMMODECTL 0x11190
1656#define MEMMODE_BOOST_EN (1<<31)
1657#define MEMMODE_BOOST_FREQ_MASK 0x0f000000
1658#define MEMMODE_BOOST_FREQ_SHIFT 24
1659#define MEMMODE_IDLE_MODE_MASK 0x00030000
1660#define MEMMODE_IDLE_MODE_SHIFT 16
1661#define MEMMODE_IDLE_MODE_EVAL 0
1662#define MEMMODE_IDLE_MODE_CONT 1
1663#define MEMMODE_HWIDLE_EN (1<<15)
1664#define MEMMODE_SWMODE_EN (1<<14)
1665#define MEMMODE_RCLK_GATE (1<<13)
1666#define MEMMODE_HW_UPDATE (1<<12)
1667#define MEMMODE_FSTART_MASK 0x00000f00
1668#define MEMMODE_FSTART_SHIFT 8
1669#define MEMMODE_FMAX_MASK 0x000000f0
1670#define MEMMODE_FMAX_SHIFT 4
1671#define MEMMODE_FMIN_MASK 0x0000000f
1672#define RCBMAXAVG 0x1119c
1673#define MEMSWCTL2 0x1119e
1674#define SWMEMCMD_RENDER_OFF (0 << 13)
1675#define SWMEMCMD_RENDER_ON (1 << 13)
1676#define SWMEMCMD_SWFREQ (2 << 13)
1677#define SWMEMCMD_TARVID (3 << 13)
1678#define SWMEMCMD_VRM_OFF (4 << 13)
1679#define SWMEMCMD_VRM_ON (5 << 13)
1680#define CMDSTS (1<<12)
1681#define SFCAVM (1<<11)
1682#define SWFREQ_MASK 0x0380
1683#define SWFREQ_SHIFT 7
1684#define TARVID_MASK 0x001f
1685#define MEMSTAT_CTG 0x111a0
1686#define RCBMINAVG 0x111a0
1687#define RCUPEI 0x111b0
1688#define RCDNEI 0x111b4
1689#define RSTDBYCTL 0x111b8
1690#define RS1EN (1<<31)
1691#define RS2EN (1<<30)
1692#define RS3EN (1<<29)
1693#define D3RS3EN (1<<28)
1694#define SWPROMORSX (1<<27)
1695#define RCWAKERW (1<<26)
1696#define DPRSLPVREN (1<<25)
1697#define GFXTGHYST (1<<24)
1698#define RCX_SW_EXIT (1<<23)
1699#define RSX_STATUS_MASK (7<<20)
1700#define RSX_STATUS_ON (0<<20)
1701#define RSX_STATUS_RC1 (1<<20)
1702#define RSX_STATUS_RC1E (2<<20)
1703#define RSX_STATUS_RS1 (3<<20)
1704#define RSX_STATUS_RS2 (4<<20)
1705#define RSX_STATUS_RSVD (5<<20)
1706#define RSX_STATUS_RS3 (6<<20)
1707#define RSX_STATUS_RSVD2 (7<<20)
1708#define UWRCRSXE (1<<19)
1709#define RSCRP (1<<18)
1710#define JRSC (1<<17)
1711#define RS2INC0 (1<<16)
1712#define RS1CONTSAV_MASK (3<<14)
1713#define RS1CONTSAV_NO_RS1 (0<<14)
1714#define RS1CONTSAV_RSVD (1<<14)
1715#define RS1CONTSAV_SAVE_RS1 (2<<14)
1716#define RS1CONTSAV_FULL_RS1 (3<<14)
1717#define NORMSLEXLAT_MASK (3<<12)
1718#define SLOW_RS123 (0<<12)
1719#define SLOW_RS23 (1<<12)
1720#define SLOW_RS3 (2<<12)
1721#define NORMAL_RS123 (3<<12)
1722#define RCMODE_TIMEOUT (1<<11)
1723#define IMPROMOEN (1<<10)
1724#define RCENTSYNC (1<<9)
1725#define STATELOCK (1<<7)
1726#define RS_CSTATE_MASK (3<<4)
1727#define RS_CSTATE_C367_RS1 (0<<4)
1728#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1729#define RS_CSTATE_RSVD (2<<4)
1730#define RS_CSTATE_C367_RS2 (3<<4)
1731#define REDSAVES (1<<3)
1732#define REDRESTORES (1<<2)
1733#define VIDCTL 0x111c0
1734#define VIDSTS 0x111c8
1735#define VIDSTART 0x111cc
1736#define MEMSTAT_ILK 0x111f8
1737#define MEMSTAT_VID_MASK 0x7f00
1738#define MEMSTAT_VID_SHIFT 8
1739#define MEMSTAT_PSTATE_MASK 0x00f8
1740#define MEMSTAT_PSTATE_SHIFT 3
1741#define MEMSTAT_MON_ACTV (1<<2)
1742#define MEMSTAT_SRC_CTL_MASK 0x0003
1743#define MEMSTAT_SRC_CTL_CORE 0
1744#define MEMSTAT_SRC_CTL_TRB 1
1745#define MEMSTAT_SRC_CTL_THM 2
1746#define MEMSTAT_SRC_CTL_STDBY 3
1747#define RCPREVBSYTUPAVG 0x113b8
1748#define RCPREVBSYTDNAVG 0x113bc
1749#define PMMISC 0x11214
1750#define MCPPCE_EN (1<<0)
1751#define SDEW 0x1124c
1752#define CSIEW0 0x11250
1753#define CSIEW1 0x11254
1754#define CSIEW2 0x11258
1755#define PEW 0x1125c
1756#define DEW 0x11270
1757#define MCHAFE 0x112c0
1758#define CSIEC 0x112e0
1759#define DMIEC 0x112e4
1760#define DDREC 0x112e8
1761#define PEG0EC 0x112ec
1762#define PEG1EC 0x112f0
1763#define GFXEC 0x112f4
1764#define RPPREVBSYTUPAVG 0x113b8
1765#define RPPREVBSYTDNAVG 0x113bc
1766#define ECR 0x11600
1767#define ECR_GPFE (1<<31)
1768#define ECR_IMONE (1<<30)
1769#define ECR_CAP_MASK 0x0000001f
1770#define OGW0 0x11608
1771#define OGW1 0x1160c
1772#define EG0 0x11610
1773#define EG1 0x11614
1774#define EG2 0x11618
1775#define EG3 0x1161c
1776#define EG4 0x11620
1777#define EG5 0x11624
1778#define EG6 0x11628
1779#define EG7 0x1162c
1780#define PXW 0x11664
1781#define PXWL 0x11680
1782#define LCFUSE02 0x116c0
1783#define LCFUSE_HIV_MASK 0x000000ff
1784#define CSIPLL0 0x12c10
1785#define DDRMPLL1 0X12c20
1786#define PEG_BAND_GAP_DATA 0x14d68
1787
1788#define GEN6_GT_THREAD_STATUS_REG 0x13805c
1789#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1790#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1791
1792#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
1793#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
1794#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
1795
1796
1797
1798
1799#define CCID 0x2180
1800#define CCID_EN (1<<0)
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814#define CXT_SIZE 0x21a0
1815#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1816#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1817#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1818#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1819#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1820#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
1821 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1822 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1823#define GEN7_CXT_SIZE 0x21a8
1824#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1825#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1826#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1827#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1828#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1829#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1830#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1831 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1832
1833
1834
1835
1836
1837
1838#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
1839
1840#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
1841
1842
1843#define VLV_CLK_CTL2 0x101104
1844#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1845
1846
1847
1848
1849
1850#define OVADD 0x30000
1851#define DOVSTA 0x30008
1852#define OC_BUF (0x3<<20)
1853#define OGAMC5 0x30010
1854#define OGAMC4 0x30014
1855#define OGAMC3 0x30018
1856#define OGAMC2 0x3001c
1857#define OGAMC1 0x30020
1858#define OGAMC0 0x30024
1859
1860
1861
1862
1863
1864
1865#define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050)
1866#define PIPE_CRC_ENABLE (1 << 31)
1867
1868#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
1869#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
1870#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
1871
1872#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
1873#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
1874#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
1875
1876#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
1877#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28)
1878
1879#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
1880#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
1881#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
1882
1883#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
1884#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
1885#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
1886
1887#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
1888#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
1889#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
1890
1891#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
1892#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
1893#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
1894#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
1895#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
1896
1897#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
1898
1899#define _PIPE_CRC_RES_1_A_IVB 0x60064
1900#define _PIPE_CRC_RES_2_A_IVB 0x60068
1901#define _PIPE_CRC_RES_3_A_IVB 0x6006c
1902#define _PIPE_CRC_RES_4_A_IVB 0x60070
1903#define _PIPE_CRC_RES_5_A_IVB 0x60074
1904
1905#define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060)
1906#define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064)
1907#define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068)
1908#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c)
1909#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
1910
1911
1912#define _PIPE_CRC_RES_1_B_IVB 0x61064
1913#define _PIPE_CRC_RES_2_B_IVB 0x61068
1914#define _PIPE_CRC_RES_3_B_IVB 0x6106c
1915#define _PIPE_CRC_RES_4_B_IVB 0x61070
1916#define _PIPE_CRC_RES_5_B_IVB 0x61074
1917
1918#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000)
1919#define PIPE_CRC_RES_1_IVB(pipe) \
1920 _PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
1921#define PIPE_CRC_RES_2_IVB(pipe) \
1922 _PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
1923#define PIPE_CRC_RES_3_IVB(pipe) \
1924 _PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
1925#define PIPE_CRC_RES_4_IVB(pipe) \
1926 _PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
1927#define PIPE_CRC_RES_5_IVB(pipe) \
1928 _PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
1929
1930#define PIPE_CRC_RES_RED(pipe) \
1931 _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000)
1932#define PIPE_CRC_RES_GREEN(pipe) \
1933 _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000)
1934#define PIPE_CRC_RES_BLUE(pipe) \
1935 _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000)
1936#define PIPE_CRC_RES_RES1_I915(pipe) \
1937 _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000)
1938#define PIPE_CRC_RES_RES2_G4X(pipe) \
1939 _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
1940
1941
1942#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
1943#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
1944#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008)
1945#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c)
1946#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010)
1947#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014)
1948#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c)
1949#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020)
1950#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028)
1951
1952
1953#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000)
1954#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004)
1955#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008)
1956#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c)
1957#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010)
1958#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014)
1959#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c)
1960#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020)
1961#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028)
1962
1963#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1964#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1965#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1966#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1967#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1968#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
1969#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1970#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1971
1972
1973#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
1974#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
1975#define EDP_PSR_ENABLE (1<<31)
1976#define EDP_PSR_LINK_DISABLE (0<<27)
1977#define EDP_PSR_LINK_STANDBY (1<<27)
1978#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
1979#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
1980#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
1981#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
1982#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
1983#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
1984#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
1985#define EDP_PSR_TP1_TP2_SEL (0<<11)
1986#define EDP_PSR_TP1_TP3_SEL (1<<11)
1987#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
1988#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
1989#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
1990#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
1991#define EDP_PSR_TP1_TIME_500us (0<<4)
1992#define EDP_PSR_TP1_TIME_100us (1<<4)
1993#define EDP_PSR_TP1_TIME_2500us (2<<4)
1994#define EDP_PSR_TP1_TIME_0us (3<<4)
1995#define EDP_PSR_IDLE_FRAME_SHIFT 0
1996
1997#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
1998#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
1999#define EDP_PSR_DPCD_COMMAND 0x80060000
2000#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
2001#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
2002#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2003#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2004#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
2005
2006#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
2007#define EDP_PSR_STATUS_STATE_MASK (7<<29)
2008#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2009#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2010#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2011#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2012#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2013#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2014#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2015#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2016#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2017#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2018#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2019#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2020#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2021#define EDP_PSR_STATUS_COUNT_SHIFT 16
2022#define EDP_PSR_STATUS_COUNT_MASK 0xf
2023#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2024#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2025#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2026#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2027#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2028#define EDP_PSR_STATUS_IDLE_MASK 0xf
2029
2030#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
2031#define EDP_PSR_PERF_CNT_MASK 0xffffff
2032
2033#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
2034#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2035#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2036#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2037
2038
2039#define ADPA 0x61100
2040#define PCH_ADPA 0xe1100
2041#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
2042
2043#define ADPA_DAC_ENABLE (1<<31)
2044#define ADPA_DAC_DISABLE 0
2045#define ADPA_PIPE_SELECT_MASK (1<<30)
2046#define ADPA_PIPE_A_SELECT 0
2047#define ADPA_PIPE_B_SELECT (1<<30)
2048#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
2049
2050#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000
2051#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2052#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2053#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2054#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2055#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2056#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2057#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2058#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2059#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2060#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2061#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2062#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2063#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2064#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2065#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2066#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2067#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2068#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2069#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2070#define ADPA_SETS_HVPOLARITY 0
2071#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
2072#define ADPA_VSYNC_CNTL_ENABLE 0
2073#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
2074#define ADPA_HSYNC_CNTL_ENABLE 0
2075#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2076#define ADPA_VSYNC_ACTIVE_LOW 0
2077#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2078#define ADPA_HSYNC_ACTIVE_LOW 0
2079#define ADPA_DPMS_MASK (~(3<<10))
2080#define ADPA_DPMS_ON (0<<10)
2081#define ADPA_DPMS_SUSPEND (1<<10)
2082#define ADPA_DPMS_STANDBY (2<<10)
2083#define ADPA_DPMS_OFF (3<<10)
2084
2085
2086
2087#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
2088#define PORTB_HOTPLUG_INT_EN (1 << 29)
2089#define PORTC_HOTPLUG_INT_EN (1 << 28)
2090#define PORTD_HOTPLUG_INT_EN (1 << 27)
2091#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2092#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2093#define TV_HOTPLUG_INT_EN (1 << 18)
2094#define CRT_HOTPLUG_INT_EN (1 << 9)
2095#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2096 PORTC_HOTPLUG_INT_EN | \
2097 PORTD_HOTPLUG_INT_EN | \
2098 SDVOC_HOTPLUG_INT_EN | \
2099 SDVOB_HOTPLUG_INT_EN | \
2100 CRT_HOTPLUG_INT_EN)
2101#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2102#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2103
2104#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2105#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2106#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2107#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2108#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2109#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2110#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2111#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2112#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2113#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2114#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2115#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2116
2117#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
2118
2119
2120
2121
2122
2123
2124
2125#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2126#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2127#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2128
2129#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2130#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2131#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
2132#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2133#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2134#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2135
2136#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2137#define TV_HOTPLUG_INT_STATUS (1 << 10)
2138#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2139#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2140#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2141#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2142#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2143#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2144#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2145#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2146
2147
2148#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2149#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2150
2151
2152
2153
2154
2155
2156#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2157#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2158#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2159#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2160#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2161 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2162 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2163 PORTB_HOTPLUG_INT_STATUS | \
2164 PORTC_HOTPLUG_INT_STATUS | \
2165 PORTD_HOTPLUG_INT_STATUS)
2166
2167#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2168 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2169 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2170 PORTB_HOTPLUG_INT_STATUS | \
2171 PORTC_HOTPLUG_INT_STATUS | \
2172 PORTD_HOTPLUG_INT_STATUS)
2173
2174
2175
2176#define GEN3_SDVOB 0x61140
2177#define GEN3_SDVOC 0x61160
2178#define GEN4_HDMIB GEN3_SDVOB
2179#define GEN4_HDMIC GEN3_SDVOC
2180#define PCH_SDVOB 0xe1140
2181#define PCH_HDMIB PCH_SDVOB
2182#define PCH_HDMIC 0xe1150
2183#define PCH_HDMID 0xe1160
2184
2185#define PORT_DFT_I9XX 0x61150
2186#define DC_BALANCE_RESET (1 << 25)
2187#define PORT_DFT2_G4X 0x61154
2188#define DC_BALANCE_RESET_VLV (1 << 31)
2189#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2190#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2191#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2192
2193
2194#define SDVO_ENABLE (1 << 31)
2195#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2196#define SDVO_PIPE_SEL_MASK (1 << 30)
2197#define SDVO_PIPE_B_SELECT (1 << 30)
2198#define SDVO_STALL_SELECT (1 << 29)
2199#define SDVO_INTERRUPT_ENABLE (1 << 26)
2200
2201
2202
2203
2204
2205#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2206#define SDVO_PORT_MULTIPLY_SHIFT 23
2207#define SDVO_PHASE_SELECT_MASK (15 << 19)
2208#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2209#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2210#define SDVOC_GANG_MODE (1 << 16)
2211#define SDVO_BORDER_ENABLE (1 << 7)
2212#define SDVOB_PCIE_CONCURRENCY (1 << 3)
2213#define SDVO_DETECTED (1 << 2)
2214
2215#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2216 SDVO_INTERRUPT_ENABLE)
2217#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2218
2219
2220#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2221#define SDVO_COLOR_FORMAT_MASK (7 << 26)
2222#define SDVO_ENCODING_SDVO (0 << 10)
2223#define SDVO_ENCODING_HDMI (2 << 10)
2224#define HDMI_MODE_SELECT_HDMI (1 << 9)
2225#define HDMI_MODE_SELECT_DVI (0 << 9)
2226#define HDMI_COLOR_RANGE_16_235 (1 << 8)
2227#define SDVO_AUDIO_ENABLE (1 << 6)
2228
2229#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2230#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2231
2232
2233#define HDMI_COLOR_FORMAT_12bpc (3 << 26)
2234#define SDVOB_HOTPLUG_ENABLE (1 << 23)
2235
2236
2237#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2238#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2239
2240
2241
2242#define DVOA 0x61120
2243#define DVOB 0x61140
2244#define DVOC 0x61160
2245#define DVO_ENABLE (1 << 31)
2246#define DVO_PIPE_B_SELECT (1 << 30)
2247#define DVO_PIPE_STALL_UNUSED (0 << 28)
2248#define DVO_PIPE_STALL (1 << 28)
2249#define DVO_PIPE_STALL_TV (2 << 28)
2250#define DVO_PIPE_STALL_MASK (3 << 28)
2251#define DVO_USE_VGA_SYNC (1 << 15)
2252#define DVO_DATA_ORDER_I740 (0 << 14)
2253#define DVO_DATA_ORDER_FP (1 << 14)
2254#define DVO_VSYNC_DISABLE (1 << 11)
2255#define DVO_HSYNC_DISABLE (1 << 10)
2256#define DVO_VSYNC_TRISTATE (1 << 9)
2257#define DVO_HSYNC_TRISTATE (1 << 8)
2258#define DVO_BORDER_ENABLE (1 << 7)
2259#define DVO_DATA_ORDER_GBRG (1 << 6)
2260#define DVO_DATA_ORDER_RGGB (0 << 6)
2261#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2262#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2263#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2264#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2265#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2266#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1)
2267#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)
2268#define DVO_PRESERVE_MASK (0x7<<24)
2269#define DVOA_SRCDIM 0x61124
2270#define DVOB_SRCDIM 0x61144
2271#define DVOC_SRCDIM 0x61164
2272#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2273#define DVO_SRCDIM_VERTICAL_SHIFT 0
2274
2275
2276#define LVDS 0x61180
2277
2278
2279
2280
2281#define LVDS_PORT_EN (1 << 31)
2282
2283#define LVDS_PIPEB_SELECT (1 << 30)
2284#define LVDS_PIPE_MASK (1 << 30)
2285#define LVDS_PIPE(pipe) ((pipe) << 30)
2286
2287#define LVDS_ENABLE_DITHER (1 << 25)
2288
2289#define LVDS_VSYNC_POLARITY (1 << 21)
2290#define LVDS_HSYNC_POLARITY (1 << 20)
2291
2292
2293#define LVDS_BORDER_ENABLE (1 << 15)
2294
2295
2296
2297
2298#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2299#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2300#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2301
2302
2303
2304
2305
2306#define LVDS_A3_POWER_MASK (3 << 6)
2307#define LVDS_A3_POWER_DOWN (0 << 6)
2308#define LVDS_A3_POWER_UP (3 << 6)
2309
2310
2311
2312
2313#define LVDS_CLKB_POWER_MASK (3 << 4)
2314#define LVDS_CLKB_POWER_DOWN (0 << 4)
2315#define LVDS_CLKB_POWER_UP (3 << 4)
2316
2317
2318
2319
2320
2321#define LVDS_B0B3_POWER_MASK (3 << 2)
2322#define LVDS_B0B3_POWER_DOWN (0 << 2)
2323#define LVDS_B0B3_POWER_UP (3 << 2)
2324
2325
2326#define VIDEO_DIP_DATA 0x61178
2327
2328
2329
2330#define VIDEO_DIP_DATA_SIZE 32
2331#define VIDEO_DIP_VSC_DATA_SIZE 36
2332#define VIDEO_DIP_CTL 0x61170
2333
2334#define VIDEO_DIP_ENABLE (1 << 31)
2335#define VIDEO_DIP_PORT_B (1 << 29)
2336#define VIDEO_DIP_PORT_C (2 << 29)
2337#define VIDEO_DIP_PORT_D (3 << 29)
2338#define VIDEO_DIP_PORT_MASK (3 << 29)
2339#define VIDEO_DIP_ENABLE_GCP (1 << 25)
2340#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2341#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2342#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
2343#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2344#define VIDEO_DIP_SELECT_AVI (0 << 19)
2345#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2346#define VIDEO_DIP_SELECT_SPD (3 << 19)
2347#define VIDEO_DIP_SELECT_MASK (3 << 19)
2348#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2349#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2350#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2351#define VIDEO_DIP_FREQ_MASK (3 << 16)
2352
2353#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2354#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2355#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2356#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2357#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2358#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2359
2360
2361#define PP_STATUS 0x61200
2362#define PP_ON (1 << 31)
2363
2364
2365
2366
2367
2368
2369
2370#define PP_READY (1 << 30)
2371#define PP_SEQUENCE_NONE (0 << 28)
2372#define PP_SEQUENCE_POWER_UP (1 << 28)
2373#define PP_SEQUENCE_POWER_DOWN (2 << 28)
2374#define PP_SEQUENCE_MASK (3 << 28)
2375#define PP_SEQUENCE_SHIFT 28
2376#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
2377#define PP_SEQUENCE_STATE_MASK 0x0000000f
2378#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2379#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2380#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2381#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2382#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2383#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2384#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2385#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2386#define PP_SEQUENCE_STATE_RESET (0xf << 0)
2387#define PP_CONTROL 0x61204
2388#define POWER_TARGET_ON (1 << 0)
2389#define PP_ON_DELAYS 0x61208
2390#define PP_OFF_DELAYS 0x6120c
2391#define PP_DIVISOR 0x61210
2392
2393
2394#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
2395#define PFIT_ENABLE (1 << 31)
2396#define PFIT_PIPE_MASK (3 << 29)
2397#define PFIT_PIPE_SHIFT 29
2398#define VERT_INTERP_DISABLE (0 << 10)
2399#define VERT_INTERP_BILINEAR (1 << 10)
2400#define VERT_INTERP_MASK (3 << 10)
2401#define VERT_AUTO_SCALE (1 << 9)
2402#define HORIZ_INTERP_DISABLE (0 << 6)
2403#define HORIZ_INTERP_BILINEAR (1 << 6)
2404#define HORIZ_INTERP_MASK (3 << 6)
2405#define HORIZ_AUTO_SCALE (1 << 5)
2406#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2407#define PFIT_FILTER_FUZZY (0 << 24)
2408#define PFIT_SCALING_AUTO (0 << 26)
2409#define PFIT_SCALING_PROGRAMMED (1 << 26)
2410#define PFIT_SCALING_PILLAR (2 << 26)
2411#define PFIT_SCALING_LETTER (3 << 26)
2412#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
2413
2414#define PFIT_VERT_SCALE_SHIFT 20
2415#define PFIT_VERT_SCALE_MASK 0xfff00000
2416#define PFIT_HORIZ_SCALE_SHIFT 4
2417#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2418
2419#define PFIT_VERT_SCALE_SHIFT_965 16
2420#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2421#define PFIT_HORIZ_SCALE_SHIFT_965 0
2422#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2423
2424#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
2425
2426#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
2427#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
2428#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2429 _VLV_BLC_PWM_CTL2_B)
2430
2431#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
2432#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
2433#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2434 _VLV_BLC_PWM_CTL_B)
2435
2436#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
2437#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
2438#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2439 _VLV_BLC_HIST_CTL_B)
2440
2441
2442#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250)
2443#define BLM_PWM_ENABLE (1 << 31)
2444#define BLM_COMBINATION_MODE (1 << 30)
2445#define BLM_PIPE_SELECT (1 << 29)
2446#define BLM_PIPE_SELECT_IVB (3 << 29)
2447#define BLM_PIPE_A (0 << 29)
2448#define BLM_PIPE_B (1 << 29)
2449#define BLM_PIPE_C (2 << 29)
2450#define BLM_TRANSCODER_A BLM_PIPE_A
2451#define BLM_TRANSCODER_B BLM_PIPE_B
2452#define BLM_TRANSCODER_C BLM_PIPE_C
2453#define BLM_TRANSCODER_EDP (3 << 29)
2454#define BLM_PIPE(pipe) ((pipe) << 29)
2455#define BLM_POLARITY_I965 (1 << 28)
2456#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2457#define BLM_PHASE_IN_ENABLE (1 << 25)
2458#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2459#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2460#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2461#define BLM_PHASE_IN_COUNT_SHIFT (8)
2462#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2463#define BLM_PHASE_IN_INCR_SHIFT (0)
2464#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
2465#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254)
2466
2467
2468
2469
2470
2471
2472#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2473#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2474#define BLM_LEGACY_MODE (1 << 16)
2475
2476
2477
2478
2479
2480
2481
2482#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2483#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
2484#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2485#define BLM_POLARITY_PNV (1 << 0)
2486
2487#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260)
2488
2489
2490
2491#define BLC_PWM_CPU_CTL2 0x48250
2492#define BLC_PWM_CPU_CTL 0x48254
2493
2494#define HSW_BLC_PWM2_CTL 0x48350
2495
2496
2497
2498#define BLC_PWM_PCH_CTL1 0xc8250
2499#define BLM_PCH_PWM_ENABLE (1 << 31)
2500#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2501#define BLM_PCH_POLARITY (1 << 29)
2502#define BLC_PWM_PCH_CTL2 0xc8254
2503
2504#define UTIL_PIN_CTL 0x48400
2505#define UTIL_PIN_ENABLE (1 << 31)
2506
2507#define PCH_GTC_CTL 0xe7000
2508#define PCH_GTC_ENABLE (1 << 31)
2509
2510
2511#define TV_CTL 0x68000
2512
2513# define TV_ENC_ENABLE (1 << 31)
2514
2515# define TV_ENC_PIPEB_SELECT (1 << 30)
2516
2517# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2518
2519# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2520
2521# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2522
2523# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2524# define TV_TRILEVEL_SYNC (1 << 21)
2525
2526# define TV_SLOW_SYNC (1 << 20)
2527
2528# define TV_OVERSAMPLE_4X (0 << 18)
2529
2530# define TV_OVERSAMPLE_2X (1 << 18)
2531
2532# define TV_OVERSAMPLE_NONE (2 << 18)
2533
2534# define TV_OVERSAMPLE_8X (3 << 18)
2535
2536# define TV_PROGRESSIVE (1 << 17)
2537
2538# define TV_PAL_BURST (1 << 16)
2539
2540# define TV_YC_SKEW_MASK (7 << 12)
2541
2542# define TV_ENC_SDP_FIX (1 << 11)
2543
2544
2545
2546
2547
2548# define TV_ENC_C0_FIX (1 << 10)
2549
2550# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2551# define TV_FUSE_STATE_MASK (3 << 4)
2552
2553# define TV_FUSE_STATE_ENABLED (0 << 4)
2554
2555# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2556
2557# define TV_FUSE_STATE_DISABLED (2 << 4)
2558
2559# define TV_TEST_MODE_NORMAL (0 << 0)
2560
2561# define TV_TEST_MODE_PATTERN_1 (1 << 0)
2562
2563# define TV_TEST_MODE_PATTERN_2 (2 << 0)
2564
2565# define TV_TEST_MODE_PATTERN_3 (3 << 0)
2566
2567# define TV_TEST_MODE_PATTERN_4 (4 << 0)
2568
2569# define TV_TEST_MODE_PATTERN_5 (5 << 0)
2570
2571
2572
2573
2574
2575# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2576# define TV_TEST_MODE_MASK (7 << 0)
2577
2578#define TV_DAC 0x68004
2579# define TV_DAC_SAVE 0x00ffff00
2580
2581
2582
2583
2584
2585# define TVDAC_STATE_CHG (1 << 31)
2586# define TVDAC_SENSE_MASK (7 << 28)
2587
2588# define TVDAC_A_SENSE (1 << 30)
2589
2590# define TVDAC_B_SENSE (1 << 29)
2591
2592# define TVDAC_C_SENSE (1 << 28)
2593
2594
2595
2596
2597
2598
2599# define TVDAC_STATE_CHG_EN (1 << 27)
2600
2601# define TVDAC_A_SENSE_CTL (1 << 26)
2602
2603# define TVDAC_B_SENSE_CTL (1 << 25)
2604
2605# define TVDAC_C_SENSE_CTL (1 << 24)
2606
2607# define DAC_CTL_OVERRIDE (1 << 7)
2608
2609# define ENC_TVDAC_SLEW_FAST (1 << 6)
2610# define DAC_A_1_3_V (0 << 4)
2611# define DAC_A_1_1_V (1 << 4)
2612# define DAC_A_0_7_V (2 << 4)
2613# define DAC_A_MASK (3 << 4)
2614# define DAC_B_1_3_V (0 << 2)
2615# define DAC_B_1_1_V (1 << 2)
2616# define DAC_B_0_7_V (2 << 2)
2617# define DAC_B_MASK (3 << 2)
2618# define DAC_C_1_3_V (0 << 0)
2619# define DAC_C_1_1_V (1 << 0)
2620# define DAC_C_0_7_V (2 << 0)
2621# define DAC_C_MASK (3 << 0)
2622
2623
2624
2625
2626
2627
2628
2629#define TV_CSC_Y 0x68010
2630# define TV_RY_MASK 0x07ff0000
2631# define TV_RY_SHIFT 16
2632# define TV_GY_MASK 0x00000fff
2633# define TV_GY_SHIFT 0
2634
2635#define TV_CSC_Y2 0x68014
2636# define TV_BY_MASK 0x07ff0000
2637# define TV_BY_SHIFT 16
2638
2639
2640
2641
2642
2643# define TV_AY_MASK 0x000003ff
2644# define TV_AY_SHIFT 0
2645
2646#define TV_CSC_U 0x68018
2647# define TV_RU_MASK 0x07ff0000
2648# define TV_RU_SHIFT 16
2649# define TV_GU_MASK 0x000007ff
2650# define TV_GU_SHIFT 0
2651
2652#define TV_CSC_U2 0x6801c
2653# define TV_BU_MASK 0x07ff0000
2654# define TV_BU_SHIFT 16
2655
2656
2657
2658
2659
2660# define TV_AU_MASK 0x000003ff
2661# define TV_AU_SHIFT 0
2662
2663#define TV_CSC_V 0x68020
2664# define TV_RV_MASK 0x0fff0000
2665# define TV_RV_SHIFT 16
2666# define TV_GV_MASK 0x000007ff
2667# define TV_GV_SHIFT 0
2668
2669#define TV_CSC_V2 0x68024
2670# define TV_BV_MASK 0x07ff0000
2671# define TV_BV_SHIFT 16
2672
2673
2674
2675
2676
2677# define TV_AV_MASK 0x000007ff
2678# define TV_AV_SHIFT 0
2679
2680#define TV_CLR_KNOBS 0x68028
2681
2682# define TV_BRIGHTNESS_MASK 0xff000000
2683# define TV_BRIGHTNESS_SHIFT 24
2684
2685# define TV_CONTRAST_MASK 0x00ff0000
2686# define TV_CONTRAST_SHIFT 16
2687
2688# define TV_SATURATION_MASK 0x0000ff00
2689# define TV_SATURATION_SHIFT 8
2690
2691# define TV_HUE_MASK 0x000000ff
2692# define TV_HUE_SHIFT 0
2693
2694#define TV_CLR_LEVEL 0x6802c
2695
2696# define TV_BLACK_LEVEL_MASK 0x01ff0000
2697# define TV_BLACK_LEVEL_SHIFT 16
2698
2699# define TV_BLANK_LEVEL_MASK 0x000001ff
2700# define TV_BLANK_LEVEL_SHIFT 0
2701
2702#define TV_H_CTL_1 0x68030
2703
2704# define TV_HSYNC_END_MASK 0x1fff0000
2705# define TV_HSYNC_END_SHIFT 16
2706
2707# define TV_HTOTAL_MASK 0x00001fff
2708# define TV_HTOTAL_SHIFT 0
2709
2710#define TV_H_CTL_2 0x68034
2711
2712# define TV_BURST_ENA (1 << 31)
2713
2714# define TV_HBURST_START_SHIFT 16
2715# define TV_HBURST_START_MASK 0x1fff0000
2716
2717# define TV_HBURST_LEN_SHIFT 0
2718# define TV_HBURST_LEN_MASK 0x0001fff
2719
2720#define TV_H_CTL_3 0x68038
2721
2722# define TV_HBLANK_END_SHIFT 16
2723# define TV_HBLANK_END_MASK 0x1fff0000
2724
2725# define TV_HBLANK_START_SHIFT 0
2726# define TV_HBLANK_START_MASK 0x0001fff
2727
2728#define TV_V_CTL_1 0x6803c
2729
2730# define TV_NBR_END_SHIFT 16
2731# define TV_NBR_END_MASK 0x07ff0000
2732
2733# define TV_VI_END_F1_SHIFT 8
2734# define TV_VI_END_F1_MASK 0x00003f00
2735
2736# define TV_VI_END_F2_SHIFT 0
2737# define TV_VI_END_F2_MASK 0x0000003f
2738
2739#define TV_V_CTL_2 0x68040
2740
2741# define TV_VSYNC_LEN_MASK 0x07ff0000
2742# define TV_VSYNC_LEN_SHIFT 16
2743
2744
2745
2746# define TV_VSYNC_START_F1_MASK 0x00007f00
2747# define TV_VSYNC_START_F1_SHIFT 8
2748
2749
2750
2751
2752# define TV_VSYNC_START_F2_MASK 0x0000007f
2753# define TV_VSYNC_START_F2_SHIFT 0
2754
2755#define TV_V_CTL_3 0x68044
2756
2757# define TV_EQUAL_ENA (1 << 31)
2758
2759# define TV_VEQ_LEN_MASK 0x007f0000
2760# define TV_VEQ_LEN_SHIFT 16
2761
2762
2763
2764# define TV_VEQ_START_F1_MASK 0x0007f00
2765# define TV_VEQ_START_F1_SHIFT 8
2766
2767
2768
2769
2770# define TV_VEQ_START_F2_MASK 0x000007f
2771# define TV_VEQ_START_F2_SHIFT 0
2772
2773#define TV_V_CTL_4 0x68048
2774
2775
2776
2777
2778# define TV_VBURST_START_F1_MASK 0x003f0000
2779# define TV_VBURST_START_F1_SHIFT 16
2780
2781
2782
2783
2784# define TV_VBURST_END_F1_MASK 0x000000ff
2785# define TV_VBURST_END_F1_SHIFT 0
2786
2787#define TV_V_CTL_5 0x6804c
2788
2789
2790
2791
2792# define TV_VBURST_START_F2_MASK 0x003f0000
2793# define TV_VBURST_START_F2_SHIFT 16
2794
2795
2796
2797
2798# define TV_VBURST_END_F2_MASK 0x000000ff
2799# define TV_VBURST_END_F2_SHIFT 0
2800
2801#define TV_V_CTL_6 0x68050
2802
2803
2804
2805
2806# define TV_VBURST_START_F3_MASK 0x003f0000
2807# define TV_VBURST_START_F3_SHIFT 16
2808
2809
2810
2811
2812# define TV_VBURST_END_F3_MASK 0x000000ff
2813# define TV_VBURST_END_F3_SHIFT 0
2814
2815#define TV_V_CTL_7 0x68054
2816
2817
2818
2819
2820# define TV_VBURST_START_F4_MASK 0x003f0000
2821# define TV_VBURST_START_F4_SHIFT 16
2822
2823
2824
2825
2826# define TV_VBURST_END_F4_MASK 0x000000ff
2827# define TV_VBURST_END_F4_SHIFT 0
2828
2829#define TV_SC_CTL_1 0x68060
2830
2831# define TV_SC_DDA1_EN (1 << 31)
2832
2833# define TV_SC_DDA2_EN (1 << 30)
2834
2835# define TV_SC_DDA3_EN (1 << 29)
2836
2837# define TV_SC_RESET_EVERY_2 (0 << 24)
2838
2839# define TV_SC_RESET_EVERY_4 (1 << 24)
2840
2841# define TV_SC_RESET_EVERY_8 (2 << 24)
2842
2843# define TV_SC_RESET_NEVER (3 << 24)
2844
2845# define TV_BURST_LEVEL_MASK 0x00ff0000
2846# define TV_BURST_LEVEL_SHIFT 16
2847
2848# define TV_SCDDA1_INC_MASK 0x00000fff
2849# define TV_SCDDA1_INC_SHIFT 0
2850
2851#define TV_SC_CTL_2 0x68064
2852
2853# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2854# define TV_SCDDA2_SIZE_SHIFT 16
2855
2856# define TV_SCDDA2_INC_MASK 0x00007fff
2857# define TV_SCDDA2_INC_SHIFT 0
2858
2859#define TV_SC_CTL_3 0x68068
2860
2861# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2862# define TV_SCDDA3_SIZE_SHIFT 16
2863
2864# define TV_SCDDA3_INC_MASK 0x00007fff
2865# define TV_SCDDA3_INC_SHIFT 0
2866
2867#define TV_WIN_POS 0x68070
2868
2869# define TV_XPOS_MASK 0x1fff0000
2870# define TV_XPOS_SHIFT 16
2871
2872# define TV_YPOS_MASK 0x00000fff
2873# define TV_YPOS_SHIFT 0
2874
2875#define TV_WIN_SIZE 0x68074
2876
2877# define TV_XSIZE_MASK 0x1fff0000
2878# define TV_XSIZE_SHIFT 16
2879
2880
2881
2882
2883
2884# define TV_YSIZE_MASK 0x00000fff
2885# define TV_YSIZE_SHIFT 0
2886
2887#define TV_FILTER_CTL_1 0x68080
2888
2889
2890
2891
2892
2893
2894# define TV_AUTO_SCALE (1 << 31)
2895
2896
2897
2898
2899# define TV_V_FILTER_BYPASS (1 << 29)
2900
2901# define TV_VADAPT (1 << 28)
2902# define TV_VADAPT_MODE_MASK (3 << 26)
2903
2904# define TV_VADAPT_MODE_LEAST (0 << 26)
2905
2906# define TV_VADAPT_MODE_MODERATE (1 << 26)
2907
2908# define TV_VADAPT_MODE_MOST (3 << 26)
2909
2910
2911
2912
2913
2914
2915
2916
2917# define TV_HSCALE_FRAC_MASK 0x00003fff
2918# define TV_HSCALE_FRAC_SHIFT 0
2919
2920#define TV_FILTER_CTL_2 0x68084
2921
2922
2923
2924
2925
2926# define TV_VSCALE_INT_MASK 0x00038000
2927# define TV_VSCALE_INT_SHIFT 15
2928
2929
2930
2931
2932
2933# define TV_VSCALE_FRAC_MASK 0x00007fff
2934# define TV_VSCALE_FRAC_SHIFT 0
2935
2936#define TV_FILTER_CTL_3 0x68088
2937
2938
2939
2940
2941
2942
2943
2944# define TV_VSCALE_IP_INT_MASK 0x00038000
2945# define TV_VSCALE_IP_INT_SHIFT 15
2946
2947
2948
2949
2950
2951
2952
2953# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2954# define TV_VSCALE_IP_FRAC_SHIFT 0
2955
2956#define TV_CC_CONTROL 0x68090
2957# define TV_CC_ENABLE (1 << 31)
2958
2959
2960
2961
2962
2963# define TV_CC_FID_MASK (1 << 27)
2964# define TV_CC_FID_SHIFT 27
2965
2966# define TV_CC_HOFF_MASK 0x03ff0000
2967# define TV_CC_HOFF_SHIFT 16
2968
2969# define TV_CC_LINE_MASK 0x0000003f
2970# define TV_CC_LINE_SHIFT 0
2971
2972#define TV_CC_DATA 0x68094
2973# define TV_CC_RDY (1 << 31)
2974
2975# define TV_CC_DATA_2_MASK 0x007f0000
2976# define TV_CC_DATA_2_SHIFT 16
2977
2978# define TV_CC_DATA_1_MASK 0x0000007f
2979# define TV_CC_DATA_1_SHIFT 0
2980
2981#define TV_H_LUMA_0 0x68100
2982#define TV_H_LUMA_59 0x681ec
2983#define TV_H_CHROMA_0 0x68200
2984#define TV_H_CHROMA_59 0x682ec
2985#define TV_V_LUMA_0 0x68300
2986#define TV_V_LUMA_42 0x683a8
2987#define TV_V_CHROMA_0 0x68400
2988#define TV_V_CHROMA_42 0x684a8
2989
2990
2991#define DP_A 0x64000
2992#define DP_B 0x64100
2993#define DP_C 0x64200
2994#define DP_D 0x64300
2995
2996#define DP_PORT_EN (1 << 31)
2997#define DP_PIPEB_SELECT (1 << 30)
2998#define DP_PIPE_MASK (1 << 30)
2999
3000
3001#define DP_LINK_TRAIN_PAT_1 (0 << 28)
3002#define DP_LINK_TRAIN_PAT_2 (1 << 28)
3003#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3004#define DP_LINK_TRAIN_OFF (3 << 28)
3005#define DP_LINK_TRAIN_MASK (3 << 28)
3006#define DP_LINK_TRAIN_SHIFT 28
3007
3008
3009#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3010#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3011#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3012#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3013#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3014#define DP_LINK_TRAIN_SHIFT_CPT 8
3015
3016
3017#define DP_VOLTAGE_0_4 (0 << 25)
3018#define DP_VOLTAGE_0_6 (1 << 25)
3019#define DP_VOLTAGE_0_8 (2 << 25)
3020#define DP_VOLTAGE_1_2 (3 << 25)
3021#define DP_VOLTAGE_MASK (7 << 25)
3022#define DP_VOLTAGE_SHIFT 25
3023
3024
3025
3026
3027#define DP_PRE_EMPHASIS_0 (0 << 22)
3028#define DP_PRE_EMPHASIS_3_5 (1 << 22)
3029#define DP_PRE_EMPHASIS_6 (2 << 22)
3030#define DP_PRE_EMPHASIS_9_5 (3 << 22)
3031#define DP_PRE_EMPHASIS_MASK (7 << 22)
3032#define DP_PRE_EMPHASIS_SHIFT 22
3033
3034
3035#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3036#define DP_PORT_WIDTH_MASK (7 << 19)
3037
3038
3039#define DP_ENHANCED_FRAMING (1 << 18)
3040
3041
3042#define DP_PLL_FREQ_270MHZ (0 << 16)
3043#define DP_PLL_FREQ_160MHZ (1 << 16)
3044#define DP_PLL_FREQ_MASK (3 << 16)
3045
3046
3047#define DP_PORT_REVERSAL (1 << 15)
3048
3049
3050#define DP_PLL_ENABLE (1 << 14)
3051
3052
3053#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3054
3055#define DP_SCRAMBLING_DISABLE (1 << 12)
3056#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3057
3058
3059#define DP_COLOR_RANGE_16_235 (1 << 8)
3060
3061
3062#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3063
3064
3065#define DP_SYNC_VS_HIGH (1 << 4)
3066#define DP_SYNC_HS_HIGH (1 << 3)
3067
3068
3069#define DP_DETECTED (1 << 2)
3070
3071
3072
3073
3074
3075
3076#define DPA_AUX_CH_CTL 0x64010
3077#define DPA_AUX_CH_DATA1 0x64014
3078#define DPA_AUX_CH_DATA2 0x64018
3079#define DPA_AUX_CH_DATA3 0x6401c
3080#define DPA_AUX_CH_DATA4 0x64020
3081#define DPA_AUX_CH_DATA5 0x64024
3082
3083#define DPB_AUX_CH_CTL 0x64110
3084#define DPB_AUX_CH_DATA1 0x64114
3085#define DPB_AUX_CH_DATA2 0x64118
3086#define DPB_AUX_CH_DATA3 0x6411c
3087#define DPB_AUX_CH_DATA4 0x64120
3088#define DPB_AUX_CH_DATA5 0x64124
3089
3090#define DPC_AUX_CH_CTL 0x64210
3091#define DPC_AUX_CH_DATA1 0x64214
3092#define DPC_AUX_CH_DATA2 0x64218
3093#define DPC_AUX_CH_DATA3 0x6421c
3094#define DPC_AUX_CH_DATA4 0x64220
3095#define DPC_AUX_CH_DATA5 0x64224
3096
3097#define DPD_AUX_CH_CTL 0x64310
3098#define DPD_AUX_CH_DATA1 0x64314
3099#define DPD_AUX_CH_DATA2 0x64318
3100#define DPD_AUX_CH_DATA3 0x6431c
3101#define DPD_AUX_CH_DATA4 0x64320
3102#define DPD_AUX_CH_DATA5 0x64324
3103
3104#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3105#define DP_AUX_CH_CTL_DONE (1 << 30)
3106#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3107#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3108#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3109#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3110#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3111#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3112#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3113#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3114#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3115#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3116#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3117#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3118#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3119#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3120#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3121#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3122#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3123#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3124#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139#define _PIPEA_DATA_M_G4X 0x70050
3140#define _PIPEB_DATA_M_G4X 0x71050
3141
3142
3143#define TU_SIZE(x) (((x)-1) << 25)
3144#define TU_SIZE_SHIFT 25
3145#define TU_SIZE_MASK (0x3f << 25)
3146
3147#define DATA_LINK_M_N_MASK (0xffffff)
3148#define DATA_LINK_N_MAX (0x800000)
3149
3150#define _PIPEA_DATA_N_G4X 0x70054
3151#define _PIPEB_DATA_N_G4X 0x71054
3152#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165#define _PIPEA_LINK_M_G4X 0x70060
3166#define _PIPEB_LINK_M_G4X 0x71060
3167#define PIPEA_DP_LINK_M_MASK (0xffffff)
3168
3169#define _PIPEA_LINK_N_G4X 0x70064
3170#define _PIPEB_LINK_N_G4X 0x71064
3171#define PIPEA_DP_LINK_N_MASK (0xffffff)
3172
3173#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3174#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3175#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3176#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3177
3178
3179
3180
3181#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000)
3182#define DSL_LINEMASK_GEN2 0x00000fff
3183#define DSL_LINEMASK_GEN3 0x00001fff
3184#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008)
3185#define PIPECONF_ENABLE (1<<31)
3186#define PIPECONF_DISABLE 0
3187#define PIPECONF_DOUBLE_WIDE (1<<30)
3188#define I965_PIPECONF_ACTIVE (1<<30)
3189#define PIPECONF_DSI_PLL_LOCKED (1<<29)
3190#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
3191#define PIPECONF_SINGLE_WIDE 0
3192#define PIPECONF_PIPE_UNLOCKED 0
3193#define PIPECONF_PIPE_LOCKED (1<<25)
3194#define PIPECONF_PALETTE 0
3195#define PIPECONF_GAMMA (1<<24)
3196#define PIPECONF_FORCE_BORDER (1<<25)
3197#define PIPECONF_INTERLACE_MASK (7 << 21)
3198#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
3199
3200
3201#define PIPECONF_PROGRESSIVE (0 << 21)
3202#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21)
3203#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21)
3204#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3205#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
3206
3207
3208
3209#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3210#define PIPECONF_INTERLACED_ILK (3 << 21)
3211#define PIPECONF_INTERLACED_DBL_ILK (4 << 21)
3212#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21)
3213#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
3214#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
3215#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
3216#define PIPECONF_BPC_MASK (0x7 << 5)
3217#define PIPECONF_8BPC (0<<5)
3218#define PIPECONF_10BPC (1<<5)
3219#define PIPECONF_6BPC (2<<5)
3220#define PIPECONF_12BPC (3<<5)
3221#define PIPECONF_DITHER_EN (1<<4)
3222#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3223#define PIPECONF_DITHER_TYPE_SP (0<<2)
3224#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3225#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3226#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3227#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
3228#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3229#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
3230#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3231#define PIPE_CRC_DONE_ENABLE (1UL<<28)
3232#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
3233#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
3234#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3235#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3236#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3237#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
3238#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
3239#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3240#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3241#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3242#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18)
3243#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18)
3244#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
3245#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
3246#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
3247#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
3248#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14)
3249#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3250#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3251#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
3252#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
3253#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3254#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3255#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3256#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3257#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3258#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3259#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3260#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2)
3261#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2)
3262#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3263#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3264
3265#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
3266#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
3267#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
3268#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
3269#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
3270#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
3271
3272#define _PIPE_MISC_A 0x70030
3273#define _PIPE_MISC_B 0x71030
3274#define PIPEMISC_DITHER_BPC_MASK (7<<5)
3275#define PIPEMISC_DITHER_8_BPC (0<<5)
3276#define PIPEMISC_DITHER_10_BPC (1<<5)
3277#define PIPEMISC_DITHER_6_BPC (2<<5)
3278#define PIPEMISC_DITHER_12_BPC (3<<5)
3279#define PIPEMISC_DITHER_ENABLE (1<<4)
3280#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3281#define PIPEMISC_DITHER_TYPE_SP (0<<2)
3282#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
3283
3284#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3285#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
3286#define PIPEB_HLINE_INT_EN (1<<28)
3287#define PIPEB_VBLANK_INT_EN (1<<27)
3288#define SPRITED_FLIPDONE_INT_EN (1<<26)
3289#define SPRITEC_FLIPDONE_INT_EN (1<<25)
3290#define PLANEB_FLIPDONE_INT_EN (1<<24)
3291#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
3292#define PIPEA_HLINE_INT_EN (1<<20)
3293#define PIPEA_VBLANK_INT_EN (1<<19)
3294#define SPRITEB_FLIPDONE_INT_EN (1<<18)
3295#define SPRITEA_FLIPDONE_INT_EN (1<<17)
3296#define PLANEA_FLIPDONE_INT_EN (1<<16)
3297
3298#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c)
3299#define CURSORB_INVALID_GTT_INT_EN (1<<23)
3300#define CURSORA_INVALID_GTT_INT_EN (1<<22)
3301#define SPRITED_INVALID_GTT_INT_EN (1<<21)
3302#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3303#define PLANEB_INVALID_GTT_INT_EN (1<<19)
3304#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3305#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3306#define PLANEA_INVALID_GTT_INT_EN (1<<16)
3307#define DPINVGTT_EN_MASK 0xff0000
3308#define CURSORB_INVALID_GTT_STATUS (1<<7)
3309#define CURSORA_INVALID_GTT_STATUS (1<<6)
3310#define SPRITED_INVALID_GTT_STATUS (1<<5)
3311#define SPRITEC_INVALID_GTT_STATUS (1<<4)
3312#define PLANEB_INVALID_GTT_STATUS (1<<3)
3313#define SPRITEB_INVALID_GTT_STATUS (1<<2)
3314#define SPRITEA_INVALID_GTT_STATUS (1<<1)
3315#define PLANEA_INVALID_GTT_STATUS (1<<0)
3316#define DPINVGTT_STATUS_MASK 0xff
3317
3318#define DSPARB 0x70030
3319#define DSPARB_CSTART_MASK (0x7f << 7)
3320#define DSPARB_CSTART_SHIFT 7
3321#define DSPARB_BSTART_MASK (0x7f)
3322#define DSPARB_BSTART_SHIFT 0
3323#define DSPARB_BEND_SHIFT 9
3324#define DSPARB_AEND_SHIFT 0
3325
3326#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
3327#define DSPFW_SR_SHIFT 23
3328#define DSPFW_SR_MASK (0x1ff<<23)
3329#define DSPFW_CURSORB_SHIFT 16
3330#define DSPFW_CURSORB_MASK (0x3f<<16)
3331#define DSPFW_PLANEB_SHIFT 8
3332#define DSPFW_PLANEB_MASK (0x7f<<8)
3333#define DSPFW_PLANEA_MASK (0x7f)
3334#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
3335#define DSPFW_CURSORA_MASK 0x00003f00
3336#define DSPFW_CURSORA_SHIFT 8
3337#define DSPFW_PLANEC_MASK (0x7f)
3338#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
3339#define DSPFW_HPLL_SR_EN (1<<31)
3340#define DSPFW_CURSOR_SR_SHIFT 24
3341#define PINEVIEW_SELF_REFRESH_EN (1<<30)
3342#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3343#define DSPFW_HPLL_CURSOR_SHIFT 16
3344#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3345#define DSPFW_HPLL_SR_MASK (0x1ff)
3346#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070)
3347#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c)
3348
3349
3350#define DRAIN_LATENCY_PRECISION_32 32
3351#define DRAIN_LATENCY_PRECISION_16 16
3352#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
3353#define DDL_CURSORA_PRECISION_32 (1<<31)
3354#define DDL_CURSORA_PRECISION_16 (0<<31)
3355#define DDL_CURSORA_SHIFT 24
3356#define DDL_PLANEA_PRECISION_32 (1<<7)
3357#define DDL_PLANEA_PRECISION_16 (0<<7)
3358#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
3359#define DDL_CURSORB_PRECISION_32 (1<<31)
3360#define DDL_CURSORB_PRECISION_16 (0<<31)
3361#define DDL_CURSORB_SHIFT 24
3362#define DDL_PLANEB_PRECISION_32 (1<<7)
3363#define DDL_PLANEB_PRECISION_16 (0<<7)
3364
3365
3366#define G4X_FIFO_LINE_SIZE 64
3367#define I915_FIFO_LINE_SIZE 64
3368#define I830_FIFO_LINE_SIZE 32
3369
3370#define VALLEYVIEW_FIFO_SIZE 255
3371#define G4X_FIFO_SIZE 127
3372#define I965_FIFO_SIZE 512
3373#define I945_FIFO_SIZE 127
3374#define I915_FIFO_SIZE 95
3375#define I855GM_FIFO_SIZE 127
3376#define I830_FIFO_SIZE 95
3377
3378#define VALLEYVIEW_MAX_WM 0xff
3379#define G4X_MAX_WM 0x3f
3380#define I915_MAX_WM 0x3f
3381
3382#define PINEVIEW_DISPLAY_FIFO 512
3383#define PINEVIEW_FIFO_LINE_SIZE 64
3384#define PINEVIEW_MAX_WM 0x1ff
3385#define PINEVIEW_DFT_WM 0x3f
3386#define PINEVIEW_DFT_HPLLOFF_WM 0
3387#define PINEVIEW_GUARD_WM 10
3388#define PINEVIEW_CURSOR_FIFO 64
3389#define PINEVIEW_CURSOR_MAX_WM 0x3f
3390#define PINEVIEW_CURSOR_DFT_WM 0
3391#define PINEVIEW_CURSOR_GUARD_WM 5
3392
3393#define VALLEYVIEW_CURSOR_MAX_WM 64
3394#define I965_CURSOR_FIFO 64
3395#define I965_CURSOR_MAX_WM 32
3396#define I965_CURSOR_DFT_WM 8
3397
3398
3399#define WM0_PIPEA_ILK 0x45100
3400#define WM0_PIPE_PLANE_MASK (0xffff<<16)
3401#define WM0_PIPE_PLANE_SHIFT 16
3402#define WM0_PIPE_SPRITE_MASK (0xff<<8)
3403#define WM0_PIPE_SPRITE_SHIFT 8
3404#define WM0_PIPE_CURSOR_MASK (0xff)
3405
3406#define WM0_PIPEB_ILK 0x45104
3407#define WM0_PIPEC_IVB 0x45200
3408#define WM1_LP_ILK 0x45108
3409#define WM1_LP_SR_EN (1<<31)
3410#define WM1_LP_LATENCY_SHIFT 24
3411#define WM1_LP_LATENCY_MASK (0x7f<<24)
3412#define WM1_LP_FBC_MASK (0xf<<20)
3413#define WM1_LP_FBC_SHIFT 20
3414#define WM1_LP_FBC_SHIFT_BDW 19
3415#define WM1_LP_SR_MASK (0x7ff<<8)
3416#define WM1_LP_SR_SHIFT 8
3417#define WM1_LP_CURSOR_MASK (0xff)
3418#define WM2_LP_ILK 0x4510c
3419#define WM2_LP_EN (1<<31)
3420#define WM3_LP_ILK 0x45110
3421#define WM3_LP_EN (1<<31)
3422#define WM1S_LP_ILK 0x45120
3423#define WM2S_LP_IVB 0x45124
3424#define WM3S_LP_IVB 0x45128
3425#define WM1S_LP_EN (1<<31)
3426
3427#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3428 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3429 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3430
3431
3432#define MLTR_ILK 0x11222
3433#define MLTR_WM1_SHIFT 0
3434#define MLTR_WM2_SHIFT 8
3435
3436#define ILK_SRLT_MASK 0x3f
3437
3438
3439
3440#define SSKPD 0x5d10
3441#define SSKPD_WM_MASK 0x3f
3442#define SSKPD_WM0_SHIFT 0
3443#define SSKPD_WM1_SHIFT 8
3444#define SSKPD_WM2_SHIFT 16
3445#define SSKPD_WM3_SHIFT 24
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462#define _PIPEAFRAMEHIGH 0x70040
3463#define PIPE_FRAME_HIGH_MASK 0x0000ffff
3464#define PIPE_FRAME_HIGH_SHIFT 0
3465#define _PIPEAFRAMEPIXEL 0x70044
3466#define PIPE_FRAME_LOW_MASK 0xff000000
3467#define PIPE_FRAME_LOW_SHIFT 24
3468#define PIPE_PIXEL_MASK 0x00ffffff
3469#define PIPE_PIXEL_SHIFT 0
3470
3471#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040)
3472#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044)
3473#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3474
3475
3476#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
3477
3478#define CURSOR_ENABLE 0x80000000
3479#define CURSOR_GAMMA_ENABLE 0x40000000
3480#define CURSOR_STRIDE_MASK 0x30000000
3481#define CURSOR_PIPE_CSC_ENABLE (1<<24)
3482#define CURSOR_FORMAT_SHIFT 24
3483#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
3484#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
3485#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
3486#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
3487#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
3488#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
3489
3490#define CURSOR_MODE 0x27
3491#define CURSOR_MODE_DISABLE 0x00
3492#define CURSOR_MODE_64_32B_AX 0x07
3493#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3494#define MCURSOR_PIPE_SELECT (1 << 28)
3495#define MCURSOR_PIPE_A 0x00
3496#define MCURSOR_PIPE_B (1 << 28)
3497#define MCURSOR_GAMMA_ENABLE (1 << 26)
3498#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
3499#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
3500#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
3501#define CURSOR_POS_MASK 0x007FF
3502#define CURSOR_POS_SIGN 0x8000
3503#define CURSOR_X_SHIFT 0
3504#define CURSOR_Y_SHIFT 16
3505#define CURSIZE 0x700a0
3506#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
3507#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
3508#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
3509
3510#define _CURBCNTR_IVB 0x71080
3511#define _CURBBASE_IVB 0x71084
3512#define _CURBPOS_IVB 0x71088
3513
3514#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3515#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3516#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3517
3518#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3519#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3520#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3521
3522
3523#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180)
3524#define DISPLAY_PLANE_ENABLE (1<<31)
3525#define DISPLAY_PLANE_DISABLE 0
3526#define DISPPLANE_GAMMA_ENABLE (1<<30)
3527#define DISPPLANE_GAMMA_DISABLE 0
3528#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3529#define DISPPLANE_YUV422 (0x0<<26)
3530#define DISPPLANE_8BPP (0x2<<26)
3531#define DISPPLANE_BGRA555 (0x3<<26)
3532#define DISPPLANE_BGRX555 (0x4<<26)
3533#define DISPPLANE_BGRX565 (0x5<<26)
3534#define DISPPLANE_BGRX888 (0x6<<26)
3535#define DISPPLANE_BGRA888 (0x7<<26)
3536#define DISPPLANE_RGBX101010 (0x8<<26)
3537#define DISPPLANE_RGBA101010 (0x9<<26)
3538#define DISPPLANE_BGRX101010 (0xa<<26)
3539#define DISPPLANE_RGBX161616 (0xc<<26)
3540#define DISPPLANE_RGBX888 (0xe<<26)
3541#define DISPPLANE_RGBA888 (0xf<<26)
3542#define DISPPLANE_STEREO_ENABLE (1<<25)
3543#define DISPPLANE_STEREO_DISABLE 0
3544#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
3545#define DISPPLANE_SEL_PIPE_SHIFT 24
3546#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3547#define DISPPLANE_SEL_PIPE_A 0
3548#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3549#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3550#define DISPPLANE_SRC_KEY_DISABLE 0
3551#define DISPPLANE_LINE_DOUBLE (1<<20)
3552#define DISPPLANE_NO_LINE_DOUBLE 0
3553#define DISPPLANE_STEREO_POLARITY_FIRST 0
3554#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3555#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14)
3556#define DISPPLANE_TILED (1<<10)
3557#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
3558#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188)
3559#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C)
3560#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190)
3561#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C)
3562#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4)
3563#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4)
3564#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC)
3565
3566#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3567#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3568#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3569#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3570#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3571#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3572#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3573#define DSPLINOFF(plane) DSPADDR(plane)
3574#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3575#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
3576
3577
3578#define DISP_BASEADDR_MASK (0xfffff000)
3579#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3580#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3581
3582
3583#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
3584#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
3585#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
3586#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
3587#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
3588#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
3589#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
3590#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
3591#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
3592#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
3593#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
3594#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
3595#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
3596
3597
3598#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
3599#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
3600#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
3601#define _PIPEBFRAMEHIGH 0x71040
3602#define _PIPEBFRAMEPIXEL 0x71044
3603#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040)
3604#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044)
3605
3606
3607
3608#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
3609#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3610#define DISPPLANE_ALPHA_TRANS_DISABLE 0
3611#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3612#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3613#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
3614#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
3615#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
3616#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
3617#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
3618#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
3619#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
3620#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
3621
3622
3623#define _DVSACNTR 0x72180
3624#define DVS_ENABLE (1<<31)
3625#define DVS_GAMMA_ENABLE (1<<30)
3626#define DVS_PIXFORMAT_MASK (3<<25)
3627#define DVS_FORMAT_YUV422 (0<<25)
3628#define DVS_FORMAT_RGBX101010 (1<<25)
3629#define DVS_FORMAT_RGBX888 (2<<25)
3630#define DVS_FORMAT_RGBX161616 (3<<25)
3631#define DVS_PIPE_CSC_ENABLE (1<<24)
3632#define DVS_SOURCE_KEY (1<<22)
3633#define DVS_RGB_ORDER_XBGR (1<<20)
3634#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3635#define DVS_YUV_ORDER_YUYV (0<<16)
3636#define DVS_YUV_ORDER_UYVY (1<<16)
3637#define DVS_YUV_ORDER_YVYU (2<<16)
3638#define DVS_YUV_ORDER_VYUY (3<<16)
3639#define DVS_DEST_KEY (1<<2)
3640#define DVS_TRICKLE_FEED_DISABLE (1<<14)
3641#define DVS_TILED (1<<10)
3642#define _DVSALINOFF 0x72184
3643#define _DVSASTRIDE 0x72188
3644#define _DVSAPOS 0x7218c
3645#define _DVSASIZE 0x72190
3646#define _DVSAKEYVAL 0x72194
3647#define _DVSAKEYMSK 0x72198
3648#define _DVSASURF 0x7219c
3649#define _DVSAKEYMAXVAL 0x721a0
3650#define _DVSATILEOFF 0x721a4
3651#define _DVSASURFLIVE 0x721ac
3652#define _DVSASCALE 0x72204
3653#define DVS_SCALE_ENABLE (1<<31)
3654#define DVS_FILTER_MASK (3<<29)
3655#define DVS_FILTER_MEDIUM (0<<29)
3656#define DVS_FILTER_ENHANCING (1<<29)
3657#define DVS_FILTER_SOFTENING (2<<29)
3658#define DVS_VERTICAL_OFFSET_HALF (1<<28)
3659#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3660#define _DVSAGAMC 0x72300
3661
3662#define _DVSBCNTR 0x73180
3663#define _DVSBLINOFF 0x73184
3664#define _DVSBSTRIDE 0x73188
3665#define _DVSBPOS 0x7318c
3666#define _DVSBSIZE 0x73190
3667#define _DVSBKEYVAL 0x73194
3668#define _DVSBKEYMSK 0x73198
3669#define _DVSBSURF 0x7319c
3670#define _DVSBKEYMAXVAL 0x731a0
3671#define _DVSBTILEOFF 0x731a4
3672#define _DVSBSURFLIVE 0x731ac
3673#define _DVSBSCALE 0x73204
3674#define _DVSBGAMC 0x73300
3675
3676#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3677#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3678#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3679#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3680#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3681#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3682#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3683#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3684#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3685#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3686#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3687#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3688
3689#define _SPRA_CTL 0x70280
3690#define SPRITE_ENABLE (1<<31)
3691#define SPRITE_GAMMA_ENABLE (1<<30)
3692#define SPRITE_PIXFORMAT_MASK (7<<25)
3693#define SPRITE_FORMAT_YUV422 (0<<25)
3694#define SPRITE_FORMAT_RGBX101010 (1<<25)
3695#define SPRITE_FORMAT_RGBX888 (2<<25)
3696#define SPRITE_FORMAT_RGBX161616 (3<<25)
3697#define SPRITE_FORMAT_YUV444 (4<<25)
3698#define SPRITE_FORMAT_XR_BGR101010 (5<<25)
3699#define SPRITE_PIPE_CSC_ENABLE (1<<24)
3700#define SPRITE_SOURCE_KEY (1<<22)
3701#define SPRITE_RGB_ORDER_RGBX (1<<20)
3702#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3703#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18)
3704#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3705#define SPRITE_YUV_ORDER_YUYV (0<<16)
3706#define SPRITE_YUV_ORDER_UYVY (1<<16)
3707#define SPRITE_YUV_ORDER_YVYU (2<<16)
3708#define SPRITE_YUV_ORDER_VYUY (3<<16)
3709#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3710#define SPRITE_INT_GAMMA_ENABLE (1<<13)
3711#define SPRITE_TILED (1<<10)
3712#define SPRITE_DEST_KEY (1<<2)
3713#define _SPRA_LINOFF 0x70284
3714#define _SPRA_STRIDE 0x70288
3715#define _SPRA_POS 0x7028c
3716#define _SPRA_SIZE 0x70290
3717#define _SPRA_KEYVAL 0x70294
3718#define _SPRA_KEYMSK 0x70298
3719#define _SPRA_SURF 0x7029c
3720#define _SPRA_KEYMAX 0x702a0
3721#define _SPRA_TILEOFF 0x702a4
3722#define _SPRA_OFFSET 0x702a4
3723#define _SPRA_SURFLIVE 0x702ac
3724#define _SPRA_SCALE 0x70304
3725#define SPRITE_SCALE_ENABLE (1<<31)
3726#define SPRITE_FILTER_MASK (3<<29)
3727#define SPRITE_FILTER_MEDIUM (0<<29)
3728#define SPRITE_FILTER_ENHANCING (1<<29)
3729#define SPRITE_FILTER_SOFTENING (2<<29)
3730#define SPRITE_VERTICAL_OFFSET_HALF (1<<28)
3731#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3732#define _SPRA_GAMC 0x70400
3733
3734#define _SPRB_CTL 0x71280
3735#define _SPRB_LINOFF 0x71284
3736#define _SPRB_STRIDE 0x71288
3737#define _SPRB_POS 0x7128c
3738#define _SPRB_SIZE 0x71290
3739#define _SPRB_KEYVAL 0x71294
3740#define _SPRB_KEYMSK 0x71298
3741#define _SPRB_SURF 0x7129c
3742#define _SPRB_KEYMAX 0x712a0
3743#define _SPRB_TILEOFF 0x712a4
3744#define _SPRB_OFFSET 0x712a4
3745#define _SPRB_SURFLIVE 0x712ac
3746#define _SPRB_SCALE 0x71304
3747#define _SPRB_GAMC 0x71400
3748
3749#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3750#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3751#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3752#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3753#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3754#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3755#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3756#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3757#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3758#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3759#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3760#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3761#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3762#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3763
3764#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3765#define SP_ENABLE (1<<31)
3766#define SP_GAMMA_ENABLE (1<<30)
3767#define SP_PIXFORMAT_MASK (0xf<<26)
3768#define SP_FORMAT_YUV422 (0<<26)
3769#define SP_FORMAT_BGR565 (5<<26)
3770#define SP_FORMAT_BGRX8888 (6<<26)
3771#define SP_FORMAT_BGRA8888 (7<<26)
3772#define SP_FORMAT_RGBX1010102 (8<<26)
3773#define SP_FORMAT_RGBA1010102 (9<<26)
3774#define SP_FORMAT_RGBX8888 (0xe<<26)
3775#define SP_FORMAT_RGBA8888 (0xf<<26)
3776#define SP_SOURCE_KEY (1<<22)
3777#define SP_YUV_BYTE_ORDER_MASK (3<<16)
3778#define SP_YUV_ORDER_YUYV (0<<16)
3779#define SP_YUV_ORDER_UYVY (1<<16)
3780#define SP_YUV_ORDER_YVYU (2<<16)
3781#define SP_YUV_ORDER_VYUY (3<<16)
3782#define SP_TILED (1<<10)
3783#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3784#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3785#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3786#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3787#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3788#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3789#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3790#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3791#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3792#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3793#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
3794
3795#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3796#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3797#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3798#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3799#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3800#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3801#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3802#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3803#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3804#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3805#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3806#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
3807
3808#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3809#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3810#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3811#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3812#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3813#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3814#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3815#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3816#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3817#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3818#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3819#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3820
3821
3822#define VGACNTRL 0x71400
3823# define VGA_DISP_DISABLE (1 << 31)
3824# define VGA_2X_MODE (1 << 30)
3825# define VGA_PIPE_B_SELECT (1 << 29)
3826
3827#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3828
3829
3830
3831#define CPU_VGACNTRL 0x41000
3832
3833#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3834#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3835#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3836#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3837#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3838#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3839#define DIGITAL_PORTA_NO_DETECT (0 << 0)
3840#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3841#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3842
3843
3844#define RR_HW_CTL 0x45300
3845#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3846#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3847
3848#define FDI_PLL_BIOS_0 0x46000
3849#define FDI_PLL_FB_CLOCK_MASK 0xff
3850#define FDI_PLL_BIOS_1 0x46004
3851#define FDI_PLL_BIOS_2 0x46008
3852#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3853#define DISPLAY_PORT_PLL_BIOS_1 0x46010
3854#define DISPLAY_PORT_PLL_BIOS_2 0x46014
3855
3856#define PCH_3DCGDIS0 0x46020
3857# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3858# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3859
3860#define PCH_3DCGDIS1 0x46024
3861# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3862
3863#define FDI_PLL_FREQ_CTL 0x46030
3864#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3865#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3866#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3867
3868
3869#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030)
3870#define PIPE_DATA_M1_OFFSET 0
3871#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034)
3872#define PIPE_DATA_N1_OFFSET 0
3873
3874#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038)
3875#define PIPE_DATA_M2_OFFSET 0
3876#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c)
3877#define PIPE_DATA_N2_OFFSET 0
3878
3879#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040)
3880#define PIPE_LINK_M1_OFFSET 0
3881#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044)
3882#define PIPE_LINK_N1_OFFSET 0
3883
3884#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048)
3885#define PIPE_LINK_M2_OFFSET 0
3886#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c)
3887#define PIPE_LINK_N2_OFFSET 0
3888
3889
3890
3891#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030)
3892#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034)
3893
3894#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038)
3895#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c)
3896
3897#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040)
3898#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044)
3899
3900#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048)
3901#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c)
3902
3903#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3904#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3905#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3906#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3907#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3908#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3909#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3910#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3911
3912
3913
3914#define _PFA_CTL_1 0x68080
3915#define _PFB_CTL_1 0x68880
3916#define PF_ENABLE (1<<31)
3917#define PF_PIPE_SEL_MASK_IVB (3<<29)
3918#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
3919#define PF_FILTER_MASK (3<<23)
3920#define PF_FILTER_PROGRAMMED (0<<23)
3921#define PF_FILTER_MED_3x3 (1<<23)
3922#define PF_FILTER_EDGE_ENHANCE (2<<23)
3923#define PF_FILTER_EDGE_SOFTEN (3<<23)
3924#define _PFA_WIN_SZ 0x68074
3925#define _PFB_WIN_SZ 0x68874
3926#define _PFA_WIN_POS 0x68070
3927#define _PFB_WIN_POS 0x68870
3928#define _PFA_VSCALE 0x68084
3929#define _PFB_VSCALE 0x68884
3930#define _PFA_HSCALE 0x68090
3931#define _PFB_HSCALE 0x68890
3932
3933#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3934#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3935#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3936#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3937#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3938
3939
3940#define _LGC_PALETTE_A 0x4a000
3941#define _LGC_PALETTE_B 0x4a800
3942#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3943
3944#define _GAMMA_MODE_A 0x4a480
3945#define _GAMMA_MODE_B 0x4ac80
3946#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3947#define GAMMA_MODE_MODE_MASK (3 << 0)
3948#define GAMMA_MODE_MODE_8BIT (0 << 0)
3949#define GAMMA_MODE_MODE_10BIT (1 << 0)
3950#define GAMMA_MODE_MODE_12BIT (2 << 0)
3951#define GAMMA_MODE_MODE_SPLIT (3 << 0)
3952
3953
3954#define DE_MASTER_IRQ_CONTROL (1 << 31)
3955#define DE_SPRITEB_FLIP_DONE (1 << 29)
3956#define DE_SPRITEA_FLIP_DONE (1 << 28)
3957#define DE_PLANEB_FLIP_DONE (1 << 27)
3958#define DE_PLANEA_FLIP_DONE (1 << 26)
3959#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
3960#define DE_PCU_EVENT (1 << 25)
3961#define DE_GTT_FAULT (1 << 24)
3962#define DE_POISON (1 << 23)
3963#define DE_PERFORM_COUNTER (1 << 22)
3964#define DE_PCH_EVENT (1 << 21)
3965#define DE_AUX_CHANNEL_A (1 << 20)
3966#define DE_DP_A_HOTPLUG (1 << 19)
3967#define DE_GSE (1 << 18)
3968#define DE_PIPEB_VBLANK (1 << 15)
3969#define DE_PIPEB_EVEN_FIELD (1 << 14)
3970#define DE_PIPEB_ODD_FIELD (1 << 13)
3971#define DE_PIPEB_LINE_COMPARE (1 << 12)
3972#define DE_PIPEB_VSYNC (1 << 11)
3973#define DE_PIPEB_CRC_DONE (1 << 10)
3974#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3975#define DE_PIPEA_VBLANK (1 << 7)
3976#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
3977#define DE_PIPEA_EVEN_FIELD (1 << 6)
3978#define DE_PIPEA_ODD_FIELD (1 << 5)
3979#define DE_PIPEA_LINE_COMPARE (1 << 4)
3980#define DE_PIPEA_VSYNC (1 << 3)
3981#define DE_PIPEA_CRC_DONE (1 << 2)
3982#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
3983#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3984#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
3985
3986
3987#define DE_ERR_INT_IVB (1<<30)
3988#define DE_GSE_IVB (1<<29)
3989#define DE_PCH_EVENT_IVB (1<<28)
3990#define DE_DP_A_HOTPLUG_IVB (1<<27)
3991#define DE_AUX_CHANNEL_A_IVB (1<<26)
3992#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
3993#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
3994#define DE_PIPEC_VBLANK_IVB (1<<10)
3995#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3996#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3997#define DE_PIPEB_VBLANK_IVB (1<<5)
3998#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3999#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
4000#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
4001#define DE_PIPEA_VBLANK_IVB (1<<0)
4002#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4003
4004#define VLV_MASTER_IER 0x4400c
4005#define MASTER_INTERRUPT_ENABLE (1<<31)
4006
4007#define DEISR 0x44000
4008#define DEIMR 0x44004
4009#define DEIIR 0x44008
4010#define DEIER 0x4400c
4011
4012#define GTISR 0x44010
4013#define GTIMR 0x44014
4014#define GTIIR 0x44018
4015#define GTIER 0x4401c
4016
4017#define GEN8_MASTER_IRQ 0x44200
4018#define GEN8_MASTER_IRQ_CONTROL (1<<31)
4019#define GEN8_PCU_IRQ (1<<30)
4020#define GEN8_DE_PCH_IRQ (1<<23)
4021#define GEN8_DE_MISC_IRQ (1<<22)
4022#define GEN8_DE_PORT_IRQ (1<<20)
4023#define GEN8_DE_PIPE_C_IRQ (1<<18)
4024#define GEN8_DE_PIPE_B_IRQ (1<<17)
4025#define GEN8_DE_PIPE_A_IRQ (1<<16)
4026#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
4027#define GEN8_GT_VECS_IRQ (1<<6)
4028#define GEN8_GT_VCS2_IRQ (1<<3)
4029#define GEN8_GT_VCS1_IRQ (1<<2)
4030#define GEN8_GT_BCS_IRQ (1<<1)
4031#define GEN8_GT_RCS_IRQ (1<<0)
4032
4033#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
4034#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
4035#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
4036#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
4037
4038#define GEN8_BCS_IRQ_SHIFT 16
4039#define GEN8_RCS_IRQ_SHIFT 0
4040#define GEN8_VCS2_IRQ_SHIFT 16
4041#define GEN8_VCS1_IRQ_SHIFT 0
4042#define GEN8_VECS_IRQ_SHIFT 0
4043
4044#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4045#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4046#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4047#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
4048#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
4049#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4050#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4051#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4052#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4053#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4054#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
4055#define GEN8_PIPE_FLIP_DONE (1 << 4)
4056#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4057#define GEN8_PIPE_VSYNC (1 << 1)
4058#define GEN8_PIPE_VBLANK (1 << 0)
4059#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4060 (GEN8_PIPE_CURSOR_FAULT | \
4061 GEN8_PIPE_SPRITE_FAULT | \
4062 GEN8_PIPE_PRIMARY_FAULT)
4063
4064#define GEN8_DE_PORT_ISR 0x44440
4065#define GEN8_DE_PORT_IMR 0x44444
4066#define GEN8_DE_PORT_IIR 0x44448
4067#define GEN8_DE_PORT_IER 0x4444c
4068#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4069#define GEN8_AUX_CHANNEL_A (1 << 0)
4070
4071#define GEN8_DE_MISC_ISR 0x44460
4072#define GEN8_DE_MISC_IMR 0x44464
4073#define GEN8_DE_MISC_IIR 0x44468
4074#define GEN8_DE_MISC_IER 0x4446c
4075#define GEN8_DE_MISC_GSE (1 << 27)
4076
4077#define GEN8_PCU_ISR 0x444e0
4078#define GEN8_PCU_IMR 0x444e4
4079#define GEN8_PCU_IIR 0x444e8
4080#define GEN8_PCU_IER 0x444ec
4081
4082#define ILK_DISPLAY_CHICKEN2 0x42004
4083
4084#define ILK_ELPIN_409_SELECT (1 << 25)
4085#define ILK_DPARB_GATE (1<<22)
4086#define ILK_VSDPFD_FULL (1<<21)
4087#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
4088#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
4089#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
4090#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
4091#define ILK_HDCP_DISABLE (1<<25)
4092#define ILK_eDP_A_DISABLE (1<<24)
4093#define ILK_DESKTOP (1<<23)
4094
4095#define ILK_DSPCLK_GATE_D 0x42020
4096#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4097#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4098#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4099#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4100#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
4101
4102#define IVB_CHICKEN3 0x4200c
4103# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4104# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4105
4106#define CHICKEN_PAR1_1 0x42080
4107#define DPA_MASK_VBLANK_SRD (1 << 15)
4108#define FORCE_ARB_IDLE_PLANES (1 << 14)
4109
4110#define _CHICKEN_PIPESL_1_A 0x420b0
4111#define _CHICKEN_PIPESL_1_B 0x420b4
4112#define DPRS_MASK_VBLANK_SRD (1 << 0)
4113#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4114
4115#define DISP_ARB_CTL 0x45000
4116#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
4117#define DISP_FBC_WM_DIS (1<<15)
4118#define DISP_ARB_CTL2 0x45004
4119#define DISP_DATA_PARTITION_5_6 (1<<6)
4120#define GEN7_MSG_CTL 0x45010
4121#define WAIT_FOR_PCH_RESET_ACK (1<<1)
4122#define WAIT_FOR_PCH_FLR_ACK (1<<0)
4123
4124
4125#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4126# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
4127#define COMMON_SLICE_CHICKEN2 0x7014
4128# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
4129
4130#define GEN7_L3CNTLREG1 0xB01C
4131#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
4132#define GEN7_L3AGDIS (1<<19)
4133
4134#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4135#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4136
4137#define GEN7_L3SQCREG4 0xb034
4138#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4139
4140
4141#define HDC_CHICKEN0 0x7300
4142#define HDC_FORCE_NON_COHERENT (1<<4)
4143
4144
4145#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4146#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4147
4148#define HSW_SCRATCH1 0xb038
4149#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4150
4151#define HSW_FUSE_STRAP 0x42014
4152#define HSW_CDCLK_LIMIT (1 << 24)
4153
4154
4155
4156
4157#define SDE_AUDIO_POWER_D (1 << 27)
4158#define SDE_AUDIO_POWER_C (1 << 26)
4159#define SDE_AUDIO_POWER_B (1 << 25)
4160#define SDE_AUDIO_POWER_SHIFT (25)
4161#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4162#define SDE_GMBUS (1 << 24)
4163#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4164#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4165#define SDE_AUDIO_HDCP_MASK (3 << 22)
4166#define SDE_AUDIO_TRANSB (1 << 21)
4167#define SDE_AUDIO_TRANSA (1 << 20)
4168#define SDE_AUDIO_TRANS_MASK (3 << 20)
4169#define SDE_POISON (1 << 19)
4170
4171#define SDE_FDI_RXB (1 << 17)
4172#define SDE_FDI_RXA (1 << 16)
4173#define SDE_FDI_MASK (3 << 16)
4174#define SDE_AUXD (1 << 15)
4175#define SDE_AUXC (1 << 14)
4176#define SDE_AUXB (1 << 13)
4177#define SDE_AUX_MASK (7 << 13)
4178
4179#define SDE_CRT_HOTPLUG (1 << 11)
4180#define SDE_PORTD_HOTPLUG (1 << 10)
4181#define SDE_PORTC_HOTPLUG (1 << 9)
4182#define SDE_PORTB_HOTPLUG (1 << 8)
4183#define SDE_SDVOB_HOTPLUG (1 << 6)
4184#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4185 SDE_SDVOB_HOTPLUG | \
4186 SDE_PORTB_HOTPLUG | \
4187 SDE_PORTC_HOTPLUG | \
4188 SDE_PORTD_HOTPLUG)
4189#define SDE_TRANSB_CRC_DONE (1 << 5)
4190#define SDE_TRANSB_CRC_ERR (1 << 4)
4191#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4192#define SDE_TRANSA_CRC_DONE (1 << 2)
4193#define SDE_TRANSA_CRC_ERR (1 << 1)
4194#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4195#define SDE_TRANS_MASK (0x3f)
4196
4197
4198#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4199#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4200#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4201#define SDE_AUDIO_POWER_SHIFT_CPT 29
4202#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4203#define SDE_AUXD_CPT (1 << 27)
4204#define SDE_AUXC_CPT (1 << 26)
4205#define SDE_AUXB_CPT (1 << 25)
4206#define SDE_AUX_MASK_CPT (7 << 25)
4207#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4208#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4209#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
4210#define SDE_CRT_HOTPLUG_CPT (1 << 19)
4211#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
4212#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
4213 SDE_SDVOB_HOTPLUG_CPT | \
4214 SDE_PORTD_HOTPLUG_CPT | \
4215 SDE_PORTC_HOTPLUG_CPT | \
4216 SDE_PORTB_HOTPLUG_CPT)
4217#define SDE_GMBUS_CPT (1 << 17)
4218#define SDE_ERROR_CPT (1 << 16)
4219#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4220#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4221#define SDE_FDI_RXC_CPT (1 << 8)
4222#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4223#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4224#define SDE_FDI_RXB_CPT (1 << 4)
4225#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4226#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4227#define SDE_FDI_RXA_CPT (1 << 0)
4228#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4229 SDE_AUDIO_CP_REQ_B_CPT | \
4230 SDE_AUDIO_CP_REQ_A_CPT)
4231#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4232 SDE_AUDIO_CP_CHG_B_CPT | \
4233 SDE_AUDIO_CP_CHG_A_CPT)
4234#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4235 SDE_FDI_RXB_CPT | \
4236 SDE_FDI_RXA_CPT)
4237
4238#define SDEISR 0xc4000
4239#define SDEIMR 0xc4004
4240#define SDEIIR 0xc4008
4241#define SDEIER 0xc400c
4242
4243#define SERR_INT 0xc4040
4244#define SERR_INT_POISON (1<<31)
4245#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4246#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4247#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
4248#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
4249
4250
4251#define PCH_PORT_HOTPLUG 0xc4030
4252#define PORTD_HOTPLUG_ENABLE (1 << 20)
4253#define PORTD_PULSE_DURATION_2ms (0)
4254#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4255#define PORTD_PULSE_DURATION_6ms (2 << 18)
4256#define PORTD_PULSE_DURATION_100ms (3 << 18)
4257#define PORTD_PULSE_DURATION_MASK (3 << 18)
4258#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4259#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4260#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4261#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
4262#define PORTC_HOTPLUG_ENABLE (1 << 12)
4263#define PORTC_PULSE_DURATION_2ms (0)
4264#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4265#define PORTC_PULSE_DURATION_6ms (2 << 10)
4266#define PORTC_PULSE_DURATION_100ms (3 << 10)
4267#define PORTC_PULSE_DURATION_MASK (3 << 10)
4268#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4269#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4270#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4271#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
4272#define PORTB_HOTPLUG_ENABLE (1 << 4)
4273#define PORTB_PULSE_DURATION_2ms (0)
4274#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4275#define PORTB_PULSE_DURATION_6ms (2 << 2)
4276#define PORTB_PULSE_DURATION_100ms (3 << 2)
4277#define PORTB_PULSE_DURATION_MASK (3 << 2)
4278#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4279#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4280#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4281#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
4282
4283#define PCH_GPIOA 0xc5010
4284#define PCH_GPIOB 0xc5014
4285#define PCH_GPIOC 0xc5018
4286#define PCH_GPIOD 0xc501c
4287#define PCH_GPIOE 0xc5020
4288#define PCH_GPIOF 0xc5024
4289
4290#define PCH_GMBUS0 0xc5100
4291#define PCH_GMBUS1 0xc5104
4292#define PCH_GMBUS2 0xc5108
4293#define PCH_GMBUS3 0xc510c
4294#define PCH_GMBUS4 0xc5110
4295#define PCH_GMBUS5 0xc5120
4296
4297#define _PCH_DPLL_A 0xc6014
4298#define _PCH_DPLL_B 0xc6018
4299#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4300
4301#define _PCH_FPA0 0xc6040
4302#define FP_CB_TUNE (0x3<<22)
4303#define _PCH_FPA1 0xc6044
4304#define _PCH_FPB0 0xc6048
4305#define _PCH_FPB1 0xc604c
4306#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4307#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
4308
4309#define PCH_DPLL_TEST 0xc606c
4310
4311#define PCH_DREF_CONTROL 0xC6200
4312#define DREF_CONTROL_MASK 0x7fc3
4313#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4314#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4315#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4316#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4317#define DREF_SSC_SOURCE_DISABLE (0<<11)
4318#define DREF_SSC_SOURCE_ENABLE (2<<11)
4319#define DREF_SSC_SOURCE_MASK (3<<11)
4320#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4321#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4322#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
4323#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
4324#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4325#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
4326#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
4327#define DREF_SSC4_DOWNSPREAD (0<<6)
4328#define DREF_SSC4_CENTERSPREAD (1<<6)
4329#define DREF_SSC1_DISABLE (0<<1)
4330#define DREF_SSC1_ENABLE (1<<1)
4331#define DREF_SSC4_DISABLE (0)
4332#define DREF_SSC4_ENABLE (1)
4333
4334#define PCH_RAWCLK_FREQ 0xc6204
4335#define FDL_TP1_TIMER_SHIFT 12
4336#define FDL_TP1_TIMER_MASK (3<<12)
4337#define FDL_TP2_TIMER_SHIFT 10
4338#define FDL_TP2_TIMER_MASK (3<<10)
4339#define RAWCLK_FREQ_MASK 0x3ff
4340
4341#define PCH_DPLL_TMR_CFG 0xc6208
4342
4343#define PCH_SSC4_PARMS 0xc6210
4344#define PCH_SSC4_AUX_PARMS 0xc6214
4345
4346#define PCH_DPLL_SEL 0xc7000
4347#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4348#define TRANS_DPLLA_SEL(pipe) 0
4349#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
4350
4351
4352
4353#define _PCH_TRANS_HTOTAL_A 0xe0000
4354#define TRANS_HTOTAL_SHIFT 16
4355#define TRANS_HACTIVE_SHIFT 0
4356#define _PCH_TRANS_HBLANK_A 0xe0004
4357#define TRANS_HBLANK_END_SHIFT 16
4358#define TRANS_HBLANK_START_SHIFT 0
4359#define _PCH_TRANS_HSYNC_A 0xe0008
4360#define TRANS_HSYNC_END_SHIFT 16
4361#define TRANS_HSYNC_START_SHIFT 0
4362#define _PCH_TRANS_VTOTAL_A 0xe000c
4363#define TRANS_VTOTAL_SHIFT 16
4364#define TRANS_VACTIVE_SHIFT 0
4365#define _PCH_TRANS_VBLANK_A 0xe0010
4366#define TRANS_VBLANK_END_SHIFT 16
4367#define TRANS_VBLANK_START_SHIFT 0
4368#define _PCH_TRANS_VSYNC_A 0xe0014
4369#define TRANS_VSYNC_END_SHIFT 16
4370#define TRANS_VSYNC_START_SHIFT 0
4371#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
4372
4373#define _PCH_TRANSA_DATA_M1 0xe0030
4374#define _PCH_TRANSA_DATA_N1 0xe0034
4375#define _PCH_TRANSA_DATA_M2 0xe0038
4376#define _PCH_TRANSA_DATA_N2 0xe003c
4377#define _PCH_TRANSA_LINK_M1 0xe0040
4378#define _PCH_TRANSA_LINK_N1 0xe0044
4379#define _PCH_TRANSA_LINK_M2 0xe0048
4380#define _PCH_TRANSA_LINK_N2 0xe004c
4381
4382
4383
4384#define _VIDEO_DIP_CTL_A 0xe0200
4385#define _VIDEO_DIP_DATA_A 0xe0208
4386#define _VIDEO_DIP_GCP_A 0xe0210
4387
4388#define _VIDEO_DIP_CTL_B 0xe1200
4389#define _VIDEO_DIP_DATA_B 0xe1208
4390#define _VIDEO_DIP_GCP_B 0xe1210
4391
4392#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4393#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4394#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4395
4396#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4397#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4398#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
4399
4400#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4401#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4402#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
4403
4404#define VLV_TVIDEO_DIP_CTL(pipe) \
4405 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4406#define VLV_TVIDEO_DIP_DATA(pipe) \
4407 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4408#define VLV_TVIDEO_DIP_GCP(pipe) \
4409 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4410
4411
4412#define HSW_VIDEO_DIP_CTL_A 0x60200
4413#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4414#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4415#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4416#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4417#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4418#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4419#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4420#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4421#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4422#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4423#define HSW_VIDEO_DIP_GCP_A 0x60210
4424
4425#define HSW_VIDEO_DIP_CTL_B 0x61200
4426#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4427#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4428#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4429#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4430#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4431#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4432#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4433#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4434#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4435#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4436#define HSW_VIDEO_DIP_GCP_B 0x61210
4437
4438#define HSW_TVIDEO_DIP_CTL(trans) \
4439 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
4440#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4441 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
4442#define HSW_TVIDEO_DIP_VS_DATA(trans) \
4443 _TRANSCODER(trans, HSW_VIDEO_DIP_VS_DATA_A, HSW_VIDEO_DIP_VS_DATA_B)
4444#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4445 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
4446#define HSW_TVIDEO_DIP_GCP(trans) \
4447 _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
4448#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4449 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
4450
4451#define HSW_STEREO_3D_CTL_A 0x70020
4452#define S3D_ENABLE (1<<31)
4453#define HSW_STEREO_3D_CTL_B 0x71020
4454
4455#define HSW_STEREO_3D_CTL(trans) \
4456 _TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A)
4457
4458#define _PCH_TRANS_HTOTAL_B 0xe1000
4459#define _PCH_TRANS_HBLANK_B 0xe1004
4460#define _PCH_TRANS_HSYNC_B 0xe1008
4461#define _PCH_TRANS_VTOTAL_B 0xe100c
4462#define _PCH_TRANS_VBLANK_B 0xe1010
4463#define _PCH_TRANS_VSYNC_B 0xe1014
4464#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
4465
4466#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4467#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4468#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4469#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4470#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4471#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4472#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4473 _PCH_TRANS_VSYNCSHIFT_B)
4474
4475#define _PCH_TRANSB_DATA_M1 0xe1030
4476#define _PCH_TRANSB_DATA_N1 0xe1034
4477#define _PCH_TRANSB_DATA_M2 0xe1038
4478#define _PCH_TRANSB_DATA_N2 0xe103c
4479#define _PCH_TRANSB_LINK_M1 0xe1040
4480#define _PCH_TRANSB_LINK_N1 0xe1044
4481#define _PCH_TRANSB_LINK_M2 0xe1048
4482#define _PCH_TRANSB_LINK_N2 0xe104c
4483
4484#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4485#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4486#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4487#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4488#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4489#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4490#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4491#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4492
4493#define _PCH_TRANSACONF 0xf0008
4494#define _PCH_TRANSBCONF 0xf1008
4495#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4496#define LPT_TRANSCONF _PCH_TRANSACONF
4497#define TRANS_DISABLE (0<<31)
4498#define TRANS_ENABLE (1<<31)
4499#define TRANS_STATE_MASK (1<<30)
4500#define TRANS_STATE_DISABLE (0<<30)
4501#define TRANS_STATE_ENABLE (1<<30)
4502#define TRANS_FSYNC_DELAY_HB1 (0<<27)
4503#define TRANS_FSYNC_DELAY_HB2 (1<<27)
4504#define TRANS_FSYNC_DELAY_HB3 (2<<27)
4505#define TRANS_FSYNC_DELAY_HB4 (3<<27)
4506#define TRANS_INTERLACE_MASK (7<<21)
4507#define TRANS_PROGRESSIVE (0<<21)
4508#define TRANS_INTERLACED (3<<21)
4509#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
4510#define TRANS_8BPC (0<<5)
4511#define TRANS_10BPC (1<<5)
4512#define TRANS_6BPC (2<<5)
4513#define TRANS_12BPC (3<<5)
4514
4515#define _TRANSA_CHICKEN1 0xf0060
4516#define _TRANSB_CHICKEN1 0xf1060
4517#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4518#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
4519#define _TRANSA_CHICKEN2 0xf0064
4520#define _TRANSB_CHICKEN2 0xf1064
4521#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
4522#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
4523#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
4524#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
4525#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
4526#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
4527
4528#define SOUTH_CHICKEN1 0xc2000
4529#define FDIA_PHASE_SYNC_SHIFT_OVR 19
4530#define FDIA_PHASE_SYNC_SHIFT_EN 18
4531#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4532#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4533#define FDI_BC_BIFURCATION_SELECT (1 << 12)
4534#define SOUTH_CHICKEN2 0xc2004
4535#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
4536#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
4537#define DPLS_EDP_PPS_FIX_DIS (1<<0)
4538
4539#define _FDI_RXA_CHICKEN 0xc200c
4540#define _FDI_RXB_CHICKEN 0xc2010
4541#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
4542#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
4543#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4544
4545#define SOUTH_DSPCLK_GATE_D 0xc2020
4546#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
4547#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4548#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
4549#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
4550
4551
4552#define _FDI_TXA_CTL 0x60100
4553#define _FDI_TXB_CTL 0x61100
4554#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
4555#define FDI_TX_DISABLE (0<<31)
4556#define FDI_TX_ENABLE (1<<31)
4557#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
4558#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
4559#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
4560#define FDI_LINK_TRAIN_NONE (3<<28)
4561#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
4562#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
4563#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
4564#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
4565#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4566#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4567#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
4568#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
4569
4570
4571
4572#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4573#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4574#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4575#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4576
4577#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
4578#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
4579#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
4580#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
4581#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
4582#define FDI_DP_PORT_WIDTH_SHIFT 19
4583#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
4584#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
4585#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
4586
4587#define FDI_TX_PLL_ENABLE (1<<14)
4588
4589
4590#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
4591#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
4592#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
4593#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
4594
4595
4596#define FDI_COMPOSITE_SYNC (1<<11)
4597#define FDI_LINK_TRAIN_AUTO (1<<10)
4598#define FDI_SCRAMBLING_ENABLE (0<<7)
4599#define FDI_SCRAMBLING_DISABLE (1<<7)
4600
4601
4602#define _FDI_RXA_CTL 0xf000c
4603#define _FDI_RXB_CTL 0xf100c
4604#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4605#define FDI_RX_ENABLE (1<<31)
4606
4607#define FDI_FS_ERRC_ENABLE (1<<27)
4608#define FDI_FE_ERRC_ENABLE (1<<26)
4609#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
4610#define FDI_8BPC (0<<16)
4611#define FDI_10BPC (1<<16)
4612#define FDI_6BPC (2<<16)
4613#define FDI_12BPC (3<<16)
4614#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
4615#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
4616#define FDI_RX_PLL_ENABLE (1<<13)
4617#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
4618#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
4619#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
4620#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
4621#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
4622#define FDI_PCDCLK (1<<4)
4623
4624#define FDI_AUTO_TRAINING (1<<10)
4625#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
4626#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
4627#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
4628#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
4629#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
4630
4631#define _FDI_RXA_MISC 0xf0010
4632#define _FDI_RXB_MISC 0xf1010
4633#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
4634#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
4635#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
4636#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
4637#define FDI_RX_TP1_TO_TP2_48 (2<<20)
4638#define FDI_RX_TP1_TO_TP2_64 (3<<20)
4639#define FDI_RX_FDI_DELAY_90 (0x90<<0)
4640#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4641
4642#define _FDI_RXA_TUSIZE1 0xf0030
4643#define _FDI_RXA_TUSIZE2 0xf0038
4644#define _FDI_RXB_TUSIZE1 0xf1030
4645#define _FDI_RXB_TUSIZE2 0xf1038
4646#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4647#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4648
4649
4650#define FDI_RX_INTER_LANE_ALIGN (1<<10)
4651#define FDI_RX_SYMBOL_LOCK (1<<9)
4652#define FDI_RX_BIT_LOCK (1<<8)
4653#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
4654#define FDI_RX_FS_CODE_ERR (1<<6)
4655#define FDI_RX_FE_CODE_ERR (1<<5)
4656#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
4657#define FDI_RX_HDCP_LINK_FAIL (1<<3)
4658#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
4659#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
4660#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
4661
4662#define _FDI_RXA_IIR 0xf0014
4663#define _FDI_RXA_IMR 0xf0018
4664#define _FDI_RXB_IIR 0xf1014
4665#define _FDI_RXB_IMR 0xf1018
4666#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4667#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4668
4669#define FDI_PLL_CTL_1 0xfe000
4670#define FDI_PLL_CTL_2 0xfe004
4671
4672#define PCH_LVDS 0xe1180
4673#define LVDS_DETECTED (1 << 1)
4674
4675
4676#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4677#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4678#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
4679#define PANEL_PORT_SELECT_DPB_VLV (1 << 30)
4680#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
4681#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4682#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4683
4684#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4685#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4686#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4687#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4688#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
4689
4690#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4691#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4692#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4693 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4694#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4695 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4696#define VLV_PIPE_PP_DIVISOR(pipe) \
4697 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4698
4699#define PCH_PP_STATUS 0xc7200
4700#define PCH_PP_CONTROL 0xc7204
4701#define PANEL_UNLOCK_REGS (0xabcd << 16)
4702#define PANEL_UNLOCK_MASK (0xffff << 16)
4703#define EDP_FORCE_VDD (1 << 3)
4704#define EDP_BLC_ENABLE (1 << 2)
4705#define PANEL_POWER_RESET (1 << 1)
4706#define PANEL_POWER_OFF (0 << 0)
4707#define PANEL_POWER_ON (1 << 0)
4708#define PCH_PP_ON_DELAYS 0xc7208
4709#define PANEL_PORT_SELECT_MASK (3 << 30)
4710#define PANEL_PORT_SELECT_LVDS (0 << 30)
4711#define PANEL_PORT_SELECT_DPA (1 << 30)
4712#define PANEL_PORT_SELECT_DPC (2 << 30)
4713#define PANEL_PORT_SELECT_DPD (3 << 30)
4714#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4715#define PANEL_POWER_UP_DELAY_SHIFT 16
4716#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4717#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4718
4719#define PCH_PP_OFF_DELAYS 0xc720c
4720#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4721#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4722#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4723#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4724
4725#define PCH_PP_DIVISOR 0xc7210
4726#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4727#define PP_REFERENCE_DIVIDER_SHIFT 8
4728#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4729#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4730
4731#define PCH_DP_B 0xe4100
4732#define PCH_DPB_AUX_CH_CTL 0xe4110
4733#define PCH_DPB_AUX_CH_DATA1 0xe4114
4734#define PCH_DPB_AUX_CH_DATA2 0xe4118
4735#define PCH_DPB_AUX_CH_DATA3 0xe411c
4736#define PCH_DPB_AUX_CH_DATA4 0xe4120
4737#define PCH_DPB_AUX_CH_DATA5 0xe4124
4738
4739#define PCH_DP_C 0xe4200
4740#define PCH_DPC_AUX_CH_CTL 0xe4210
4741#define PCH_DPC_AUX_CH_DATA1 0xe4214
4742#define PCH_DPC_AUX_CH_DATA2 0xe4218
4743#define PCH_DPC_AUX_CH_DATA3 0xe421c
4744#define PCH_DPC_AUX_CH_DATA4 0xe4220
4745#define PCH_DPC_AUX_CH_DATA5 0xe4224
4746
4747#define PCH_DP_D 0xe4300
4748#define PCH_DPD_AUX_CH_CTL 0xe4310
4749#define PCH_DPD_AUX_CH_DATA1 0xe4314
4750#define PCH_DPD_AUX_CH_DATA2 0xe4318
4751#define PCH_DPD_AUX_CH_DATA3 0xe431c
4752#define PCH_DPD_AUX_CH_DATA4 0xe4320
4753#define PCH_DPD_AUX_CH_DATA5 0xe4324
4754
4755
4756#define PORT_TRANS_A_SEL_CPT 0
4757#define PORT_TRANS_B_SEL_CPT (1<<29)
4758#define PORT_TRANS_C_SEL_CPT (2<<29)
4759#define PORT_TRANS_SEL_MASK (3<<29)
4760#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4761#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4762#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4763
4764#define TRANS_DP_CTL_A 0xe0300
4765#define TRANS_DP_CTL_B 0xe1300
4766#define TRANS_DP_CTL_C 0xe2300
4767#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4768#define TRANS_DP_OUTPUT_ENABLE (1<<31)
4769#define TRANS_DP_PORT_SEL_B (0<<29)
4770#define TRANS_DP_PORT_SEL_C (1<<29)
4771#define TRANS_DP_PORT_SEL_D (2<<29)
4772#define TRANS_DP_PORT_SEL_NONE (3<<29)
4773#define TRANS_DP_PORT_SEL_MASK (3<<29)
4774#define TRANS_DP_AUDIO_ONLY (1<<26)
4775#define TRANS_DP_ENH_FRAMING (1<<18)
4776#define TRANS_DP_8BPC (0<<9)
4777#define TRANS_DP_10BPC (1<<9)
4778#define TRANS_DP_6BPC (2<<9)
4779#define TRANS_DP_12BPC (3<<9)
4780#define TRANS_DP_BPC_MASK (3<<9)
4781#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4782#define TRANS_DP_VSYNC_ACTIVE_LOW 0
4783#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4784#define TRANS_DP_HSYNC_ACTIVE_LOW 0
4785#define TRANS_DP_SYNC_MASK (3<<3)
4786
4787
4788
4789#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4790#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4791#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4792#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4793
4794#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4795#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4796#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4797#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4798#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4799#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4800
4801
4802#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4803#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4804#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4805#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4806#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4807#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4808#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
4809
4810
4811#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4812#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4813#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4814#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4815#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4816
4817#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4818
4819#define FORCEWAKE 0xA18C
4820#define FORCEWAKE_VLV 0x1300b0
4821#define FORCEWAKE_ACK_VLV 0x1300b4
4822#define FORCEWAKE_MEDIA_VLV 0x1300b8
4823#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
4824#define FORCEWAKE_ACK_HSW 0x130044
4825#define FORCEWAKE_ACK 0x130090
4826#define VLV_GTLC_WAKE_CTRL 0x130090
4827#define VLV_GTLC_PW_STATUS 0x130094
4828#define VLV_GTLC_PW_RENDER_STATUS_MASK 0x80
4829#define VLV_GTLC_PW_MEDIA_STATUS_MASK 0x20
4830#define FORCEWAKE_MT 0xa188
4831#define FORCEWAKE_KERNEL 0x1
4832#define FORCEWAKE_USER 0x2
4833#define FORCEWAKE_MT_ACK 0x130040
4834#define ECOBUS 0xa180
4835#define FORCEWAKE_MT_ENABLE (1<<5)
4836
4837#define GTFIFODBG 0x120000
4838#define GT_FIFO_SBDROPERR (1<<6)
4839#define GT_FIFO_BLOBDROPERR (1<<5)
4840#define GT_FIFO_SB_READ_ABORTERR (1<<4)
4841#define GT_FIFO_DROPERR (1<<3)
4842#define GT_FIFO_OVFERR (1<<2)
4843#define GT_FIFO_IAWRERR (1<<1)
4844#define GT_FIFO_IARDERR (1<<0)
4845
4846#define GTFIFOCTL 0x120008
4847#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
4848#define GT_FIFO_NUM_RESERVED_ENTRIES 20
4849
4850#define HSW_IDICR 0x9008
4851#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
4852#define HSW_EDRAM_PRESENT 0x120010
4853
4854#define GEN6_UCGCTL1 0x9400
4855# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4856# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4857
4858#define GEN6_UCGCTL2 0x9404
4859# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4860# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4861# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4862# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4863# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4864
4865#define GEN7_UCGCTL4 0x940c
4866#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4867
4868#define GEN6_RPNSWREQ 0xA008
4869#define GEN6_TURBO_DISABLE (1<<31)
4870#define GEN6_FREQUENCY(x) ((x)<<25)
4871#define HSW_FREQUENCY(x) ((x)<<24)
4872#define GEN6_OFFSET(x) ((x)<<19)
4873#define GEN6_AGGRESSIVE_TURBO (0<<15)
4874#define GEN6_RC_VIDEO_FREQ 0xA00C
4875#define GEN6_RC_CONTROL 0xA090
4876#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4877#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4878#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4879#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4880#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4881#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
4882#define GEN7_RC_CTL_TO_MODE (1<<28)
4883#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4884#define GEN6_RC_CTL_HW_ENABLE (1<<31)
4885#define GEN6_RP_DOWN_TIMEOUT 0xA010
4886#define GEN6_RP_INTERRUPT_LIMITS 0xA014
4887#define GEN6_RPSTAT1 0xA01C
4888#define GEN6_CAGF_SHIFT 8
4889#define HSW_CAGF_SHIFT 7
4890#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4891#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
4892#define GEN6_RP_CONTROL 0xA024
4893#define GEN6_RP_MEDIA_TURBO (1<<11)
4894#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4895#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4896#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4897#define GEN6_RP_MEDIA_HW_MODE (1<<9)
4898#define GEN6_RP_MEDIA_SW_MODE (0<<9)
4899#define GEN6_RP_MEDIA_IS_GFX (1<<8)
4900#define GEN6_RP_ENABLE (1<<7)
4901#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4902#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4903#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4904#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
4905#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4906#define GEN6_RP_UP_THRESHOLD 0xA02C
4907#define GEN6_RP_DOWN_THRESHOLD 0xA030
4908#define GEN6_RP_CUR_UP_EI 0xA050
4909#define GEN6_CURICONT_MASK 0xffffff
4910#define GEN6_RP_CUR_UP 0xA054
4911#define GEN6_CURBSYTAVG_MASK 0xffffff
4912#define GEN6_RP_PREV_UP 0xA058
4913#define GEN6_RP_CUR_DOWN_EI 0xA05C
4914#define GEN6_CURIAVG_MASK 0xffffff
4915#define GEN6_RP_CUR_DOWN 0xA060
4916#define GEN6_RP_PREV_DOWN 0xA064
4917#define GEN6_RP_UP_EI 0xA068
4918#define GEN6_RP_DOWN_EI 0xA06C
4919#define GEN6_RP_IDLE_HYSTERSIS 0xA070
4920#define GEN6_RC_STATE 0xA094
4921#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4922#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4923#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4924#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4925#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4926#define GEN6_RC_SLEEP 0xA0B0
4927#define GEN6_RC1e_THRESHOLD 0xA0B4
4928#define GEN6_RC6_THRESHOLD 0xA0B8
4929#define GEN6_RC6p_THRESHOLD 0xA0BC
4930#define GEN6_RC6pp_THRESHOLD 0xA0C0
4931#define GEN6_PMINTRMSK 0xA168
4932
4933#define GEN6_PMISR 0x44020
4934#define GEN6_PMIMR 0x44024
4935#define GEN6_PMIIR 0x44028
4936#define GEN6_PMIER 0x4402C
4937#define GEN6_PM_MBOX_EVENT (1<<25)
4938#define GEN6_PM_THERMAL_EVENT (1<<24)
4939#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4940#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4941#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4942#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4943#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
4944#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
4945 GEN6_PM_RP_DOWN_THRESHOLD | \
4946 GEN6_PM_RP_DOWN_TIMEOUT)
4947
4948#define GEN6_GT_GFX_RC6_LOCKED 0x138104
4949#define VLV_COUNTER_CONTROL 0x138104
4950#define VLV_COUNT_RANGE_HIGH (1<<15)
4951#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
4952#define VLV_RENDER_RC6_COUNT_EN (1<<0)
4953#define GEN6_GT_GFX_RC6 0x138108
4954#define GEN6_GT_GFX_RC6p 0x13810C
4955#define GEN6_GT_GFX_RC6pp 0x138110
4956
4957#define GEN6_PCODE_MAILBOX 0x138124
4958#define GEN6_PCODE_READY (1<<31)
4959#define GEN6_READ_OC_PARAMS 0xc
4960#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4961#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
4962#define GEN6_PCODE_WRITE_RC6VIDS 0x4
4963#define GEN6_PCODE_READ_RC6VIDS 0x5
4964#define GEN6_PCODE_READ_D_COMP 0x10
4965#define GEN6_PCODE_WRITE_D_COMP 0x11
4966#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
4967#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
4968#define DISPLAY_IPS_CONTROL 0x19
4969#define GEN6_PCODE_DATA 0x138128
4970#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
4971#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
4972
4973#define GEN6_GT_CORE_STATUS 0x138060
4974#define GEN6_CORE_CPD_STATE_MASK (7<<4)
4975#define GEN6_RCn_MASK 7
4976#define GEN6_RC0 0
4977#define GEN6_RC3 2
4978#define GEN6_RC6 3
4979#define GEN6_RC7 4
4980
4981#define GEN7_MISCCPCTL (0x9424)
4982#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
4983
4984
4985#define GEN7_L3CDERRST1 0xB008
4986#define HSW_L3CDERRST11 0xB208
4987#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
4988#define GEN7_PARITY_ERROR_VALID (1<<13)
4989#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
4990#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
4991#define GEN7_PARITY_ERROR_ROW(reg) \
4992 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4993#define GEN7_PARITY_ERROR_BANK(reg) \
4994 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4995#define GEN7_PARITY_ERROR_SUBBANK(reg) \
4996 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4997#define GEN7_L3CDERRST1_ENABLE (1<<7)
4998
4999#define GEN7_L3LOG_BASE 0xB070
5000#define HSW_L3LOG_BASE_SLICE1 0xB270
5001#define GEN7_L3LOG_SIZE 0x80
5002
5003#define GEN7_HALF_SLICE_CHICKEN1 0xe100
5004#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
5005#define GEN7_MAX_PS_THREAD_DEP (8<<12)
5006#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
5007#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
5008
5009#define GEN7_ROW_CHICKEN2 0xe4f4
5010#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
5011#define DOP_CLOCK_GATING_DISABLE (1<<0)
5012
5013#define HSW_ROW_CHICKEN3 0xe49c
5014#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
5015
5016#define HALF_SLICE_CHICKEN3 0xe184
5017#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
5018#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
5019
5020#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
5021#define INTEL_AUDIO_DEVCL 0x808629FB
5022#define INTEL_AUDIO_DEVBLC 0x80862801
5023#define INTEL_AUDIO_DEVCTG 0x80862802
5024
5025#define G4X_AUD_CNTL_ST 0x620B4
5026#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
5027#define G4X_ELDV_DEVCTG (1 << 14)
5028#define G4X_ELD_ADDR (0xf << 5)
5029#define G4X_ELD_ACK (1 << 4)
5030#define G4X_HDMIW_HDMIEDID 0x6210C
5031
5032#define IBX_HDMIW_HDMIEDID_A 0xE2050
5033#define IBX_HDMIW_HDMIEDID_B 0xE2150
5034#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5035 IBX_HDMIW_HDMIEDID_A, \
5036 IBX_HDMIW_HDMIEDID_B)
5037#define IBX_AUD_CNTL_ST_A 0xE20B4
5038#define IBX_AUD_CNTL_ST_B 0xE21B4
5039#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5040 IBX_AUD_CNTL_ST_A, \
5041 IBX_AUD_CNTL_ST_B)
5042#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
5043#define IBX_ELD_ADDRESS (0x1f << 5)
5044#define IBX_ELD_ACK (1 << 4)
5045#define IBX_AUD_CNTL_ST2 0xE20C0
5046#define IBX_ELD_VALIDB (1 << 0)
5047#define IBX_CP_READYB (1 << 1)
5048
5049#define CPT_HDMIW_HDMIEDID_A 0xE5050
5050#define CPT_HDMIW_HDMIEDID_B 0xE5150
5051#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5052 CPT_HDMIW_HDMIEDID_A, \
5053 CPT_HDMIW_HDMIEDID_B)
5054#define CPT_AUD_CNTL_ST_A 0xE50B4
5055#define CPT_AUD_CNTL_ST_B 0xE51B4
5056#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5057 CPT_AUD_CNTL_ST_A, \
5058 CPT_AUD_CNTL_ST_B)
5059#define CPT_AUD_CNTRL_ST2 0xE50C0
5060
5061#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
5062#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
5063#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5064 VLV_HDMIW_HDMIEDID_A, \
5065 VLV_HDMIW_HDMIEDID_B)
5066#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
5067#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
5068#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5069 VLV_AUD_CNTL_ST_A, \
5070 VLV_AUD_CNTL_ST_B)
5071#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
5072
5073
5074
5075
5076
5077#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
5078
5079#define IBX_AUD_CONFIG_A 0xe2000
5080#define IBX_AUD_CONFIG_B 0xe2100
5081#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5082 IBX_AUD_CONFIG_A, \
5083 IBX_AUD_CONFIG_B)
5084#define CPT_AUD_CONFIG_A 0xe5000
5085#define CPT_AUD_CONFIG_B 0xe5100
5086#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5087 CPT_AUD_CONFIG_A, \
5088 CPT_AUD_CONFIG_B)
5089#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
5090#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
5091#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5092 VLV_AUD_CONFIG_A, \
5093 VLV_AUD_CONFIG_B)
5094
5095#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
5096#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
5097#define AUD_CONFIG_UPPER_N_SHIFT 20
5098#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
5099#define AUD_CONFIG_LOWER_N_SHIFT 4
5100#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
5101#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
5102#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
5103#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
5104#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
5105#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
5106#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
5107#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
5108#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
5109#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
5110#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
5111#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
5112#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
5113#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
5114
5115
5116#define HSW_AUD_CONFIG_A 0x65000
5117#define HSW_AUD_CONFIG_B 0x65100
5118#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5119 HSW_AUD_CONFIG_A, \
5120 HSW_AUD_CONFIG_B)
5121
5122#define HSW_AUD_MISC_CTRL_A 0x65010
5123#define HSW_AUD_MISC_CTRL_B 0x65110
5124#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5125 HSW_AUD_MISC_CTRL_A, \
5126 HSW_AUD_MISC_CTRL_B)
5127
5128#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
5129#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
5130#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5131 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5132 HSW_AUD_DIP_ELD_CTRL_ST_B)
5133
5134
5135#define HSW_AUD_DIG_CNVT_1 0x65080
5136#define HSW_AUD_DIG_CNVT_2 0x65180
5137#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5138 HSW_AUD_DIG_CNVT_1, \
5139 HSW_AUD_DIG_CNVT_2)
5140#define DIP_PORT_SEL_MASK 0x3
5141
5142#define HSW_AUD_EDID_DATA_A 0x65050
5143#define HSW_AUD_EDID_DATA_B 0x65150
5144#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5145 HSW_AUD_EDID_DATA_A, \
5146 HSW_AUD_EDID_DATA_B)
5147
5148#define HSW_AUD_PIPE_CONV_CFG 0x6507c
5149#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
5150#define AUDIO_INACTIVE_C (1<<11)
5151#define AUDIO_INACTIVE_B (1<<7)
5152#define AUDIO_INACTIVE_A (1<<3)
5153#define AUDIO_OUTPUT_ENABLE_A (1<<2)
5154#define AUDIO_OUTPUT_ENABLE_B (1<<6)
5155#define AUDIO_OUTPUT_ENABLE_C (1<<10)
5156#define AUDIO_ELD_VALID_A (1<<0)
5157#define AUDIO_ELD_VALID_B (1<<4)
5158#define AUDIO_ELD_VALID_C (1<<8)
5159#define AUDIO_CP_READY_A (1<<1)
5160#define AUDIO_CP_READY_B (1<<5)
5161#define AUDIO_CP_READY_C (1<<9)
5162
5163
5164#define HSW_PWR_WELL_BIOS 0x45400
5165#define HSW_PWR_WELL_DRIVER 0x45404
5166#define HSW_PWR_WELL_KVMR 0x45408
5167#define HSW_PWR_WELL_DEBUG 0x4540C
5168#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5169#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
5170#define HSW_PWR_WELL_CTL5 0x45410
5171#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5172#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
5173#define HSW_PWR_WELL_FORCE_ON (1<<19)
5174#define HSW_PWR_WELL_CTL6 0x45414
5175
5176
5177#define TRANS_DDI_FUNC_CTL_A 0x60400
5178#define TRANS_DDI_FUNC_CTL_B 0x61400
5179#define TRANS_DDI_FUNC_CTL_C 0x62400
5180#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
5181#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
5182 TRANS_DDI_FUNC_CTL_B)
5183#define TRANS_DDI_FUNC_ENABLE (1<<31)
5184
5185#define TRANS_DDI_PORT_MASK (7<<28)
5186#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5187#define TRANS_DDI_PORT_NONE (0<<28)
5188#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5189#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5190#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5191#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5192#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5193#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5194#define TRANS_DDI_BPC_MASK (7<<20)
5195#define TRANS_DDI_BPC_8 (0<<20)
5196#define TRANS_DDI_BPC_10 (1<<20)
5197#define TRANS_DDI_BPC_6 (2<<20)
5198#define TRANS_DDI_BPC_12 (3<<20)
5199#define TRANS_DDI_PVSYNC (1<<17)
5200#define TRANS_DDI_PHSYNC (1<<16)
5201#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5202#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5203#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5204#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5205#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5206#define TRANS_DDI_BFI_ENABLE (1<<4)
5207
5208
5209#define DP_TP_CTL_A 0x64040
5210#define DP_TP_CTL_B 0x64140
5211#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5212#define DP_TP_CTL_ENABLE (1<<31)
5213#define DP_TP_CTL_MODE_SST (0<<27)
5214#define DP_TP_CTL_MODE_MST (1<<27)
5215#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
5216#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
5217#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5218#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5219#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
5220#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5221#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
5222#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
5223#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
5224
5225
5226#define DP_TP_STATUS_A 0x64044
5227#define DP_TP_STATUS_B 0x64144
5228#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
5229#define DP_TP_STATUS_IDLE_DONE (1<<25)
5230#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5231
5232
5233#define DDI_BUF_CTL_A 0x64000
5234#define DDI_BUF_CTL_B 0x64100
5235#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5236#define DDI_BUF_CTL_ENABLE (1<<31)
5237
5238#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24)
5239#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24)
5240#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24)
5241#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24)
5242#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24)
5243#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24)
5244#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24)
5245#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24)
5246#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24)
5247
5248#define DDI_BUF_EMP_400MV_0DB_BDW (0<<24)
5249#define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24)
5250#define DDI_BUF_EMP_400MV_6DB_BDW (2<<24)
5251#define DDI_BUF_EMP_600MV_0DB_BDW (3<<24)
5252#define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24)
5253#define DDI_BUF_EMP_600MV_6DB_BDW (5<<24)
5254#define DDI_BUF_EMP_800MV_0DB_BDW (6<<24)
5255#define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24)
5256#define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24)
5257#define DDI_BUF_EMP_MASK (0xf<<24)
5258#define DDI_BUF_PORT_REVERSAL (1<<16)
5259#define DDI_BUF_IS_IDLE (1<<7)
5260#define DDI_A_4_LANES (1<<4)
5261#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
5262#define DDI_INIT_DISPLAY_DETECTED (1<<0)
5263
5264
5265#define DDI_BUF_TRANS_A 0x64E00
5266#define DDI_BUF_TRANS_B 0x64E60
5267#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
5268
5269
5270
5271
5272#define SBI_ADDR 0xC6000
5273#define SBI_DATA 0xC6004
5274#define SBI_CTL_STAT 0xC6008
5275#define SBI_CTL_DEST_ICLK (0x0<<16)
5276#define SBI_CTL_DEST_MPHY (0x1<<16)
5277#define SBI_CTL_OP_IORD (0x2<<8)
5278#define SBI_CTL_OP_IOWR (0x3<<8)
5279#define SBI_CTL_OP_CRRD (0x6<<8)
5280#define SBI_CTL_OP_CRWR (0x7<<8)
5281#define SBI_RESPONSE_FAIL (0x1<<1)
5282#define SBI_RESPONSE_SUCCESS (0x0<<1)
5283#define SBI_BUSY (0x1<<0)
5284#define SBI_READY (0x0<<0)
5285
5286
5287#define SBI_SSCDIVINTPHASE6 0x0600
5288#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
5289#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
5290#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
5291#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
5292#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
5293#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
5294#define SBI_SSCCTL 0x020c
5295#define SBI_SSCCTL6 0x060C
5296#define SBI_SSCCTL_PATHALT (1<<3)
5297#define SBI_SSCCTL_DISABLE (1<<0)
5298#define SBI_SSCAUXDIV6 0x0610
5299#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
5300#define SBI_DBUFF0 0x2a00
5301#define SBI_GEN0 0x1f00
5302#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
5303
5304
5305#define PIXCLK_GATE 0xC6020
5306#define PIXCLK_GATE_UNGATE (1<<0)
5307#define PIXCLK_GATE_GATE (0<<0)
5308
5309
5310#define SPLL_CTL 0x46020
5311#define SPLL_PLL_ENABLE (1<<31)
5312#define SPLL_PLL_SSC (1<<28)
5313#define SPLL_PLL_NON_SSC (2<<28)
5314#define SPLL_PLL_FREQ_810MHz (0<<26)
5315#define SPLL_PLL_FREQ_1350MHz (1<<26)
5316
5317
5318#define WRPLL_CTL1 0x46040
5319#define WRPLL_CTL2 0x46060
5320#define WRPLL_PLL_ENABLE (1<<31)
5321#define WRPLL_PLL_SELECT_SSC (0x01<<28)
5322#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
5323#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
5324
5325#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
5326#define WRPLL_DIVIDER_POST(x) ((x)<<8)
5327#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
5328
5329
5330#define PORT_CLK_SEL_A 0x46100
5331#define PORT_CLK_SEL_B 0x46104
5332#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
5333#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
5334#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
5335#define PORT_CLK_SEL_LCPLL_810 (2<<29)
5336#define PORT_CLK_SEL_SPLL (3<<29)
5337#define PORT_CLK_SEL_WRPLL1 (4<<29)
5338#define PORT_CLK_SEL_WRPLL2 (5<<29)
5339#define PORT_CLK_SEL_NONE (7<<29)
5340
5341
5342#define TRANS_CLK_SEL_A 0x46140
5343#define TRANS_CLK_SEL_B 0x46144
5344#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5345
5346#define TRANS_CLK_SEL_DISABLED (0x0<<29)
5347#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
5348
5349#define _TRANSA_MSA_MISC 0x60410
5350#define _TRANSB_MSA_MISC 0x61410
5351#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
5352 _TRANSB_MSA_MISC)
5353#define TRANS_MSA_SYNC_CLK (1<<0)
5354#define TRANS_MSA_6_BPC (0<<5)
5355#define TRANS_MSA_8_BPC (1<<5)
5356#define TRANS_MSA_10_BPC (2<<5)
5357#define TRANS_MSA_12_BPC (3<<5)
5358#define TRANS_MSA_16_BPC (4<<5)
5359
5360
5361#define LCPLL_CTL 0x130040
5362#define LCPLL_PLL_DISABLE (1<<31)
5363#define LCPLL_PLL_LOCK (1<<30)
5364#define LCPLL_CLK_FREQ_MASK (3<<26)
5365#define LCPLL_CLK_FREQ_450 (0<<26)
5366#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
5367#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
5368#define LCPLL_CLK_FREQ_675_BDW (3<<26)
5369#define LCPLL_CD_CLOCK_DISABLE (1<<25)
5370#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
5371#define LCPLL_POWER_DOWN_ALLOW (1<<22)
5372#define LCPLL_CD_SOURCE_FCLK (1<<21)
5373#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5374
5375#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5376#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5377#define D_COMP_COMP_FORCE (1<<8)
5378#define D_COMP_COMP_DISABLE (1<<0)
5379
5380
5381#define PIPE_WM_LINETIME_A 0x45270
5382#define PIPE_WM_LINETIME_B 0x45274
5383#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5384 PIPE_WM_LINETIME_B)
5385#define PIPE_WM_LINETIME_MASK (0x1ff)
5386#define PIPE_WM_LINETIME_TIME(x) ((x))
5387#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
5388#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
5389
5390
5391#define SFUSE_STRAP 0xc2014
5392#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5393#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5394#define SFUSE_STRAP_DDID_DETECTED (1<<0)
5395
5396#define WM_MISC 0x45260
5397#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5398
5399#define WM_DBG 0x45280
5400#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5401#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5402#define WM_DBG_DISALLOW_SPRITE (1<<2)
5403
5404
5405#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5406#define _PIPE_A_CSC_COEFF_BY 0x49014
5407#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5408#define _PIPE_A_CSC_COEFF_BU 0x4901c
5409#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5410#define _PIPE_A_CSC_COEFF_BV 0x49024
5411#define _PIPE_A_CSC_MODE 0x49028
5412#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
5413#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
5414#define CSC_MODE_YUV_TO_RGB (1 << 0)
5415#define _PIPE_A_CSC_PREOFF_HI 0x49030
5416#define _PIPE_A_CSC_PREOFF_ME 0x49034
5417#define _PIPE_A_CSC_PREOFF_LO 0x49038
5418#define _PIPE_A_CSC_POSTOFF_HI 0x49040
5419#define _PIPE_A_CSC_POSTOFF_ME 0x49044
5420#define _PIPE_A_CSC_POSTOFF_LO 0x49048
5421
5422#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
5423#define _PIPE_B_CSC_COEFF_BY 0x49114
5424#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
5425#define _PIPE_B_CSC_COEFF_BU 0x4911c
5426#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
5427#define _PIPE_B_CSC_COEFF_BV 0x49124
5428#define _PIPE_B_CSC_MODE 0x49128
5429#define _PIPE_B_CSC_PREOFF_HI 0x49130
5430#define _PIPE_B_CSC_PREOFF_ME 0x49134
5431#define _PIPE_B_CSC_PREOFF_LO 0x49138
5432#define _PIPE_B_CSC_POSTOFF_HI 0x49140
5433#define _PIPE_B_CSC_POSTOFF_ME 0x49144
5434#define _PIPE_B_CSC_POSTOFF_LO 0x49148
5435
5436#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5437#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5438#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5439#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5440#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5441#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5442#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5443#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5444#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5445#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5446#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5447#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5448#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5449
5450
5451
5452#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
5453#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
5454#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
5455#define DPI_ENABLE (1 << 31)
5456#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
5457#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
5458#define DUAL_LINK_MODE_MASK (1 << 26)
5459#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
5460#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
5461#define DITHERING_ENABLE (1 << 25)
5462#define FLOPPED_HSTX (1 << 23)
5463#define DE_INVERT (1 << 19)
5464#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
5465#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
5466#define AFE_LATCHOUT (1 << 17)
5467#define LP_OUTPUT_HOLD (1 << 16)
5468#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
5469#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
5470#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
5471#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
5472#define CSB_SHIFT 9
5473#define CSB_MASK (3 << 9)
5474#define CSB_20MHZ (0 << 9)
5475#define CSB_10MHZ (1 << 9)
5476#define CSB_40MHZ (2 << 9)
5477#define BANDGAP_MASK (1 << 8)
5478#define BANDGAP_PNW_CIRCUIT (0 << 8)
5479#define BANDGAP_LNC_CIRCUIT (1 << 8)
5480#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
5481#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
5482#define TEARING_EFFECT_DELAY (1 << 4)
5483#define TEARING_EFFECT_SHIFT 2
5484#define TEARING_EFFECT_MASK (3 << 2)
5485#define TEARING_EFFECT_OFF (0 << 2)
5486#define TEARING_EFFECT_DSI (1 << 2)
5487#define TEARING_EFFECT_GPIO (2 << 2)
5488#define LANE_CONFIGURATION_SHIFT 0
5489#define LANE_CONFIGURATION_MASK (3 << 0)
5490#define LANE_CONFIGURATION_4LANE (0 << 0)
5491#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
5492#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
5493
5494#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
5495#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
5496#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
5497#define TEARING_EFFECT_DELAY_SHIFT 0
5498#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
5499
5500
5501#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
5502
5503
5504
5505#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
5506#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
5507#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
5508#define BUS_POSSESSION (1 << 3)
5509#define ULPS_STATE_MASK (3 << 1)
5510#define ULPS_STATE_ENTER (2 << 1)
5511#define ULPS_STATE_EXIT (1 << 1)
5512#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
5513#define DEVICE_READY (1 << 0)
5514
5515#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
5516#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
5517#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
5518#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
5519#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
5520#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
5521#define TEARING_EFFECT (1 << 31)
5522#define SPL_PKT_SENT_INTERRUPT (1 << 30)
5523#define GEN_READ_DATA_AVAIL (1 << 29)
5524#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
5525#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
5526#define RX_PROT_VIOLATION (1 << 26)
5527#define RX_INVALID_TX_LENGTH (1 << 25)
5528#define ACK_WITH_NO_ERROR (1 << 24)
5529#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
5530#define LP_RX_TIMEOUT (1 << 22)
5531#define HS_TX_TIMEOUT (1 << 21)
5532#define DPI_FIFO_UNDERRUN (1 << 20)
5533#define LOW_CONTENTION (1 << 19)
5534#define HIGH_CONTENTION (1 << 18)
5535#define TXDSI_VC_ID_INVALID (1 << 17)
5536#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
5537#define TXCHECKSUM_ERROR (1 << 15)
5538#define TXECC_MULTIBIT_ERROR (1 << 14)
5539#define TXECC_SINGLE_BIT_ERROR (1 << 13)
5540#define TXFALSE_CONTROL_ERROR (1 << 12)
5541#define RXDSI_VC_ID_INVALID (1 << 11)
5542#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
5543#define RXCHECKSUM_ERROR (1 << 9)
5544#define RXECC_MULTIBIT_ERROR (1 << 8)
5545#define RXECC_SINGLE_BIT_ERROR (1 << 7)
5546#define RXFALSE_CONTROL_ERROR (1 << 6)
5547#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
5548#define RX_LP_TX_SYNC_ERROR (1 << 4)
5549#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
5550#define RXEOT_SYNC_ERROR (1 << 2)
5551#define RXSOT_SYNC_ERROR (1 << 1)
5552#define RXSOT_ERROR (1 << 0)
5553
5554#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
5555#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
5556#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
5557#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
5558#define CMD_MODE_NOT_SUPPORTED (0 << 13)
5559#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
5560#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
5561#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
5562#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
5563#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
5564#define VID_MODE_FORMAT_MASK (0xf << 7)
5565#define VID_MODE_NOT_SUPPORTED (0 << 7)
5566#define VID_MODE_FORMAT_RGB565 (1 << 7)
5567#define VID_MODE_FORMAT_RGB666 (2 << 7)
5568#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
5569#define VID_MODE_FORMAT_RGB888 (4 << 7)
5570#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
5571#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
5572#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
5573#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
5574#define DATA_LANES_PRG_REG_SHIFT 0
5575#define DATA_LANES_PRG_REG_MASK (7 << 0)
5576
5577#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
5578#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
5579#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
5580#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
5581
5582#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
5583#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
5584#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
5585#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
5586
5587#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
5588#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
5589#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
5590#define TURN_AROUND_TIMEOUT_MASK 0x3f
5591
5592#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
5593#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
5594#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
5595#define DEVICE_RESET_TIMER_MASK 0xffff
5596
5597#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
5598#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
5599#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
5600#define VERTICAL_ADDRESS_SHIFT 16
5601#define VERTICAL_ADDRESS_MASK (0xffff << 16)
5602#define HORIZONTAL_ADDRESS_SHIFT 0
5603#define HORIZONTAL_ADDRESS_MASK 0xffff
5604
5605#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
5606#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
5607#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
5608#define DBI_FIFO_EMPTY_HALF (0 << 0)
5609#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
5610#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
5611
5612
5613#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
5614#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
5615#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
5616
5617#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
5618#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
5619#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
5620
5621#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
5622#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
5623#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
5624
5625#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
5626#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
5627#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
5628
5629#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
5630#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
5631#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
5632
5633#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
5634#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
5635#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
5636
5637#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
5638#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
5639#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
5640
5641#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
5642#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
5643#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
5644
5645
5646#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
5647#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
5648#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
5649#define DPI_LP_MODE (1 << 6)
5650#define BACKLIGHT_OFF (1 << 5)
5651#define BACKLIGHT_ON (1 << 4)
5652#define COLOR_MODE_OFF (1 << 3)
5653#define COLOR_MODE_ON (1 << 2)
5654#define TURN_ON (1 << 1)
5655#define SHUTDOWN (1 << 0)
5656
5657#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
5658#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
5659#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
5660#define COMMAND_BYTE_SHIFT 0
5661#define COMMAND_BYTE_MASK (0x3f << 0)
5662
5663#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
5664#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
5665#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
5666#define MASTER_INIT_TIMER_SHIFT 0
5667#define MASTER_INIT_TIMER_MASK (0xffff << 0)
5668
5669#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
5670#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
5671#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
5672#define MAX_RETURN_PKT_SIZE_SHIFT 0
5673#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
5674
5675#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
5676#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
5677#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
5678#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
5679#define DISABLE_VIDEO_BTA (1 << 3)
5680#define IP_TG_CONFIG (1 << 2)
5681#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
5682#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
5683#define VIDEO_MODE_BURST (3 << 0)
5684
5685#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
5686#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
5687#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
5688#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
5689#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
5690#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
5691#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
5692#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
5693#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
5694#define CLOCKSTOP (1 << 1)
5695#define EOT_DISABLE (1 << 0)
5696
5697#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
5698#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
5699#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
5700#define LP_BYTECLK_SHIFT 0
5701#define LP_BYTECLK_MASK (0xffff << 0)
5702
5703
5704#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
5705#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
5706#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
5707
5708
5709#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
5710#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
5711#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
5712
5713#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
5714#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
5715#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
5716#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
5717#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
5718#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
5719#define LONG_PACKET_WORD_COUNT_SHIFT 8
5720#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
5721#define SHORT_PACKET_PARAM_SHIFT 8
5722#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
5723#define VIRTUAL_CHANNEL_SHIFT 6
5724#define VIRTUAL_CHANNEL_MASK (3 << 6)
5725#define DATA_TYPE_SHIFT 0
5726#define DATA_TYPE_MASK (3f << 0)
5727
5728
5729#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
5730#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
5731#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
5732#define DPI_FIFO_EMPTY (1 << 28)
5733#define DBI_FIFO_EMPTY (1 << 27)
5734#define LP_CTRL_FIFO_EMPTY (1 << 26)
5735#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
5736#define LP_CTRL_FIFO_FULL (1 << 24)
5737#define HS_CTRL_FIFO_EMPTY (1 << 18)
5738#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
5739#define HS_CTRL_FIFO_FULL (1 << 16)
5740#define LP_DATA_FIFO_EMPTY (1 << 10)
5741#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
5742#define LP_DATA_FIFO_FULL (1 << 8)
5743#define HS_DATA_FIFO_EMPTY (1 << 2)
5744#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
5745#define HS_DATA_FIFO_FULL (1 << 0)
5746
5747#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
5748#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
5749#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
5750#define DBI_HS_LP_MODE_MASK (1 << 0)
5751#define DBI_LP_MODE (1 << 0)
5752#define DBI_HS_MODE (0 << 0)
5753
5754#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
5755#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
5756#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
5757#define EXIT_ZERO_COUNT_SHIFT 24
5758#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
5759#define TRAIL_COUNT_SHIFT 16
5760#define TRAIL_COUNT_MASK (0x1f << 16)
5761#define CLK_ZERO_COUNT_SHIFT 8
5762#define CLK_ZERO_COUNT_MASK (0xff << 8)
5763#define PREPARE_COUNT_SHIFT 0
5764#define PREPARE_COUNT_MASK (0x3f << 0)
5765
5766
5767#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
5768#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
5769#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
5770
5771#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
5772#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
5773#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
5774#define LP_HS_SSW_CNT_SHIFT 16
5775#define LP_HS_SSW_CNT_MASK (0xffff << 16)
5776#define HS_LP_PWR_SW_CNT_SHIFT 0
5777#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
5778
5779#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
5780#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
5781#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
5782#define STOP_STATE_STALL_COUNTER_SHIFT 0
5783#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
5784
5785#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
5786#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
5787#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
5788#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
5789#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
5790#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
5791#define RX_CONTENTION_DETECTED (1 << 0)
5792
5793
5794#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
5795#define DBI_TYPEC_ENABLE (1 << 31)
5796#define DBI_TYPEC_WIP (1 << 30)
5797#define DBI_TYPEC_OPTION_SHIFT 28
5798#define DBI_TYPEC_OPTION_MASK (3 << 28)
5799#define DBI_TYPEC_FREQ_SHIFT 24
5800#define DBI_TYPEC_FREQ_MASK (0xf << 24)
5801#define DBI_TYPEC_OVERRIDE (1 << 8)
5802#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
5803#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
5804
5805
5806
5807
5808#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
5809#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
5810#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
5811#define ESCAPE_CLOCK_DIVIDER_SHIFT 5
5812#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
5813#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
5814#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
5815#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
5816#define READ_REQUEST_PRIORITY_SHIFT 3
5817#define READ_REQUEST_PRIORITY_MASK (3 << 3)
5818#define READ_REQUEST_PRIORITY_LOW (0 << 3)
5819#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
5820#define RGB_FLIP_TO_BGR (1 << 2)
5821
5822#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
5823#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
5824#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
5825#define DATA_MEM_ADDRESS_SHIFT 5
5826#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
5827#define DATA_VALID (1 << 0)
5828
5829#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
5830#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
5831#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
5832#define DATA_LENGTH_SHIFT 0
5833#define DATA_LENGTH_MASK (0xfffff << 0)
5834
5835#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
5836#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
5837#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
5838#define COMMAND_MEM_ADDRESS_SHIFT 5
5839#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
5840#define AUTO_PWG_ENABLE (1 << 2)
5841#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
5842#define COMMAND_VALID (1 << 0)
5843
5844#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
5845#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
5846#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
5847#define COMMAND_LENGTH_SHIFT(n) (8 * (n))
5848#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
5849
5850#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
5851#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
5852#define MIPI_READ_DATA_RETURN(pipe, n) \
5853 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n))
5854
5855#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
5856#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
5857#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
5858#define READ_DATA_VALID(n) (1 << (n))
5859
5860#endif
5861