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25#include <linux/module.h>
26#include <linux/types.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/string.h>
30#include <linux/ioport.h>
31#include <linux/of_address.h>
32#include <linux/of_platform.h>
33#include <linux/platform_device.h>
34#include <linux/slab.h>
35#include <linux/interrupt.h>
36
37#include <linux/mtd/mtd.h>
38#include <linux/mtd/nand.h>
39#include <linux/mtd/nand_ecc.h>
40#include <linux/mtd/partitions.h>
41
42#include <asm/io.h>
43#include <asm/fsl_lbc.h>
44
45#define MAX_BANKS 8
46#define ERR_BYTE 0xFF
47#define FCM_TIMEOUT_MSECS 500
48
49
50
51struct fsl_elbc_mtd {
52 struct mtd_info mtd;
53 struct nand_chip chip;
54 struct fsl_lbc_ctrl *ctrl;
55
56 struct device *dev;
57 int bank;
58 u8 __iomem *vbase;
59 int page_size;
60 unsigned int fmr;
61};
62
63
64
65struct fsl_elbc_fcm_ctrl {
66 struct nand_hw_control controller;
67 struct fsl_elbc_mtd *chips[MAX_BANKS];
68
69 u8 __iomem *addr;
70 unsigned int page;
71 unsigned int read_bytes;
72 unsigned int column;
73 unsigned int index;
74 unsigned int status;
75 unsigned int mdr;
76 unsigned int use_mdr;
77 unsigned int oob;
78 unsigned int counter;
79 unsigned int max_bitflips;
80};
81
82
83
84
85static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
86 .eccbytes = 3,
87 .eccpos = {6, 7, 8},
88 .oobfree = { {0, 5}, {9, 7} },
89};
90
91
92static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
93 .eccbytes = 3,
94 .eccpos = {8, 9, 10},
95 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
96};
97
98
99static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
100 .eccbytes = 12,
101 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
102 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
103};
104
105
106static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
107 .eccbytes = 12,
108 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
109 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
110};
111
112
113
114
115
116
117static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
118static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
119
120static struct nand_bbt_descr bbt_main_descr = {
121 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
122 NAND_BBT_2BIT | NAND_BBT_VERSION,
123 .offs = 11,
124 .len = 4,
125 .veroffs = 15,
126 .maxblocks = 4,
127 .pattern = bbt_pattern,
128};
129
130static struct nand_bbt_descr bbt_mirror_descr = {
131 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
132 NAND_BBT_2BIT | NAND_BBT_VERSION,
133 .offs = 11,
134 .len = 4,
135 .veroffs = 15,
136 .maxblocks = 4,
137 .pattern = mirror_pattern,
138};
139
140
141
142
143
144
145
146static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
147{
148 struct nand_chip *chip = mtd->priv;
149 struct fsl_elbc_mtd *priv = chip->priv;
150 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
151 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
152 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
153 int buf_num;
154
155 elbc_fcm_ctrl->page = page_addr;
156
157 if (priv->page_size) {
158
159
160
161
162 out_be32(&lbc->fbar, page_addr >> 6);
163 out_be32(&lbc->fpar,
164 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
165 (oob ? FPAR_LP_MS : 0) | column);
166 buf_num = (page_addr & 1) << 2;
167 } else {
168
169
170
171
172 out_be32(&lbc->fbar, page_addr >> 5);
173 out_be32(&lbc->fpar,
174 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
175 (oob ? FPAR_SP_MS : 0) | column);
176 buf_num = page_addr & 7;
177 }
178
179 elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
180 elbc_fcm_ctrl->index = column;
181
182
183 if (oob)
184 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
185
186 dev_vdbg(priv->dev, "set_addr: bank=%d, "
187 "elbc_fcm_ctrl->addr=0x%p (0x%p), "
188 "index %x, pes %d ps %d\n",
189 buf_num, elbc_fcm_ctrl->addr, priv->vbase,
190 elbc_fcm_ctrl->index,
191 chip->phys_erase_shift, chip->page_shift);
192}
193
194
195
196
197static int fsl_elbc_run_command(struct mtd_info *mtd)
198{
199 struct nand_chip *chip = mtd->priv;
200 struct fsl_elbc_mtd *priv = chip->priv;
201 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
202 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
203 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
204
205
206 out_be32(&lbc->fmr, priv->fmr | 3);
207 if (elbc_fcm_ctrl->use_mdr)
208 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
209
210 dev_vdbg(priv->dev,
211 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
212 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
213 dev_vdbg(priv->dev,
214 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
215 "fbcr=%08x bank=%d\n",
216 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
217 in_be32(&lbc->fbcr), priv->bank);
218
219 ctrl->irq_status = 0;
220
221 out_be32(&lbc->lsor, priv->bank);
222
223
224 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
225 FCM_TIMEOUT_MSECS * HZ/1000);
226 elbc_fcm_ctrl->status = ctrl->irq_status;
227
228 if (elbc_fcm_ctrl->use_mdr)
229 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
230
231 elbc_fcm_ctrl->use_mdr = 0;
232
233 if (elbc_fcm_ctrl->status != LTESR_CC) {
234 dev_info(priv->dev,
235 "command failed: fir %x fcr %x status %x mdr %x\n",
236 in_be32(&lbc->fir), in_be32(&lbc->fcr),
237 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
238 return -EIO;
239 }
240
241 if (chip->ecc.mode != NAND_ECC_HW)
242 return 0;
243
244 elbc_fcm_ctrl->max_bitflips = 0;
245
246 if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
247 uint32_t lteccr = in_be32(&lbc->lteccr);
248
249
250
251
252
253
254
255
256
257
258
259 if (lteccr & 0x000F000F)
260 out_be32(&lbc->lteccr, 0x000F000F);
261 if (lteccr & 0x000F0000) {
262 mtd->ecc_stats.corrected++;
263 elbc_fcm_ctrl->max_bitflips = 1;
264 }
265 }
266
267 return 0;
268}
269
270static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
271{
272 struct fsl_elbc_mtd *priv = chip->priv;
273 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
274 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
275
276 if (priv->page_size) {
277 out_be32(&lbc->fir,
278 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
279 (FIR_OP_CA << FIR_OP1_SHIFT) |
280 (FIR_OP_PA << FIR_OP2_SHIFT) |
281 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
282 (FIR_OP_RBW << FIR_OP4_SHIFT));
283
284 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
285 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
286 } else {
287 out_be32(&lbc->fir,
288 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
289 (FIR_OP_CA << FIR_OP1_SHIFT) |
290 (FIR_OP_PA << FIR_OP2_SHIFT) |
291 (FIR_OP_RBW << FIR_OP3_SHIFT));
292
293 if (oob)
294 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
295 else
296 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
297 }
298}
299
300
301static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
302 int column, int page_addr)
303{
304 struct nand_chip *chip = mtd->priv;
305 struct fsl_elbc_mtd *priv = chip->priv;
306 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
307 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
308 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
309
310 elbc_fcm_ctrl->use_mdr = 0;
311
312
313 elbc_fcm_ctrl->read_bytes = 0;
314 if (command != NAND_CMD_PAGEPROG)
315 elbc_fcm_ctrl->index = 0;
316
317 switch (command) {
318
319 case NAND_CMD_READ1:
320 column += 256;
321
322
323 case NAND_CMD_READ0:
324 dev_dbg(priv->dev,
325 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
326 " 0x%x, column: 0x%x.\n", page_addr, column);
327
328
329 out_be32(&lbc->fbcr, 0);
330 set_addr(mtd, 0, page_addr, 0);
331
332 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
333 elbc_fcm_ctrl->index += column;
334
335 fsl_elbc_do_read(chip, 0);
336 fsl_elbc_run_command(mtd);
337 return;
338
339
340 case NAND_CMD_READOOB:
341 dev_vdbg(priv->dev,
342 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
343 " 0x%x, column: 0x%x.\n", page_addr, column);
344
345 out_be32(&lbc->fbcr, mtd->oobsize - column);
346 set_addr(mtd, column, page_addr, 1);
347
348 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
349
350 fsl_elbc_do_read(chip, 1);
351 fsl_elbc_run_command(mtd);
352 return;
353
354 case NAND_CMD_READID:
355 case NAND_CMD_PARAM:
356 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
357
358 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
359 (FIR_OP_UA << FIR_OP1_SHIFT) |
360 (FIR_OP_RBW << FIR_OP2_SHIFT));
361 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
362
363
364
365
366 out_be32(&lbc->fbcr, 256);
367 elbc_fcm_ctrl->read_bytes = 256;
368 elbc_fcm_ctrl->use_mdr = 1;
369 elbc_fcm_ctrl->mdr = column;
370 set_addr(mtd, 0, 0, 0);
371 fsl_elbc_run_command(mtd);
372 return;
373
374
375 case NAND_CMD_ERASE1:
376 dev_vdbg(priv->dev,
377 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
378 "page_addr: 0x%x.\n", page_addr);
379 set_addr(mtd, 0, page_addr, 0);
380 return;
381
382
383 case NAND_CMD_ERASE2:
384 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
385
386 out_be32(&lbc->fir,
387 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
388 (FIR_OP_PA << FIR_OP1_SHIFT) |
389 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
390 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
391 (FIR_OP_RS << FIR_OP4_SHIFT));
392
393 out_be32(&lbc->fcr,
394 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
395 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
396 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
397
398 out_be32(&lbc->fbcr, 0);
399 elbc_fcm_ctrl->read_bytes = 0;
400 elbc_fcm_ctrl->use_mdr = 1;
401
402 fsl_elbc_run_command(mtd);
403 return;
404
405
406 case NAND_CMD_SEQIN: {
407 __be32 fcr;
408 dev_vdbg(priv->dev,
409 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
410 "page_addr: 0x%x, column: 0x%x.\n",
411 page_addr, column);
412
413 elbc_fcm_ctrl->column = column;
414 elbc_fcm_ctrl->use_mdr = 1;
415
416 if (column >= mtd->writesize) {
417
418 column -= mtd->writesize;
419 elbc_fcm_ctrl->oob = 1;
420 } else {
421 WARN_ON(column != 0);
422 elbc_fcm_ctrl->oob = 0;
423 }
424
425 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
426 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
427 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
428
429 if (priv->page_size) {
430 out_be32(&lbc->fir,
431 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
432 (FIR_OP_CA << FIR_OP1_SHIFT) |
433 (FIR_OP_PA << FIR_OP2_SHIFT) |
434 (FIR_OP_WB << FIR_OP3_SHIFT) |
435 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
436 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
437 (FIR_OP_RS << FIR_OP6_SHIFT));
438 } else {
439 out_be32(&lbc->fir,
440 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
441 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
442 (FIR_OP_CA << FIR_OP2_SHIFT) |
443 (FIR_OP_PA << FIR_OP3_SHIFT) |
444 (FIR_OP_WB << FIR_OP4_SHIFT) |
445 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
446 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
447 (FIR_OP_RS << FIR_OP7_SHIFT));
448
449 if (elbc_fcm_ctrl->oob)
450
451 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
452 else
453
454 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
455 }
456
457 out_be32(&lbc->fcr, fcr);
458 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
459 return;
460 }
461
462
463 case NAND_CMD_PAGEPROG: {
464 dev_vdbg(priv->dev,
465 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
466 "writing %d bytes.\n", elbc_fcm_ctrl->index);
467
468
469
470
471
472 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
473 elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
474 out_be32(&lbc->fbcr,
475 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
476 else
477 out_be32(&lbc->fbcr, 0);
478
479 fsl_elbc_run_command(mtd);
480 return;
481 }
482
483
484
485 case NAND_CMD_STATUS:
486 out_be32(&lbc->fir,
487 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
488 (FIR_OP_RBW << FIR_OP1_SHIFT));
489 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
490 out_be32(&lbc->fbcr, 1);
491 set_addr(mtd, 0, 0, 0);
492 elbc_fcm_ctrl->read_bytes = 1;
493
494 fsl_elbc_run_command(mtd);
495
496
497
498
499 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
500 return;
501
502
503 case NAND_CMD_RESET:
504 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
505 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
506 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
507 fsl_elbc_run_command(mtd);
508 return;
509
510 default:
511 dev_err(priv->dev,
512 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
513 command);
514 }
515}
516
517static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
518{
519
520
521
522}
523
524
525
526
527static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
528{
529 struct nand_chip *chip = mtd->priv;
530 struct fsl_elbc_mtd *priv = chip->priv;
531 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
532 unsigned int bufsize = mtd->writesize + mtd->oobsize;
533
534 if (len <= 0) {
535 dev_err(priv->dev, "write_buf of %d bytes", len);
536 elbc_fcm_ctrl->status = 0;
537 return;
538 }
539
540 if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
541 dev_err(priv->dev,
542 "write_buf beyond end of buffer "
543 "(%d requested, %u available)\n",
544 len, bufsize - elbc_fcm_ctrl->index);
545 len = bufsize - elbc_fcm_ctrl->index;
546 }
547
548 memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
549
550
551
552
553
554
555
556 in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
557
558 elbc_fcm_ctrl->index += len;
559}
560
561
562
563
564
565static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
566{
567 struct nand_chip *chip = mtd->priv;
568 struct fsl_elbc_mtd *priv = chip->priv;
569 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
570
571
572 if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
573 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
574
575 dev_err(priv->dev, "read_byte beyond end of buffer\n");
576 return ERR_BYTE;
577}
578
579
580
581
582static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
583{
584 struct nand_chip *chip = mtd->priv;
585 struct fsl_elbc_mtd *priv = chip->priv;
586 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
587 int avail;
588
589 if (len < 0)
590 return;
591
592 avail = min((unsigned int)len,
593 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
594 memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
595 elbc_fcm_ctrl->index += avail;
596
597 if (len > avail)
598 dev_err(priv->dev,
599 "read_buf beyond end of buffer "
600 "(%d requested, %d available)\n",
601 len, avail);
602}
603
604
605
606
607static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
608{
609 struct fsl_elbc_mtd *priv = chip->priv;
610 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
611
612 if (elbc_fcm_ctrl->status != LTESR_CC)
613 return NAND_STATUS_FAIL;
614
615
616
617
618 return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
619}
620
621static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
622{
623 struct nand_chip *chip = mtd->priv;
624 struct fsl_elbc_mtd *priv = chip->priv;
625 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
626 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
627 unsigned int al;
628
629
630 al = 0;
631 if (chip->pagemask & 0xffff0000)
632 al++;
633 if (chip->pagemask & 0xff000000)
634 al++;
635
636 priv->fmr |= al << FMR_AL_SHIFT;
637
638 dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
639 chip->numchips);
640 dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
641 chip->chipsize);
642 dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
643 chip->pagemask);
644 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
645 chip->chip_delay);
646 dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
647 chip->badblockpos);
648 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
649 chip->chip_shift);
650 dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
651 chip->page_shift);
652 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
653 chip->phys_erase_shift);
654 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
655 chip->ecc.mode);
656 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
657 chip->ecc.steps);
658 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
659 chip->ecc.bytes);
660 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
661 chip->ecc.total);
662 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
663 chip->ecc.layout);
664 dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
665 dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
666 dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
667 mtd->erasesize);
668 dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
669 mtd->writesize);
670 dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
671 mtd->oobsize);
672
673
674 if (mtd->writesize == 512) {
675 priv->page_size = 0;
676 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
677 } else if (mtd->writesize == 2048) {
678 priv->page_size = 1;
679 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
680
681 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
682 BR_DECC_CHK_GEN) {
683 chip->ecc.size = 512;
684 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
685 &fsl_elbc_oob_lp_eccm1 :
686 &fsl_elbc_oob_lp_eccm0;
687 }
688 } else {
689 dev_err(priv->dev,
690 "fsl_elbc_init: page size %d is not supported\n",
691 mtd->writesize);
692 return -1;
693 }
694
695 return 0;
696}
697
698static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
699 uint8_t *buf, int oob_required, int page)
700{
701 struct fsl_elbc_mtd *priv = chip->priv;
702 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
703 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
704
705 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
706 if (oob_required)
707 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
708
709 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
710 mtd->ecc_stats.failed++;
711
712 return elbc_fcm_ctrl->max_bitflips;
713}
714
715
716
717
718static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
719 const uint8_t *buf, int oob_required)
720{
721 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
722 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
723
724 return 0;
725}
726
727static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
728{
729 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
730 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
731 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
732 struct nand_chip *chip = &priv->chip;
733
734 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
735
736
737 priv->mtd.priv = chip;
738 priv->mtd.owner = THIS_MODULE;
739
740
741 priv->fmr = 15 << FMR_CWTO_SHIFT;
742 if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
743 priv->fmr |= FMR_ECCM;
744
745
746
747 chip->read_byte = fsl_elbc_read_byte;
748 chip->write_buf = fsl_elbc_write_buf;
749 chip->read_buf = fsl_elbc_read_buf;
750 chip->select_chip = fsl_elbc_select_chip;
751 chip->cmdfunc = fsl_elbc_cmdfunc;
752 chip->waitfunc = fsl_elbc_wait;
753
754 chip->bbt_td = &bbt_main_descr;
755 chip->bbt_md = &bbt_mirror_descr;
756
757
758 chip->bbt_options = NAND_BBT_USE_FLASH;
759
760 chip->controller = &elbc_fcm_ctrl->controller;
761 chip->priv = priv;
762
763 chip->ecc.read_page = fsl_elbc_read_page;
764 chip->ecc.write_page = fsl_elbc_write_page;
765
766
767 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
768 BR_DECC_CHK_GEN) {
769 chip->ecc.mode = NAND_ECC_HW;
770
771 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
772 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
773 chip->ecc.size = 512;
774 chip->ecc.bytes = 3;
775 chip->ecc.strength = 1;
776 } else {
777
778 chip->ecc.mode = NAND_ECC_SOFT;
779 }
780
781 return 0;
782}
783
784static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
785{
786 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
787 nand_release(&priv->mtd);
788
789 kfree(priv->mtd.name);
790
791 if (priv->vbase)
792 iounmap(priv->vbase);
793
794 elbc_fcm_ctrl->chips[priv->bank] = NULL;
795 kfree(priv);
796 return 0;
797}
798
799static DEFINE_MUTEX(fsl_elbc_nand_mutex);
800
801static int fsl_elbc_nand_probe(struct platform_device *pdev)
802{
803 struct fsl_lbc_regs __iomem *lbc;
804 struct fsl_elbc_mtd *priv;
805 struct resource res;
806 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
807 static const char *part_probe_types[]
808 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
809 int ret;
810 int bank;
811 struct device *dev;
812 struct device_node *node = pdev->dev.of_node;
813 struct mtd_part_parser_data ppdata;
814
815 ppdata.of_node = pdev->dev.of_node;
816 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
817 return -ENODEV;
818 lbc = fsl_lbc_ctrl_dev->regs;
819 dev = fsl_lbc_ctrl_dev->dev;
820
821
822 ret = of_address_to_resource(node, 0, &res);
823 if (ret) {
824 dev_err(dev, "failed to get resource\n");
825 return ret;
826 }
827
828
829 for (bank = 0; bank < MAX_BANKS; bank++)
830 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
831 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
832 (in_be32(&lbc->bank[bank].br) &
833 in_be32(&lbc->bank[bank].or) & BR_BA)
834 == fsl_lbc_addr(res.start))
835 break;
836
837 if (bank >= MAX_BANKS) {
838 dev_err(dev, "address did not match any chip selects\n");
839 return -ENODEV;
840 }
841
842 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
843 if (!priv)
844 return -ENOMEM;
845
846 mutex_lock(&fsl_elbc_nand_mutex);
847 if (!fsl_lbc_ctrl_dev->nand) {
848 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
849 if (!elbc_fcm_ctrl) {
850 mutex_unlock(&fsl_elbc_nand_mutex);
851 ret = -ENOMEM;
852 goto err;
853 }
854 elbc_fcm_ctrl->counter++;
855
856 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
857 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
858 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
859 } else {
860 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
861 }
862 mutex_unlock(&fsl_elbc_nand_mutex);
863
864 elbc_fcm_ctrl->chips[bank] = priv;
865 priv->bank = bank;
866 priv->ctrl = fsl_lbc_ctrl_dev;
867 priv->dev = &pdev->dev;
868 dev_set_drvdata(priv->dev, priv);
869
870 priv->vbase = ioremap(res.start, resource_size(&res));
871 if (!priv->vbase) {
872 dev_err(dev, "failed to map chip region\n");
873 ret = -ENOMEM;
874 goto err;
875 }
876
877 priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
878 if (!priv->mtd.name) {
879 ret = -ENOMEM;
880 goto err;
881 }
882
883 ret = fsl_elbc_chip_init(priv);
884 if (ret)
885 goto err;
886
887 ret = nand_scan_ident(&priv->mtd, 1, NULL);
888 if (ret)
889 goto err;
890
891 ret = fsl_elbc_chip_init_tail(&priv->mtd);
892 if (ret)
893 goto err;
894
895 ret = nand_scan_tail(&priv->mtd);
896 if (ret)
897 goto err;
898
899
900
901 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
902 NULL, 0);
903
904 printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
905 (unsigned long long)res.start, priv->bank);
906 return 0;
907
908err:
909 fsl_elbc_chip_remove(priv);
910 return ret;
911}
912
913static int fsl_elbc_nand_remove(struct platform_device *pdev)
914{
915 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
916 struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
917
918 fsl_elbc_chip_remove(priv);
919
920 mutex_lock(&fsl_elbc_nand_mutex);
921 elbc_fcm_ctrl->counter--;
922 if (!elbc_fcm_ctrl->counter) {
923 fsl_lbc_ctrl_dev->nand = NULL;
924 kfree(elbc_fcm_ctrl);
925 }
926 mutex_unlock(&fsl_elbc_nand_mutex);
927
928 return 0;
929
930}
931
932static const struct of_device_id fsl_elbc_nand_match[] = {
933 { .compatible = "fsl,elbc-fcm-nand", },
934 {}
935};
936
937static struct platform_driver fsl_elbc_nand_driver = {
938 .driver = {
939 .name = "fsl,elbc-fcm-nand",
940 .owner = THIS_MODULE,
941 .of_match_table = fsl_elbc_nand_match,
942 },
943 .probe = fsl_elbc_nand_probe,
944 .remove = fsl_elbc_nand_remove,
945};
946
947module_platform_driver(fsl_elbc_nand_driver);
948
949MODULE_LICENSE("GPL");
950MODULE_AUTHOR("Freescale");
951MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
952