linux/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
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   1/*
   2 * Freescale GPMI NAND Flash Driver
   3 *
   4 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   5 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 */
  17#ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
  18#define __DRIVERS_MTD_NAND_GPMI_NAND_H
  19
  20#include <linux/mtd/nand.h>
  21#include <linux/platform_device.h>
  22#include <linux/dma-mapping.h>
  23#include <linux/dmaengine.h>
  24
  25#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
  26struct resources {
  27        void __iomem  *gpmi_regs;
  28        void __iomem  *bch_regs;
  29        unsigned int  dma_low_channel;
  30        unsigned int  dma_high_channel;
  31        struct clk    *clock[GPMI_CLK_MAX];
  32};
  33
  34/**
  35 * struct bch_geometry - BCH geometry description.
  36 * @gf_len:                   The length of Galois Field. (e.g., 13 or 14)
  37 * @ecc_strength:             A number that describes the strength of the ECC
  38 *                            algorithm.
  39 * @page_size:                The size, in bytes, of a physical page, including
  40 *                            both data and OOB.
  41 * @metadata_size:            The size, in bytes, of the metadata.
  42 * @ecc_chunk_size:           The size, in bytes, of a single ECC chunk. Note
  43 *                            the first chunk in the page includes both data and
  44 *                            metadata, so it's a bit larger than this value.
  45 * @ecc_chunk_count:          The number of ECC chunks in the page,
  46 * @payload_size:             The size, in bytes, of the payload buffer.
  47 * @auxiliary_size:           The size, in bytes, of the auxiliary buffer.
  48 * @auxiliary_status_offset:  The offset into the auxiliary buffer at which
  49 *                            the ECC status appears.
  50 * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
  51 *                            which the underlying physical block mark appears.
  52 * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
  53 *                            which the underlying physical block mark appears.
  54 */
  55struct bch_geometry {
  56        unsigned int  gf_len;
  57        unsigned int  ecc_strength;
  58        unsigned int  page_size;
  59        unsigned int  metadata_size;
  60        unsigned int  ecc_chunk_size;
  61        unsigned int  ecc_chunk_count;
  62        unsigned int  payload_size;
  63        unsigned int  auxiliary_size;
  64        unsigned int  auxiliary_status_offset;
  65        unsigned int  block_mark_byte_offset;
  66        unsigned int  block_mark_bit_offset;
  67};
  68
  69/**
  70 * struct boot_rom_geometry - Boot ROM geometry description.
  71 * @stride_size_in_pages:        The size of a boot block stride, in pages.
  72 * @search_area_stride_exponent: The logarithm to base 2 of the size of a
  73 *                               search area in boot block strides.
  74 */
  75struct boot_rom_geometry {
  76        unsigned int  stride_size_in_pages;
  77        unsigned int  search_area_stride_exponent;
  78};
  79
  80/* DMA operations types */
  81enum dma_ops_type {
  82        DMA_FOR_COMMAND = 1,
  83        DMA_FOR_READ_DATA,
  84        DMA_FOR_WRITE_DATA,
  85        DMA_FOR_READ_ECC_PAGE,
  86        DMA_FOR_WRITE_ECC_PAGE
  87};
  88
  89/**
  90 * struct nand_timing - Fundamental timing attributes for NAND.
  91 * @data_setup_in_ns:         The data setup time, in nanoseconds. Usually the
  92 *                            maximum of tDS and tWP. A negative value
  93 *                            indicates this characteristic isn't known.
  94 * @data_hold_in_ns:          The data hold time, in nanoseconds. Usually the
  95 *                            maximum of tDH, tWH and tREH. A negative value
  96 *                            indicates this characteristic isn't known.
  97 * @address_setup_in_ns:      The address setup time, in nanoseconds. Usually
  98 *                            the maximum of tCLS, tCS and tALS. A negative
  99 *                            value indicates this characteristic isn't known.
 100 * @gpmi_sample_delay_in_ns:  A GPMI-specific timing parameter. A negative value
 101 *                            indicates this characteristic isn't known.
 102 * @tREA_in_ns:               tREA, in nanoseconds, from the data sheet. A
 103 *                            negative value indicates this characteristic isn't
 104 *                            known.
 105 * @tRLOH_in_ns:              tRLOH, in nanoseconds, from the data sheet. A
 106 *                            negative value indicates this characteristic isn't
 107 *                            known.
 108 * @tRHOH_in_ns:              tRHOH, in nanoseconds, from the data sheet. A
 109 *                            negative value indicates this characteristic isn't
 110 *                            known.
 111 */
 112struct nand_timing {
 113        int8_t  data_setup_in_ns;
 114        int8_t  data_hold_in_ns;
 115        int8_t  address_setup_in_ns;
 116        int8_t  gpmi_sample_delay_in_ns;
 117        int8_t  tREA_in_ns;
 118        int8_t  tRLOH_in_ns;
 119        int8_t  tRHOH_in_ns;
 120};
 121
 122struct gpmi_nand_data {
 123        /* flags */
 124#define GPMI_ASYNC_EDO_ENABLED  (1 << 0)
 125#define GPMI_TIMING_INIT_OK     (1 << 1)
 126        int                     flags;
 127
 128        /* System Interface */
 129        struct device           *dev;
 130        struct platform_device  *pdev;
 131
 132        /* Resources */
 133        struct resources        resources;
 134
 135        /* Flash Hardware */
 136        struct nand_timing      timing;
 137        int                     timing_mode;
 138
 139        /* BCH */
 140        struct bch_geometry     bch_geometry;
 141        struct completion       bch_done;
 142
 143        /* NAND Boot issue */
 144        bool                    swap_block_mark;
 145        struct boot_rom_geometry rom_geometry;
 146
 147        /* MTD / NAND */
 148        struct nand_chip        nand;
 149        struct mtd_info         mtd;
 150
 151        /* General-use Variables */
 152        int                     current_chip;
 153        unsigned int            command_length;
 154
 155        /* passed from upper layer */
 156        uint8_t                 *upper_buf;
 157        int                     upper_len;
 158
 159        /* for DMA operations */
 160        bool                    direct_dma_map_ok;
 161
 162        struct scatterlist      cmd_sgl;
 163        char                    *cmd_buffer;
 164
 165        struct scatterlist      data_sgl;
 166        char                    *data_buffer_dma;
 167
 168        void                    *page_buffer_virt;
 169        dma_addr_t              page_buffer_phys;
 170        unsigned int            page_buffer_size;
 171
 172        void                    *payload_virt;
 173        dma_addr_t              payload_phys;
 174
 175        void                    *auxiliary_virt;
 176        dma_addr_t              auxiliary_phys;
 177
 178        /* DMA channels */
 179#define DMA_CHANS               8
 180        struct dma_chan         *dma_chans[DMA_CHANS];
 181        enum dma_ops_type       last_dma_type;
 182        enum dma_ops_type       dma_type;
 183        struct completion       dma_done;
 184
 185        /* private */
 186        void                    *private;
 187};
 188
 189/**
 190 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
 191 * @data_setup_in_cycles:      The data setup time, in cycles.
 192 * @data_hold_in_cycles:       The data hold time, in cycles.
 193 * @address_setup_in_cycles:   The address setup time, in cycles.
 194 * @device_busy_timeout:       The timeout waiting for NAND Ready/Busy,
 195 *                             this value is the number of cycles multiplied
 196 *                             by 4096.
 197 * @use_half_periods:          Indicates the clock is running slowly, so the
 198 *                             NFC DLL should use half-periods.
 199 * @sample_delay_factor:       The sample delay factor.
 200 * @wrn_dly_sel:               The delay on the GPMI write strobe.
 201 */
 202struct gpmi_nfc_hardware_timing {
 203        /* for HW_GPMI_TIMING0 */
 204        uint8_t  data_setup_in_cycles;
 205        uint8_t  data_hold_in_cycles;
 206        uint8_t  address_setup_in_cycles;
 207
 208        /* for HW_GPMI_TIMING1 */
 209        uint16_t device_busy_timeout;
 210#define GPMI_DEFAULT_BUSY_TIMEOUT       0x500 /* default busy timeout value.*/
 211
 212        /* for HW_GPMI_CTRL1 */
 213        bool     use_half_periods;
 214        uint8_t  sample_delay_factor;
 215        uint8_t  wrn_dly_sel;
 216};
 217
 218/**
 219 * struct timing_threshod - Timing threshold
 220 * @max_data_setup_cycles:       The maximum number of data setup cycles that
 221 *                               can be expressed in the hardware.
 222 * @internal_data_setup_in_ns:   The time, in ns, that the NFC hardware requires
 223 *                               for data read internal setup. In the Reference
 224 *                               Manual, see the chapter "High-Speed NAND
 225 *                               Timing" for more details.
 226 * @max_sample_delay_factor:     The maximum sample delay factor that can be
 227 *                               expressed in the hardware.
 228 * @max_dll_clock_period_in_ns:  The maximum period of the GPMI clock that the
 229 *                               sample delay DLL hardware can possibly work
 230 *                               with (the DLL is unusable with longer periods).
 231 *                               If the full-cycle period is greater than HALF
 232 *                               this value, the DLL must be configured to use
 233 *                               half-periods.
 234 * @max_dll_delay_in_ns:         The maximum amount of delay, in ns, that the
 235 *                               DLL can implement.
 236 * @clock_frequency_in_hz:       The clock frequency, in Hz, during the current
 237 *                               I/O transaction. If no I/O transaction is in
 238 *                               progress, this is the clock frequency during
 239 *                               the most recent I/O transaction.
 240 */
 241struct timing_threshod {
 242        const unsigned int      max_chip_count;
 243        const unsigned int      max_data_setup_cycles;
 244        const unsigned int      internal_data_setup_in_ns;
 245        const unsigned int      max_sample_delay_factor;
 246        const unsigned int      max_dll_clock_period_in_ns;
 247        const unsigned int      max_dll_delay_in_ns;
 248        unsigned long           clock_frequency_in_hz;
 249
 250};
 251
 252/* Common Services */
 253extern int common_nfc_set_geometry(struct gpmi_nand_data *);
 254extern struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
 255extern void prepare_data_dma(struct gpmi_nand_data *,
 256                                enum dma_data_direction dr);
 257extern int start_dma_without_bch_irq(struct gpmi_nand_data *,
 258                                struct dma_async_tx_descriptor *);
 259extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
 260                                struct dma_async_tx_descriptor *);
 261
 262/* GPMI-NAND helper function library */
 263extern int gpmi_init(struct gpmi_nand_data *);
 264extern int gpmi_extra_init(struct gpmi_nand_data *);
 265extern void gpmi_clear_bch(struct gpmi_nand_data *);
 266extern void gpmi_dump_info(struct gpmi_nand_data *);
 267extern int bch_set_geometry(struct gpmi_nand_data *);
 268extern int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
 269extern int gpmi_send_command(struct gpmi_nand_data *);
 270extern void gpmi_begin(struct gpmi_nand_data *);
 271extern void gpmi_end(struct gpmi_nand_data *);
 272extern int gpmi_read_data(struct gpmi_nand_data *);
 273extern int gpmi_send_data(struct gpmi_nand_data *);
 274extern int gpmi_send_page(struct gpmi_nand_data *,
 275                        dma_addr_t payload, dma_addr_t auxiliary);
 276extern int gpmi_read_page(struct gpmi_nand_data *,
 277                        dma_addr_t payload, dma_addr_t auxiliary);
 278
 279/* BCH : Status Block Completion Codes */
 280#define STATUS_GOOD             0x00
 281#define STATUS_ERASED           0xff
 282#define STATUS_UNCORRECTABLE    0xfe
 283
 284/* BCH's bit correction capability. */
 285#define MXS_ECC_STRENGTH_MAX    20      /* mx23 and mx28 */
 286#define MX6_ECC_STRENGTH_MAX    40
 287
 288/* Use the platform_id to distinguish different Archs. */
 289#define IS_MX23                 0x0
 290#define IS_MX28                 0x1
 291#define IS_MX6Q                 0x2
 292#define GPMI_IS_MX23(x)         ((x)->pdev->id_entry->driver_data == IS_MX23)
 293#define GPMI_IS_MX28(x)         ((x)->pdev->id_entry->driver_data == IS_MX28)
 294#define GPMI_IS_MX6Q(x)         ((x)->pdev->id_entry->driver_data == IS_MX6Q)
 295#endif
 296
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.