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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <asm/io.h>
50#include "cxgb4_uld.h"
51
52#define T4FW_VERSION_MAJOR 0x01
53#define T4FW_VERSION_MINOR 0x09
54#define T4FW_VERSION_MICRO 0x17
55#define T4FW_VERSION_BUILD 0x00
56
57#define T5FW_VERSION_MAJOR 0x01
58#define T5FW_VERSION_MINOR 0x09
59#define T5FW_VERSION_MICRO 0x17
60#define T5FW_VERSION_BUILD 0x00
61
62#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
63
64enum {
65 MAX_NPORTS = 4,
66 SERNUM_LEN = 24,
67 EC_LEN = 16,
68 ID_LEN = 16,
69};
70
71enum {
72 MEM_EDC0,
73 MEM_EDC1,
74 MEM_MC,
75 MEM_MC0 = MEM_MC,
76 MEM_MC1
77};
78
79enum {
80 MEMWIN0_APERTURE = 2048,
81 MEMWIN0_BASE = 0x1b800,
82 MEMWIN1_APERTURE = 32768,
83 MEMWIN1_BASE = 0x28000,
84 MEMWIN1_BASE_T5 = 0x52000,
85 MEMWIN2_APERTURE = 65536,
86 MEMWIN2_BASE = 0x30000,
87 MEMWIN2_BASE_T5 = 0x54000,
88};
89
90enum dev_master {
91 MASTER_CANT,
92 MASTER_MAY,
93 MASTER_MUST
94};
95
96enum dev_state {
97 DEV_STATE_UNINIT,
98 DEV_STATE_INIT,
99 DEV_STATE_ERR
100};
101
102enum {
103 PAUSE_RX = 1 << 0,
104 PAUSE_TX = 1 << 1,
105 PAUSE_AUTONEG = 1 << 2
106};
107
108struct port_stats {
109 u64 tx_octets;
110 u64 tx_frames;
111 u64 tx_bcast_frames;
112 u64 tx_mcast_frames;
113 u64 tx_ucast_frames;
114 u64 tx_error_frames;
115
116 u64 tx_frames_64;
117 u64 tx_frames_65_127;
118 u64 tx_frames_128_255;
119 u64 tx_frames_256_511;
120 u64 tx_frames_512_1023;
121 u64 tx_frames_1024_1518;
122 u64 tx_frames_1519_max;
123
124 u64 tx_drop;
125 u64 tx_pause;
126 u64 tx_ppp0;
127 u64 tx_ppp1;
128 u64 tx_ppp2;
129 u64 tx_ppp3;
130 u64 tx_ppp4;
131 u64 tx_ppp5;
132 u64 tx_ppp6;
133 u64 tx_ppp7;
134
135 u64 rx_octets;
136 u64 rx_frames;
137 u64 rx_bcast_frames;
138 u64 rx_mcast_frames;
139 u64 rx_ucast_frames;
140 u64 rx_too_long;
141 u64 rx_jabber;
142 u64 rx_fcs_err;
143 u64 rx_len_err;
144 u64 rx_symbol_err;
145 u64 rx_runt;
146
147 u64 rx_frames_64;
148 u64 rx_frames_65_127;
149 u64 rx_frames_128_255;
150 u64 rx_frames_256_511;
151 u64 rx_frames_512_1023;
152 u64 rx_frames_1024_1518;
153 u64 rx_frames_1519_max;
154
155 u64 rx_pause;
156 u64 rx_ppp0;
157 u64 rx_ppp1;
158 u64 rx_ppp2;
159 u64 rx_ppp3;
160 u64 rx_ppp4;
161 u64 rx_ppp5;
162 u64 rx_ppp6;
163 u64 rx_ppp7;
164
165 u64 rx_ovflow0;
166 u64 rx_ovflow1;
167 u64 rx_ovflow2;
168 u64 rx_ovflow3;
169 u64 rx_trunc0;
170 u64 rx_trunc1;
171 u64 rx_trunc2;
172 u64 rx_trunc3;
173};
174
175struct lb_port_stats {
176 u64 octets;
177 u64 frames;
178 u64 bcast_frames;
179 u64 mcast_frames;
180 u64 ucast_frames;
181 u64 error_frames;
182
183 u64 frames_64;
184 u64 frames_65_127;
185 u64 frames_128_255;
186 u64 frames_256_511;
187 u64 frames_512_1023;
188 u64 frames_1024_1518;
189 u64 frames_1519_max;
190
191 u64 drop;
192
193 u64 ovflow0;
194 u64 ovflow1;
195 u64 ovflow2;
196 u64 ovflow3;
197 u64 trunc0;
198 u64 trunc1;
199 u64 trunc2;
200 u64 trunc3;
201};
202
203struct tp_tcp_stats {
204 u32 tcpOutRsts;
205 u64 tcpInSegs;
206 u64 tcpOutSegs;
207 u64 tcpRetransSegs;
208};
209
210struct tp_err_stats {
211 u32 macInErrs[4];
212 u32 hdrInErrs[4];
213 u32 tcpInErrs[4];
214 u32 tnlCongDrops[4];
215 u32 ofldChanDrops[4];
216 u32 tnlTxDrops[4];
217 u32 ofldVlanDrops[4];
218 u32 tcp6InErrs[4];
219 u32 ofldNoNeigh;
220 u32 ofldCongDefer;
221};
222
223struct tp_params {
224 unsigned int ntxchan;
225 unsigned int tre;
226 unsigned short tx_modq_map;
227
228
229 uint32_t dack_re;
230 unsigned short tx_modq[NCHAN];
231
232 u32 vlan_pri_map;
233 u32 ingress_config;
234
235
236
237
238
239
240
241
242
243
244
245
246 int vlan_shift;
247 int vnic_shift;
248 int port_shift;
249 int protocol_shift;
250};
251
252struct vpd_params {
253 unsigned int cclk;
254 u8 ec[EC_LEN + 1];
255 u8 sn[SERNUM_LEN + 1];
256 u8 id[ID_LEN + 1];
257};
258
259struct pci_params {
260 unsigned char speed;
261 unsigned char width;
262};
263
264#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
265#define CHELSIO_CHIP_FPGA 0x100
266#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
267#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
268
269#define CHELSIO_T4 0x4
270#define CHELSIO_T5 0x5
271
272enum chip_type {
273 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
274 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
275 T4_FIRST_REV = T4_A1,
276 T4_LAST_REV = T4_A2,
277
278 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
279 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
280 T5_FIRST_REV = T5_A0,
281 T5_LAST_REV = T5_A1,
282};
283
284struct adapter_params {
285 struct tp_params tp;
286 struct vpd_params vpd;
287 struct pci_params pci;
288
289 unsigned int sf_size;
290 unsigned int sf_nsec;
291 unsigned int sf_fw_start;
292
293 unsigned int fw_vers;
294 unsigned int tp_vers;
295 u8 api_vers[7];
296
297 unsigned short mtus[NMTUS];
298 unsigned short a_wnd[NCCTRL_WIN];
299 unsigned short b_wnd[NCCTRL_WIN];
300
301 unsigned char nports;
302 unsigned char portvec;
303 enum chip_type chip;
304 unsigned char offload;
305
306 unsigned char bypass;
307
308 unsigned int ofldq_wr_cred;
309};
310
311#include "t4fw_api.h"
312
313#define FW_VERSION(chip) ( \
314 FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
315 FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
316 FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
317 FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
318#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
319
320struct fw_info {
321 u8 chip;
322 char *fs_name;
323 char *fw_mod_name;
324 struct fw_hdr fw_hdr;
325};
326
327
328struct trace_params {
329 u32 data[TRACE_LEN / 4];
330 u32 mask[TRACE_LEN / 4];
331 unsigned short snap_len;
332 unsigned short min_len;
333 unsigned char skip_ofst;
334 unsigned char skip_len;
335 unsigned char invert;
336 unsigned char port;
337};
338
339struct link_config {
340 unsigned short supported;
341 unsigned short advertising;
342 unsigned short requested_speed;
343 unsigned short speed;
344 unsigned char requested_fc;
345 unsigned char fc;
346 unsigned char autoneg;
347 unsigned char link_ok;
348};
349
350#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
351
352enum {
353 MAX_ETH_QSETS = 32,
354 MAX_OFLD_QSETS = 16,
355 MAX_CTRL_QUEUES = NCHAN,
356 MAX_RDMA_QUEUES = NCHAN,
357};
358
359enum {
360 MAX_EGRQ = 128,
361 MAX_INGQ = 64
362};
363
364struct adapter;
365struct sge_rspq;
366
367struct port_info {
368 struct adapter *adapter;
369 u16 viid;
370 s16 xact_addr_filt;
371 u16 rss_size;
372 s8 mdio_addr;
373 u8 port_type;
374 u8 mod_type;
375 u8 port_id;
376 u8 tx_chan;
377 u8 lport;
378 u8 nqsets;
379 u8 first_qset;
380 u8 rss_mode;
381 struct link_config link_cfg;
382 u16 *rss;
383};
384
385struct dentry;
386struct work_struct;
387
388enum {
389 FULL_INIT_DONE = (1 << 0),
390 DEV_ENABLED = (1 << 1),
391 USING_MSI = (1 << 2),
392 USING_MSIX = (1 << 3),
393 FW_OK = (1 << 4),
394 RSS_TNLALLLOOKUP = (1 << 5),
395 USING_SOFT_PARAMS = (1 << 6),
396 MASTER_PF = (1 << 7),
397 FW_OFLD_CONN = (1 << 9),
398};
399
400struct rx_sw_desc;
401
402struct sge_fl {
403 unsigned int avail;
404 unsigned int pend_cred;
405 unsigned int cidx;
406 unsigned int pidx;
407 unsigned long alloc_failed;
408 unsigned long large_alloc_failed;
409 unsigned long starving;
410
411 unsigned int cntxt_id;
412 unsigned int size;
413 struct rx_sw_desc *sdesc;
414 __be64 *desc;
415 dma_addr_t addr;
416};
417
418
419struct pkt_gl {
420 struct page_frag frags[MAX_SKB_FRAGS];
421 void *va;
422 unsigned int nfrags;
423 unsigned int tot_len;
424};
425
426typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
427 const struct pkt_gl *gl);
428
429struct sge_rspq {
430 struct napi_struct napi;
431 const __be64 *cur_desc;
432 unsigned int cidx;
433 u8 gen;
434 u8 intr_params;
435 u8 next_intr_params;
436 u8 pktcnt_idx;
437 u8 uld;
438 u8 idx;
439 int offset;
440 u16 cntxt_id;
441 u16 abs_id;
442 __be64 *desc;
443 dma_addr_t phys_addr;
444 unsigned int iqe_len;
445 unsigned int size;
446 struct adapter *adap;
447 struct net_device *netdev;
448 rspq_handler_t handler;
449};
450
451struct sge_eth_stats {
452 unsigned long pkts;
453 unsigned long lro_pkts;
454 unsigned long lro_merged;
455 unsigned long rx_cso;
456 unsigned long vlan_ex;
457 unsigned long rx_drops;
458};
459
460struct sge_eth_rxq {
461 struct sge_rspq rspq;
462 struct sge_fl fl;
463 struct sge_eth_stats stats;
464} ____cacheline_aligned_in_smp;
465
466struct sge_ofld_stats {
467 unsigned long pkts;
468 unsigned long imm;
469 unsigned long an;
470 unsigned long nomem;
471};
472
473struct sge_ofld_rxq {
474 struct sge_rspq rspq;
475 struct sge_fl fl;
476 struct sge_ofld_stats stats;
477} ____cacheline_aligned_in_smp;
478
479struct tx_desc {
480 __be64 flit[8];
481};
482
483struct tx_sw_desc;
484
485struct sge_txq {
486 unsigned int in_use;
487 unsigned int size;
488 unsigned int cidx;
489 unsigned int pidx;
490 unsigned long stops;
491 unsigned long restarts;
492 unsigned int cntxt_id;
493 struct tx_desc *desc;
494 struct tx_sw_desc *sdesc;
495 struct sge_qstat *stat;
496 dma_addr_t phys_addr;
497 spinlock_t db_lock;
498 int db_disabled;
499 unsigned short db_pidx;
500 u64 udb;
501};
502
503struct sge_eth_txq {
504 struct sge_txq q;
505 struct netdev_queue *txq;
506 unsigned long tso;
507 unsigned long tx_cso;
508 unsigned long vlan_ins;
509 unsigned long mapping_err;
510} ____cacheline_aligned_in_smp;
511
512struct sge_ofld_txq {
513 struct sge_txq q;
514 struct adapter *adap;
515 struct sk_buff_head sendq;
516 struct tasklet_struct qresume_tsk;
517 u8 full;
518 unsigned long mapping_err;
519} ____cacheline_aligned_in_smp;
520
521struct sge_ctrl_txq {
522 struct sge_txq q;
523 struct adapter *adap;
524 struct sk_buff_head sendq;
525 struct tasklet_struct qresume_tsk;
526 u8 full;
527} ____cacheline_aligned_in_smp;
528
529struct sge {
530 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
531 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
532 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
533
534 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
535 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
536 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
537 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
538
539 struct sge_rspq intrq ____cacheline_aligned_in_smp;
540 spinlock_t intrq_lock;
541
542 u16 max_ethqsets;
543 u16 ethqsets;
544 u16 ethtxq_rover;
545 u16 ofldqsets;
546 u16 rdmaqs;
547 u16 ofld_rxq[MAX_OFLD_QSETS];
548 u16 rdma_rxq[NCHAN];
549 u16 timer_val[SGE_NTIMERS];
550 u8 counter_val[SGE_NCOUNTERS];
551 u32 fl_pg_order;
552 u32 stat_len;
553 u32 pktshift;
554 u32 fl_align;
555 u32 fl_starve_thres;
556 unsigned int starve_thres;
557 u8 idma_state[2];
558 unsigned int egr_start;
559 unsigned int ingr_start;
560 void *egr_map[MAX_EGRQ];
561 struct sge_rspq *ingr_map[MAX_INGQ];
562 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
563 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
564 struct timer_list rx_timer;
565 struct timer_list tx_timer;
566};
567
568#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
569#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
570#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
571
572struct l2t_data;
573
574#ifdef CONFIG_PCI_IOV
575
576
577
578
579
580#define NUM_OF_PF_WITH_SRIOV 4
581
582#endif
583
584struct adapter {
585 void __iomem *regs;
586 void __iomem *bar2;
587 struct pci_dev *pdev;
588 struct device *pdev_dev;
589 unsigned int mbox;
590 unsigned int fn;
591 unsigned int flags;
592 enum chip_type chip;
593
594 int msg_enable;
595
596 struct adapter_params params;
597 struct cxgb4_virt_res vres;
598 unsigned int swintr;
599
600 unsigned int wol;
601
602 struct {
603 unsigned short vec;
604 char desc[IFNAMSIZ + 10];
605 } msix_info[MAX_INGQ + 1];
606
607 struct sge sge;
608
609 struct net_device *port[MAX_NPORTS];
610 u8 chan_map[NCHAN];
611
612 u32 filter_mode;
613 unsigned int l2t_start;
614 unsigned int l2t_end;
615 struct l2t_data *l2t;
616 void *uld_handle[CXGB4_ULD_MAX];
617 struct list_head list_node;
618 struct list_head rcu_node;
619
620 struct tid_info tids;
621 void **tid_release_head;
622 spinlock_t tid_release_lock;
623 struct work_struct tid_release_task;
624 struct work_struct db_full_task;
625 struct work_struct db_drop_task;
626 bool tid_release_task_busy;
627
628 struct dentry *debugfs_root;
629
630 spinlock_t stats_lock;
631};
632
633
634
635#define ETHTYPE_BITWIDTH 16
636#define FRAG_BITWIDTH 1
637#define MACIDX_BITWIDTH 9
638#define FCOE_BITWIDTH 1
639#define IPORT_BITWIDTH 3
640#define MATCHTYPE_BITWIDTH 3
641#define PROTO_BITWIDTH 8
642#define TOS_BITWIDTH 8
643#define PF_BITWIDTH 8
644#define VF_BITWIDTH 8
645#define IVLAN_BITWIDTH 16
646#define OVLAN_BITWIDTH 16
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665struct ch_filter_tuple {
666
667
668
669
670
671
672 uint32_t ethtype:ETHTYPE_BITWIDTH;
673 uint32_t frag:FRAG_BITWIDTH;
674 uint32_t ivlan_vld:1;
675 uint32_t ovlan_vld:1;
676 uint32_t pfvf_vld:1;
677 uint32_t macidx:MACIDX_BITWIDTH;
678 uint32_t fcoe:FCOE_BITWIDTH;
679 uint32_t iport:IPORT_BITWIDTH;
680 uint32_t matchtype:MATCHTYPE_BITWIDTH;
681 uint32_t proto:PROTO_BITWIDTH;
682 uint32_t tos:TOS_BITWIDTH;
683 uint32_t pf:PF_BITWIDTH;
684 uint32_t vf:VF_BITWIDTH;
685 uint32_t ivlan:IVLAN_BITWIDTH;
686 uint32_t ovlan:OVLAN_BITWIDTH;
687
688
689
690
691 uint8_t lip[16];
692 uint8_t fip[16];
693 uint16_t lport;
694 uint16_t fport;
695};
696
697
698
699struct ch_filter_specification {
700
701
702 uint32_t hitcnts:1;
703 uint32_t prio:1;
704
705
706
707
708 uint32_t type:1;
709
710
711
712
713
714 uint32_t action:2;
715
716 uint32_t rpttid:1;
717
718 uint32_t dirsteer:1;
719 uint32_t iq:10;
720
721 uint32_t maskhash:1;
722 uint32_t dirsteerhash:1;
723
724
725
726
727
728
729 uint32_t eport:2;
730 uint32_t newdmac:1;
731 uint32_t newsmac:1;
732 uint32_t newvlan:2;
733 uint8_t dmac[ETH_ALEN];
734 uint8_t smac[ETH_ALEN];
735 uint16_t vlan;
736
737
738
739 struct ch_filter_tuple val;
740 struct ch_filter_tuple mask;
741};
742
743enum {
744 FILTER_PASS = 0,
745 FILTER_DROP,
746 FILTER_SWITCH
747};
748
749enum {
750 VLAN_NOCHANGE = 0,
751 VLAN_REMOVE,
752 VLAN_INSERT,
753 VLAN_REWRITE
754};
755
756static inline int is_t5(enum chip_type chip)
757{
758 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
759}
760
761static inline int is_t4(enum chip_type chip)
762{
763 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
764}
765
766static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
767{
768 return readl(adap->regs + reg_addr);
769}
770
771static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
772{
773 writel(val, adap->regs + reg_addr);
774}
775
776#ifndef readq
777static inline u64 readq(const volatile void __iomem *addr)
778{
779 return readl(addr) + ((u64)readl(addr + 4) << 32);
780}
781
782static inline void writeq(u64 val, volatile void __iomem *addr)
783{
784 writel(val, addr);
785 writel(val >> 32, addr + 4);
786}
787#endif
788
789static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
790{
791 return readq(adap->regs + reg_addr);
792}
793
794static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
795{
796 writeq(val, adap->regs + reg_addr);
797}
798
799
800
801
802
803
804
805static inline struct port_info *netdev2pinfo(const struct net_device *dev)
806{
807 return netdev_priv(dev);
808}
809
810
811
812
813
814
815
816
817static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
818{
819 return netdev_priv(adap->port[idx]);
820}
821
822
823
824
825
826
827
828static inline struct adapter *netdev2adap(const struct net_device *dev)
829{
830 return netdev2pinfo(dev)->adapter;
831}
832
833void t4_os_portmod_changed(const struct adapter *adap, int port_id);
834void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
835
836void *t4_alloc_mem(size_t size);
837
838void t4_free_sge_resources(struct adapter *adap);
839irq_handler_t t4_intr_handler(struct adapter *adap);
840netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
841int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
842 const struct pkt_gl *gl);
843int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
844int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
845int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
846 struct net_device *dev, int intr_idx,
847 struct sge_fl *fl, rspq_handler_t hnd);
848int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
849 struct net_device *dev, struct netdev_queue *netdevq,
850 unsigned int iqid);
851int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
852 struct net_device *dev, unsigned int iqid,
853 unsigned int cmplqid);
854int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
855 struct net_device *dev, unsigned int iqid);
856irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
857int t4_sge_init(struct adapter *adap);
858void t4_sge_start(struct adapter *adap);
859void t4_sge_stop(struct adapter *adap);
860extern int dbfifo_int_thresh;
861
862#define for_each_port(adapter, iter) \
863 for (iter = 0; iter < (adapter)->params.nports; ++iter)
864
865static inline int is_bypass(struct adapter *adap)
866{
867 return adap->params.bypass;
868}
869
870static inline int is_bypass_device(int device)
871{
872
873 switch (device) {
874 case 0x440b:
875 case 0x440c:
876 return 1;
877 default:
878 return 0;
879 }
880}
881
882static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
883{
884 return adap->params.vpd.cclk / 1000;
885}
886
887static inline unsigned int us_to_core_ticks(const struct adapter *adap,
888 unsigned int us)
889{
890 return (us * adap->params.vpd.cclk) / 1000;
891}
892
893static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
894 unsigned int ticks)
895{
896
897 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
898 adapter->params.vpd.cclk);
899}
900
901void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
902 u32 val);
903
904int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
905 void *rpl, bool sleep_ok);
906
907static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
908 int size, void *rpl)
909{
910 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
911}
912
913static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
914 int size, void *rpl)
915{
916 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
917}
918
919void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
920 unsigned int data_reg, const u32 *vals,
921 unsigned int nregs, unsigned int start_idx);
922void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
923 unsigned int data_reg, u32 *vals, unsigned int nregs,
924 unsigned int start_idx);
925
926struct fw_filter_wr;
927
928void t4_intr_enable(struct adapter *adapter);
929void t4_intr_disable(struct adapter *adapter);
930int t4_slow_intr_handler(struct adapter *adapter);
931
932int t4_wait_dev_ready(struct adapter *adap);
933int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
934 struct link_config *lc);
935int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
936int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
937 __be32 *buf);
938int t4_seeprom_wp(struct adapter *adapter, bool enable);
939int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
940int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
941unsigned int t4_flash_cfg_addr(struct adapter *adapter);
942int t4_get_fw_version(struct adapter *adapter, u32 *vers);
943int t4_get_tp_version(struct adapter *adapter, u32 *vers);
944int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
945 const u8 *fw_data, unsigned int fw_size,
946 struct fw_hdr *card_fw, enum dev_state state, int *reset);
947int t4_prep_adapter(struct adapter *adapter);
948int t4_init_tp_params(struct adapter *adap);
949int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
950int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
951void t4_fatal_err(struct adapter *adapter);
952int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
953 int start, int n, const u16 *rspq, unsigned int nrspq);
954int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
955 unsigned int flags);
956int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
957 u64 *parity);
958int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
959 u64 *parity);
960
961void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
962void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
963void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
964 unsigned int mask, unsigned int val);
965void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
966 struct tp_tcp_stats *v6);
967void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
968 const unsigned short *alpha, const unsigned short *beta);
969
970void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
971
972void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
973 const u8 *addr);
974int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
975 u64 mask0, u64 mask1, unsigned int crc, bool enable);
976
977int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
978 enum dev_master master, enum dev_state *state);
979int t4_fw_bye(struct adapter *adap, unsigned int mbox);
980int t4_early_init(struct adapter *adap, unsigned int mbox);
981int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
982int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
983 unsigned int cache_line_size);
984int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
985int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
986 unsigned int vf, unsigned int nparams, const u32 *params,
987 u32 *val);
988int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
989 unsigned int vf, unsigned int nparams, const u32 *params,
990 const u32 *val);
991int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
992 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
993 unsigned int rxqi, unsigned int rxq, unsigned int tc,
994 unsigned int vi, unsigned int cmask, unsigned int pmask,
995 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
996int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
997 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
998 unsigned int *rss_size);
999int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1000 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1001 bool sleep_ok);
1002int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1003 unsigned int viid, bool free, unsigned int naddr,
1004 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1005int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1006 int idx, const u8 *addr, bool persist, bool add_smt);
1007int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1008 bool ucast, u64 vec, bool sleep_ok);
1009int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1010 bool rx_en, bool tx_en);
1011int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1012 unsigned int nblinks);
1013int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1014 unsigned int mmd, unsigned int reg, u16 *valp);
1015int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1016 unsigned int mmd, unsigned int reg, u16 val);
1017int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1018 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1019 unsigned int fl0id, unsigned int fl1id);
1020int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1021 unsigned int vf, unsigned int eqid);
1022int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1023 unsigned int vf, unsigned int eqid);
1024int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1025 unsigned int vf, unsigned int eqid);
1026int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1027void t4_db_full(struct adapter *adapter);
1028void t4_db_dropped(struct adapter *adapter);
1029int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
1030int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1031 u32 addr, u32 val);
1032#endif
1033