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34#include <linux/gfp.h>
35#include <linux/export.h>
36#include <linux/mlx5/cmd.h>
37#include <linux/mlx5/qp.h>
38#include <linux/mlx5/driver.h>
39
40#include "mlx5_core.h"
41
42void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type)
43{
44 struct mlx5_qp_table *table = &dev->priv.qp_table;
45 struct mlx5_core_qp *qp;
46
47 spin_lock(&table->lock);
48
49 qp = radix_tree_lookup(&table->tree, qpn);
50 if (qp)
51 atomic_inc(&qp->refcount);
52
53 spin_unlock(&table->lock);
54
55 if (!qp) {
56 mlx5_core_warn(dev, "Async event for bogus QP 0x%x\n", qpn);
57 return;
58 }
59
60 qp->event(qp, event_type);
61
62 if (atomic_dec_and_test(&qp->refcount))
63 complete(&qp->free);
64}
65
66int mlx5_core_create_qp(struct mlx5_core_dev *dev,
67 struct mlx5_core_qp *qp,
68 struct mlx5_create_qp_mbox_in *in,
69 int inlen)
70{
71 struct mlx5_qp_table *table = &dev->priv.qp_table;
72 struct mlx5_create_qp_mbox_out out;
73 struct mlx5_destroy_qp_mbox_in din;
74 struct mlx5_destroy_qp_mbox_out dout;
75 int err;
76
77 memset(&out, 0, sizeof(out));
78 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_QP);
79
80 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
81 if (err) {
82 mlx5_core_warn(dev, "ret %d", err);
83 return err;
84 }
85
86 if (out.hdr.status) {
87 mlx5_core_warn(dev, "current num of QPs 0x%x\n",
88 atomic_read(&dev->num_qps));
89 return mlx5_cmd_status_to_err(&out.hdr);
90 }
91
92 qp->qpn = be32_to_cpu(out.qpn) & 0xffffff;
93 mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn);
94
95 spin_lock_irq(&table->lock);
96 err = radix_tree_insert(&table->tree, qp->qpn, qp);
97 spin_unlock_irq(&table->lock);
98 if (err) {
99 mlx5_core_warn(dev, "err %d", err);
100 goto err_cmd;
101 }
102
103 err = mlx5_debug_qp_add(dev, qp);
104 if (err)
105 mlx5_core_dbg(dev, "failed adding QP 0x%x to debug file system\n",
106 qp->qpn);
107
108 qp->pid = current->pid;
109 atomic_set(&qp->refcount, 1);
110 atomic_inc(&dev->num_qps);
111 init_completion(&qp->free);
112
113 return 0;
114
115err_cmd:
116 memset(&din, 0, sizeof(din));
117 memset(&dout, 0, sizeof(dout));
118 din.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
119 din.qpn = cpu_to_be32(qp->qpn);
120 mlx5_cmd_exec(dev, &din, sizeof(din), &out, sizeof(dout));
121
122 return err;
123}
124EXPORT_SYMBOL_GPL(mlx5_core_create_qp);
125
126int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
127 struct mlx5_core_qp *qp)
128{
129 struct mlx5_destroy_qp_mbox_in in;
130 struct mlx5_destroy_qp_mbox_out out;
131 struct mlx5_qp_table *table = &dev->priv.qp_table;
132 unsigned long flags;
133 int err;
134
135 mlx5_debug_qp_remove(dev, qp);
136
137 spin_lock_irqsave(&table->lock, flags);
138 radix_tree_delete(&table->tree, qp->qpn);
139 spin_unlock_irqrestore(&table->lock, flags);
140
141 if (atomic_dec_and_test(&qp->refcount))
142 complete(&qp->free);
143 wait_for_completion(&qp->free);
144
145 memset(&in, 0, sizeof(in));
146 memset(&out, 0, sizeof(out));
147 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_QP);
148 in.qpn = cpu_to_be32(qp->qpn);
149 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
150 if (err)
151 return err;
152
153 if (out.hdr.status)
154 return mlx5_cmd_status_to_err(&out.hdr);
155
156 atomic_dec(&dev->num_qps);
157 return 0;
158}
159EXPORT_SYMBOL_GPL(mlx5_core_destroy_qp);
160
161int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
162 enum mlx5_qp_state new_state,
163 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
164 struct mlx5_core_qp *qp)
165{
166 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
167 [MLX5_QP_STATE_RST] = {
168 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
169 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
170 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
171 },
172 [MLX5_QP_STATE_INIT] = {
173 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
174 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
175 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
176 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
177 },
178 [MLX5_QP_STATE_RTR] = {
179 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
180 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
181 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
182 },
183 [MLX5_QP_STATE_RTS] = {
184 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
185 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
186 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
187 [MLX5_QP_STATE_SQD] = MLX5_CMD_OP_RTS2SQD_QP,
188 },
189 [MLX5_QP_STATE_SQD] = {
190 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
191 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
192 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD2RTS_QP,
193 [MLX5_QP_STATE_SQD] = MLX5_CMD_OP_SQD2SQD_QP,
194 },
195 [MLX5_QP_STATE_SQER] = {
196 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
197 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
198 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
199 },
200 [MLX5_QP_STATE_ERR] = {
201 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
202 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
203 }
204 };
205
206 struct mlx5_modify_qp_mbox_out out;
207 int err = 0;
208 u16 op;
209
210 if (cur_state >= MLX5_QP_NUM_STATE || new_state >= MLX5_QP_NUM_STATE ||
211 !optab[cur_state][new_state])
212 return -EINVAL;
213
214 memset(&out, 0, sizeof(out));
215 op = optab[cur_state][new_state];
216 in->hdr.opcode = cpu_to_be16(op);
217 in->qpn = cpu_to_be32(qp->qpn);
218 err = mlx5_cmd_exec(dev, in, sizeof(*in), &out, sizeof(out));
219 if (err)
220 return err;
221
222 return mlx5_cmd_status_to_err(&out.hdr);
223}
224EXPORT_SYMBOL_GPL(mlx5_core_qp_modify);
225
226void mlx5_init_qp_table(struct mlx5_core_dev *dev)
227{
228 struct mlx5_qp_table *table = &dev->priv.qp_table;
229
230 spin_lock_init(&table->lock);
231 INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
232 mlx5_qp_debugfs_init(dev);
233}
234
235void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
236{
237 mlx5_qp_debugfs_cleanup(dev);
238}
239
240int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
241 struct mlx5_query_qp_mbox_out *out, int outlen)
242{
243 struct mlx5_query_qp_mbox_in in;
244 int err;
245
246 memset(&in, 0, sizeof(in));
247 memset(out, 0, outlen);
248 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_QP);
249 in.qpn = cpu_to_be32(qp->qpn);
250 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
251 if (err)
252 return err;
253
254 if (out->hdr.status)
255 return mlx5_cmd_status_to_err(&out->hdr);
256
257 return err;
258}
259EXPORT_SYMBOL_GPL(mlx5_core_qp_query);
260
261int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn)
262{
263 struct mlx5_alloc_xrcd_mbox_in in;
264 struct mlx5_alloc_xrcd_mbox_out out;
265 int err;
266
267 memset(&in, 0, sizeof(in));
268 memset(&out, 0, sizeof(out));
269 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_XRCD);
270 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
271 if (err)
272 return err;
273
274 if (out.hdr.status)
275 err = mlx5_cmd_status_to_err(&out.hdr);
276 else
277 *xrcdn = be32_to_cpu(out.xrcdn);
278
279 return err;
280}
281EXPORT_SYMBOL_GPL(mlx5_core_xrcd_alloc);
282
283int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn)
284{
285 struct mlx5_dealloc_xrcd_mbox_in in;
286 struct mlx5_dealloc_xrcd_mbox_out out;
287 int err;
288
289 memset(&in, 0, sizeof(in));
290 memset(&out, 0, sizeof(out));
291 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_XRCD);
292 in.xrcdn = cpu_to_be32(xrcdn);
293 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
294 if (err)
295 return err;
296
297 if (out.hdr.status)
298 err = mlx5_cmd_status_to_err(&out.hdr);
299
300 return err;
301}
302EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc);
303
