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24
25#define DRV_VERSION "1.39"
26static const char *version = "tc35815.c:v" DRV_VERSION "\n";
27#define MODNAME "tc35815"
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/fcntl.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/in.h>
36#include <linux/if_vlan.h>
37#include <linux/slab.h>
38#include <linux/string.h>
39#include <linux/spinlock.h>
40#include <linux/errno.h>
41#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/skbuff.h>
44#include <linux/delay.h>
45#include <linux/pci.h>
46#include <linux/phy.h>
47#include <linux/workqueue.h>
48#include <linux/platform_device.h>
49#include <linux/prefetch.h>
50#include <asm/io.h>
51#include <asm/byteorder.h>
52
53enum tc35815_chiptype {
54 TC35815CF = 0,
55 TC35815_NWU,
56 TC35815_TX4939,
57};
58
59
60static const struct {
61 const char *name;
62} chip_info[] = {
63 { "TOSHIBA TC35815CF 10/100BaseTX" },
64 { "TOSHIBA TC35815 with Wake on LAN" },
65 { "TOSHIBA TC35815/TX4939" },
66};
67
68static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
69 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
72 {0,}
73};
74MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
75
76
77static struct tc35815_options {
78 int speed;
79 int duplex;
80} options;
81
82
83
84
85struct tc35815_regs {
86 __u32 DMA_Ctl;
87 __u32 TxFrmPtr;
88 __u32 TxThrsh;
89 __u32 TxPollCtr;
90 __u32 BLFrmPtr;
91 __u32 RxFragSize;
92 __u32 Int_En;
93 __u32 FDA_Bas;
94 __u32 FDA_Lim;
95 __u32 Int_Src;
96 __u32 unused0[2];
97 __u32 PauseCnt;
98 __u32 RemPauCnt;
99 __u32 TxCtlFrmStat;
100 __u32 unused1;
101 __u32 MAC_Ctl;
102 __u32 CAM_Ctl;
103 __u32 Tx_Ctl;
104 __u32 Tx_Stat;
105 __u32 Rx_Ctl;
106 __u32 Rx_Stat;
107 __u32 MD_Data;
108 __u32 MD_CA;
109 __u32 CAM_Adr;
110 __u32 CAM_Data;
111 __u32 CAM_Ena;
112 __u32 PROM_Ctl;
113 __u32 PROM_Data;
114 __u32 Algn_Cnt;
115 __u32 CRC_Cnt;
116 __u32 Miss_Cnt;
117};
118
119
120
121
122
123#define DMA_RxAlign 0x00c00000
124#define DMA_RxAlign_1 0x00400000
125#define DMA_RxAlign_2 0x00800000
126#define DMA_RxAlign_3 0x00c00000
127#define DMA_M66EnStat 0x00080000
128#define DMA_IntMask 0x00040000
129#define DMA_SWIntReq 0x00020000
130#define DMA_TxWakeUp 0x00010000
131#define DMA_RxBigE 0x00008000
132#define DMA_TxBigE 0x00004000
133#define DMA_TestMode 0x00002000
134#define DMA_PowrMgmnt 0x00001000
135#define DMA_DmBurst_Mask 0x000001fc
136
137
138#define RxFrag_EnPack 0x00008000
139#define RxFrag_MinFragMask 0x00000ffc
140
141
142#define MAC_Link10 0x00008000
143#define MAC_EnMissRoll 0x00002000
144#define MAC_MissRoll 0x00000400
145#define MAC_Loop10 0x00000080
146#define MAC_Conn_Auto 0x00000000
147#define MAC_Conn_10M 0x00000020
148#define MAC_Conn_Mll 0x00000040
149#define MAC_MacLoop 0x00000010
150#define MAC_FullDup 0x00000008
151#define MAC_Reset 0x00000004
152#define MAC_HaltImm 0x00000002
153#define MAC_HaltReq 0x00000001
154
155
156#define PROM_Busy 0x00008000
157#define PROM_Read 0x00004000
158#define PROM_Write 0x00002000
159#define PROM_Erase 0x00006000
160
161
162#define PROM_Addr_Ena 0x00000030
163
164
165
166#define CAM_CompEn 0x00000010
167#define CAM_NegCAM 0x00000008
168
169#define CAM_BroadAcc 0x00000004
170#define CAM_GroupAcc 0x00000002
171#define CAM_StationAcc 0x00000001
172
173
174#define CAM_ENTRY_MAX 21
175#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1)
176#define CAM_Ena_Bit(index) (1 << (index))
177#define CAM_ENTRY_DESTINATION 0
178#define CAM_ENTRY_SOURCE 1
179#define CAM_ENTRY_MACCTL 20
180
181
182#define Tx_En 0x00000001
183#define Tx_TxHalt 0x00000002
184#define Tx_NoPad 0x00000004
185#define Tx_NoCRC 0x00000008
186#define Tx_FBack 0x00000010
187#define Tx_EnUnder 0x00000100
188#define Tx_EnExDefer 0x00000200
189#define Tx_EnLCarr 0x00000400
190#define Tx_EnExColl 0x00000800
191#define Tx_EnLateColl 0x00001000
192#define Tx_EnTxPar 0x00002000
193#define Tx_EnComp 0x00004000
194
195
196#define Tx_TxColl_MASK 0x0000000F
197#define Tx_ExColl 0x00000010
198#define Tx_TXDefer 0x00000020
199#define Tx_Paused 0x00000040
200#define Tx_IntTx 0x00000080
201#define Tx_Under 0x00000100
202#define Tx_Defer 0x00000200
203#define Tx_NCarr 0x00000400
204#define Tx_10Stat 0x00000800
205#define Tx_LateColl 0x00001000
206#define Tx_TxPar 0x00002000
207#define Tx_Comp 0x00004000
208#define Tx_Halted 0x00008000
209#define Tx_SQErr 0x00010000
210
211
212#define Rx_EnGood 0x00004000
213#define Rx_EnRxPar 0x00002000
214#define Rx_EnLongErr 0x00000800
215#define Rx_EnOver 0x00000400
216#define Rx_EnCRCErr 0x00000200
217#define Rx_EnAlign 0x00000100
218#define Rx_IgnoreCRC 0x00000040
219#define Rx_StripCRC 0x00000010
220#define Rx_ShortEn 0x00000008
221#define Rx_LongEn 0x00000004
222#define Rx_RxHalt 0x00000002
223#define Rx_RxEn 0x00000001
224
225
226#define Rx_Halted 0x00008000
227#define Rx_Good 0x00004000
228#define Rx_RxPar 0x00002000
229#define Rx_TypePkt 0x00001000
230#define Rx_LongErr 0x00000800
231#define Rx_Over 0x00000400
232#define Rx_CRCErr 0x00000200
233#define Rx_Align 0x00000100
234#define Rx_10Stat 0x00000080
235#define Rx_IntRx 0x00000040
236#define Rx_CtlRecd 0x00000020
237#define Rx_InLenErr 0x00000010
238
239#define Rx_Stat_Mask 0x0000FFF0
240
241
242#define Int_NRAbtEn 0x00000800
243#define Int_TxCtlCmpEn 0x00000400
244#define Int_DmParErrEn 0x00000200
245#define Int_DParDEn 0x00000100
246#define Int_EarNotEn 0x00000080
247#define Int_DParErrEn 0x00000040
248#define Int_SSysErrEn 0x00000020
249#define Int_RMasAbtEn 0x00000010
250#define Int_RTargAbtEn 0x00000008
251#define Int_STargAbtEn 0x00000004
252#define Int_BLExEn 0x00000002
253#define Int_FDAExEn 0x00000001
254
255
256
257#define Int_NRabt 0x00004000
258#define Int_DmParErrStat 0x00002000
259#define Int_BLEx 0x00001000
260#define Int_FDAEx 0x00000800
261#define Int_IntNRAbt 0x00000400
262#define Int_IntCmp 0x00000200
263#define Int_IntExBD 0x00000100
264#define Int_DmParErr 0x00000080
265#define Int_IntEarNot 0x00000040
266#define Int_SWInt 0x00000020
267#define Int_IntBLEx 0x00000010
268#define Int_IntFDAEx 0x00000008
269#define Int_IntPCI 0x00000004
270#define Int_IntMacRx 0x00000002
271#define Int_IntMacTx 0x00000001
272
273
274#define MD_CA_PreSup 0x00001000
275#define MD_CA_Busy 0x00000800
276#define MD_CA_Wr 0x00000400
277
278
279
280
281
282
283
284struct FDesc {
285 volatile __u32 FDNext;
286 volatile __u32 FDSystem;
287 volatile __u32 FDStat;
288 volatile __u32 FDCtl;
289};
290
291
292struct BDesc {
293 volatile __u32 BuffData;
294 volatile __u32 BDCtl;
295};
296
297#define FD_ALIGN 16
298
299
300#define FD_FDLength_MASK 0x0000FFFF
301#define FD_BDCnt_MASK 0x001F0000
302#define FD_FrmOpt_MASK 0x7C000000
303#define FD_FrmOpt_BigEndian 0x40000000
304#define FD_FrmOpt_IntTx 0x20000000
305#define FD_FrmOpt_NoCRC 0x10000000
306#define FD_FrmOpt_NoPadding 0x08000000
307#define FD_FrmOpt_Packing 0x04000000
308#define FD_CownsFD 0x80000000
309#define FD_Next_EOL 0x00000001
310#define FD_BDCnt_SHIFT 16
311
312
313#define BD_BuffLength_MASK 0x0000FFFF
314#define BD_RxBDID_MASK 0x00FF0000
315#define BD_RxBDSeqN_MASK 0x7F000000
316#define BD_CownsBD 0x80000000
317#define BD_RxBDID_SHIFT 16
318#define BD_RxBDSeqN_SHIFT 24
319
320
321
322
323#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
324 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
325 Tx_En)
326
327#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
328 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn)
329#define INT_EN_CMD (Int_NRAbtEn | \
330 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
331 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
332 Int_STargAbtEn | \
333 Int_BLExEn | Int_FDAExEn)
334#define DMA_CTL_CMD DMA_BURST_SIZE
335#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
336
337
338#define DMA_BURST_SIZE 32
339#define TX_THRESHOLD 1024
340
341#define TX_THRESHOLD_MAX 1536
342
343#define TX_THRESHOLD_KEEP_LIMIT 10
344
345
346#define FD_PAGE_NUM 4
347#define RX_BUF_NUM 128
348#define RX_FD_NUM 256
349#define TX_FD_NUM 128
350#if RX_CTL_CMD & Rx_LongEn
351#define RX_BUF_SIZE PAGE_SIZE
352#elif RX_CTL_CMD & Rx_StripCRC
353#define RX_BUF_SIZE \
354 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
355#else
356#define RX_BUF_SIZE \
357 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
358#endif
359#define RX_FD_RESERVE (2 / 2)
360#define NAPI_WEIGHT 16
361
362struct TxFD {
363 struct FDesc fd;
364 struct BDesc bd;
365 struct BDesc unused;
366};
367
368struct RxFD {
369 struct FDesc fd;
370 struct BDesc bd[0];
371};
372
373struct FrFD {
374 struct FDesc fd;
375 struct BDesc bd[RX_BUF_NUM];
376};
377
378
379#define tc_readl(addr) ioread32(addr)
380#define tc_writel(d, addr) iowrite32(d, addr)
381
382#define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
383
384
385struct tc35815_local {
386 struct pci_dev *pci_dev;
387
388 struct net_device *dev;
389 struct napi_struct napi;
390
391
392 struct {
393 int max_tx_qlen;
394 int tx_ints;
395 int rx_ints;
396 int tx_underrun;
397 } lstats;
398
399
400
401
402
403
404 spinlock_t lock;
405 spinlock_t rx_lock;
406
407 struct mii_bus *mii_bus;
408 struct phy_device *phy_dev;
409 int duplex;
410 int speed;
411 int link;
412 struct work_struct restart_work;
413
414
415
416
417
418
419
420
421
422 void *fd_buf;
423 dma_addr_t fd_buf_dma;
424 struct TxFD *tfd_base;
425 unsigned int tfd_start;
426 unsigned int tfd_end;
427 struct RxFD *rfd_base;
428 struct RxFD *rfd_limit;
429 struct RxFD *rfd_cur;
430 struct FrFD *fbl_ptr;
431 unsigned int fbl_count;
432 struct {
433 struct sk_buff *skb;
434 dma_addr_t skb_dma;
435 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
436 u32 msg_enable;
437 enum tc35815_chiptype chiptype;
438};
439
440static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
441{
442 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
443}
444#ifdef DEBUG
445static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
446{
447 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
448}
449#endif
450static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
451 struct pci_dev *hwdev,
452 dma_addr_t *dma_handle)
453{
454 struct sk_buff *skb;
455 skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
456 if (!skb)
457 return NULL;
458 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
459 PCI_DMA_FROMDEVICE);
460 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
461 dev_kfree_skb_any(skb);
462 return NULL;
463 }
464 skb_reserve(skb, 2);
465 return skb;
466}
467
468static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
469{
470 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
471 PCI_DMA_FROMDEVICE);
472 dev_kfree_skb_any(skb);
473}
474
475
476
477static int tc35815_open(struct net_device *dev);
478static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
479static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
480static int tc35815_rx(struct net_device *dev, int limit);
481static int tc35815_poll(struct napi_struct *napi, int budget);
482static void tc35815_txdone(struct net_device *dev);
483static int tc35815_close(struct net_device *dev);
484static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
485static void tc35815_set_multicast_list(struct net_device *dev);
486static void tc35815_tx_timeout(struct net_device *dev);
487static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
488#ifdef CONFIG_NET_POLL_CONTROLLER
489static void tc35815_poll_controller(struct net_device *dev);
490#endif
491static const struct ethtool_ops tc35815_ethtool_ops;
492
493
494static void tc35815_chip_reset(struct net_device *dev);
495static void tc35815_chip_init(struct net_device *dev);
496
497#ifdef DEBUG
498static void panic_queues(struct net_device *dev);
499#endif
500
501static void tc35815_restart_work(struct work_struct *work);
502
503static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
504{
505 struct net_device *dev = bus->priv;
506 struct tc35815_regs __iomem *tr =
507 (struct tc35815_regs __iomem *)dev->base_addr;
508 unsigned long timeout = jiffies + HZ;
509
510 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
511 udelay(12);
512 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
513 if (time_after(jiffies, timeout))
514 return -EIO;
515 cpu_relax();
516 }
517 return tc_readl(&tr->MD_Data) & 0xffff;
518}
519
520static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
521{
522 struct net_device *dev = bus->priv;
523 struct tc35815_regs __iomem *tr =
524 (struct tc35815_regs __iomem *)dev->base_addr;
525 unsigned long timeout = jiffies + HZ;
526
527 tc_writel(val, &tr->MD_Data);
528 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
529 &tr->MD_CA);
530 udelay(12);
531 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
532 if (time_after(jiffies, timeout))
533 return -EIO;
534 cpu_relax();
535 }
536 return 0;
537}
538
539static void tc_handle_link_change(struct net_device *dev)
540{
541 struct tc35815_local *lp = netdev_priv(dev);
542 struct phy_device *phydev = lp->phy_dev;
543 unsigned long flags;
544 int status_change = 0;
545
546 spin_lock_irqsave(&lp->lock, flags);
547 if (phydev->link &&
548 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
549 struct tc35815_regs __iomem *tr =
550 (struct tc35815_regs __iomem *)dev->base_addr;
551 u32 reg;
552
553 reg = tc_readl(&tr->MAC_Ctl);
554 reg |= MAC_HaltReq;
555 tc_writel(reg, &tr->MAC_Ctl);
556 if (phydev->duplex == DUPLEX_FULL)
557 reg |= MAC_FullDup;
558 else
559 reg &= ~MAC_FullDup;
560 tc_writel(reg, &tr->MAC_Ctl);
561 reg &= ~MAC_HaltReq;
562 tc_writel(reg, &tr->MAC_Ctl);
563
564
565
566
567
568
569
570
571
572
573 if (phydev->duplex == DUPLEX_HALF &&
574 lp->chiptype != TC35815_TX4939)
575 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
576 &tr->Tx_Ctl);
577
578 lp->speed = phydev->speed;
579 lp->duplex = phydev->duplex;
580 status_change = 1;
581 }
582
583 if (phydev->link != lp->link) {
584 if (phydev->link) {
585
586 if (dev->flags & IFF_PROMISC)
587 tc35815_set_multicast_list(dev);
588 } else {
589 lp->speed = 0;
590 lp->duplex = -1;
591 }
592 lp->link = phydev->link;
593
594 status_change = 1;
595 }
596 spin_unlock_irqrestore(&lp->lock, flags);
597
598 if (status_change && netif_msg_link(lp)) {
599 phy_print_status(phydev);
600 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
601 dev->name,
602 phy_read(phydev, MII_BMCR),
603 phy_read(phydev, MII_BMSR),
604 phy_read(phydev, MII_LPA));
605 }
606}
607
608static int tc_mii_probe(struct net_device *dev)
609{
610 struct tc35815_local *lp = netdev_priv(dev);
611 struct phy_device *phydev = NULL;
612 int phy_addr;
613 u32 dropmask;
614
615
616 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
617 if (lp->mii_bus->phy_map[phy_addr]) {
618 if (phydev) {
619 printk(KERN_ERR "%s: multiple PHYs found\n",
620 dev->name);
621 return -EINVAL;
622 }
623 phydev = lp->mii_bus->phy_map[phy_addr];
624 break;
625 }
626 }
627
628 if (!phydev) {
629 printk(KERN_ERR "%s: no PHY found\n", dev->name);
630 return -ENODEV;
631 }
632
633
634 phydev = phy_connect(dev, dev_name(&phydev->dev),
635 &tc_handle_link_change,
636 lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
637 if (IS_ERR(phydev)) {
638 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
639 return PTR_ERR(phydev);
640 }
641 printk(KERN_INFO "%s: attached PHY driver [%s] "
642 "(mii_bus:phy_addr=%s, id=%x)\n",
643 dev->name, phydev->drv->name, dev_name(&phydev->dev),
644 phydev->phy_id);
645
646
647 phydev->supported &= PHY_BASIC_FEATURES;
648 dropmask = 0;
649 if (options.speed == 10)
650 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
651 else if (options.speed == 100)
652 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
653 if (options.duplex == 1)
654 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
655 else if (options.duplex == 2)
656 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
657 phydev->supported &= ~dropmask;
658 phydev->advertising = phydev->supported;
659
660 lp->link = 0;
661 lp->speed = 0;
662 lp->duplex = -1;
663 lp->phy_dev = phydev;
664
665 return 0;
666}
667
668static int tc_mii_init(struct net_device *dev)
669{
670 struct tc35815_local *lp = netdev_priv(dev);
671 int err;
672 int i;
673
674 lp->mii_bus = mdiobus_alloc();
675 if (lp->mii_bus == NULL) {
676 err = -ENOMEM;
677 goto err_out;
678 }
679
680 lp->mii_bus->name = "tc35815_mii_bus";
681 lp->mii_bus->read = tc_mdio_read;
682 lp->mii_bus->write = tc_mdio_write;
683 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
684 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
685 lp->mii_bus->priv = dev;
686 lp->mii_bus->parent = &lp->pci_dev->dev;
687 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
688 if (!lp->mii_bus->irq) {
689 err = -ENOMEM;
690 goto err_out_free_mii_bus;
691 }
692
693 for (i = 0; i < PHY_MAX_ADDR; i++)
694 lp->mii_bus->irq[i] = PHY_POLL;
695
696 err = mdiobus_register(lp->mii_bus);
697 if (err)
698 goto err_out_free_mdio_irq;
699 err = tc_mii_probe(dev);
700 if (err)
701 goto err_out_unregister_bus;
702 return 0;
703
704err_out_unregister_bus:
705 mdiobus_unregister(lp->mii_bus);
706err_out_free_mdio_irq:
707 kfree(lp->mii_bus->irq);
708err_out_free_mii_bus:
709 mdiobus_free(lp->mii_bus);
710err_out:
711 return err;
712}
713
714#ifdef CONFIG_CPU_TX49XX
715
716
717
718
719
720static int tc35815_mac_match(struct device *dev, void *data)
721{
722 struct platform_device *plat_dev = to_platform_device(dev);
723 struct pci_dev *pci_dev = data;
724 unsigned int id = pci_dev->irq;
725 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
726}
727
728static int tc35815_read_plat_dev_addr(struct net_device *dev)
729{
730 struct tc35815_local *lp = netdev_priv(dev);
731 struct device *pd = bus_find_device(&platform_bus_type, NULL,
732 lp->pci_dev, tc35815_mac_match);
733 if (pd) {
734 if (pd->platform_data)
735 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
736 put_device(pd);
737 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
738 }
739 return -ENODEV;
740}
741#else
742static int tc35815_read_plat_dev_addr(struct net_device *dev)
743{
744 return -ENODEV;
745}
746#endif
747
748static int tc35815_init_dev_addr(struct net_device *dev)
749{
750 struct tc35815_regs __iomem *tr =
751 (struct tc35815_regs __iomem *)dev->base_addr;
752 int i;
753
754 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
755 ;
756 for (i = 0; i < 6; i += 2) {
757 unsigned short data;
758 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
759 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
760 ;
761 data = tc_readl(&tr->PROM_Data);
762 dev->dev_addr[i] = data & 0xff;
763 dev->dev_addr[i+1] = data >> 8;
764 }
765 if (!is_valid_ether_addr(dev->dev_addr))
766 return tc35815_read_plat_dev_addr(dev);
767 return 0;
768}
769
770static const struct net_device_ops tc35815_netdev_ops = {
771 .ndo_open = tc35815_open,
772 .ndo_stop = tc35815_close,
773 .ndo_start_xmit = tc35815_send_packet,
774 .ndo_get_stats = tc35815_get_stats,
775 .ndo_set_rx_mode = tc35815_set_multicast_list,
776 .ndo_tx_timeout = tc35815_tx_timeout,
777 .ndo_do_ioctl = tc35815_ioctl,
778 .ndo_validate_addr = eth_validate_addr,
779 .ndo_change_mtu = eth_change_mtu,
780 .ndo_set_mac_address = eth_mac_addr,
781#ifdef CONFIG_NET_POLL_CONTROLLER
782 .ndo_poll_controller = tc35815_poll_controller,
783#endif
784};
785
786static int tc35815_init_one(struct pci_dev *pdev,
787 const struct pci_device_id *ent)
788{
789 void __iomem *ioaddr = NULL;
790 struct net_device *dev;
791 struct tc35815_local *lp;
792 int rc;
793
794 static int printed_version;
795 if (!printed_version++) {
796 printk(version);
797 dev_printk(KERN_DEBUG, &pdev->dev,
798 "speed:%d duplex:%d\n",
799 options.speed, options.duplex);
800 }
801
802 if (!pdev->irq) {
803 dev_warn(&pdev->dev, "no IRQ assigned.\n");
804 return -ENODEV;
805 }
806
807
808 dev = alloc_etherdev(sizeof(*lp));
809 if (dev == NULL)
810 return -ENOMEM;
811
812 SET_NETDEV_DEV(dev, &pdev->dev);
813 lp = netdev_priv(dev);
814 lp->dev = dev;
815
816
817 rc = pcim_enable_device(pdev);
818 if (rc)
819 goto err_out;
820 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
821 if (rc)
822 goto err_out;
823 pci_set_master(pdev);
824 ioaddr = pcim_iomap_table(pdev)[1];
825
826
827 dev->netdev_ops = &tc35815_netdev_ops;
828 dev->ethtool_ops = &tc35815_ethtool_ops;
829 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
830 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
831
832 dev->irq = pdev->irq;
833 dev->base_addr = (unsigned long)ioaddr;
834
835 INIT_WORK(&lp->restart_work, tc35815_restart_work);
836 spin_lock_init(&lp->lock);
837 spin_lock_init(&lp->rx_lock);
838 lp->pci_dev = pdev;
839 lp->chiptype = ent->driver_data;
840
841 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
842 pci_set_drvdata(pdev, dev);
843
844
845 tc35815_chip_reset(dev);
846
847
848 if (tc35815_init_dev_addr(dev)) {
849 dev_warn(&pdev->dev, "not valid ether addr\n");
850 eth_hw_addr_random(dev);
851 }
852
853 rc = register_netdev(dev);
854 if (rc)
855 goto err_out;
856
857 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
858 dev->name,
859 chip_info[ent->driver_data].name,
860 dev->base_addr,
861 dev->dev_addr,
862 dev->irq);
863
864 rc = tc_mii_init(dev);
865 if (rc)
866 goto err_out_unregister;
867
868 return 0;
869
870err_out_unregister:
871 unregister_netdev(dev);
872err_out:
873 free_netdev(dev);
874 return rc;
875}
876
877
878static void tc35815_remove_one(struct pci_dev *pdev)
879{
880 struct net_device *dev = pci_get_drvdata(pdev);
881 struct tc35815_local *lp = netdev_priv(dev);
882
883 phy_disconnect(lp->phy_dev);
884 mdiobus_unregister(lp->mii_bus);
885 kfree(lp->mii_bus->irq);
886 mdiobus_free(lp->mii_bus);
887 unregister_netdev(dev);
888 free_netdev(dev);
889}
890
891static int
892tc35815_init_queues(struct net_device *dev)
893{
894 struct tc35815_local *lp = netdev_priv(dev);
895 int i;
896 unsigned long fd_addr;
897
898 if (!lp->fd_buf) {
899 BUG_ON(sizeof(struct FDesc) +
900 sizeof(struct BDesc) * RX_BUF_NUM +
901 sizeof(struct FDesc) * RX_FD_NUM +
902 sizeof(struct TxFD) * TX_FD_NUM >
903 PAGE_SIZE * FD_PAGE_NUM);
904
905 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
906 PAGE_SIZE * FD_PAGE_NUM,
907 &lp->fd_buf_dma);
908 if (!lp->fd_buf)
909 return -ENOMEM;
910 for (i = 0; i < RX_BUF_NUM; i++) {
911 lp->rx_skbs[i].skb =
912 alloc_rxbuf_skb(dev, lp->pci_dev,
913 &lp->rx_skbs[i].skb_dma);
914 if (!lp->rx_skbs[i].skb) {
915 while (--i >= 0) {
916 free_rxbuf_skb(lp->pci_dev,
917 lp->rx_skbs[i].skb,
918 lp->rx_skbs[i].skb_dma);
919 lp->rx_skbs[i].skb = NULL;
920 }
921 pci_free_consistent(lp->pci_dev,
922 PAGE_SIZE * FD_PAGE_NUM,
923 lp->fd_buf,
924 lp->fd_buf_dma);
925 lp->fd_buf = NULL;
926 return -ENOMEM;
927 }
928 }
929 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
930 dev->name, lp->fd_buf);
931 printk("\n");
932 } else {
933 for (i = 0; i < FD_PAGE_NUM; i++)
934 clear_page((void *)((unsigned long)lp->fd_buf +
935 i * PAGE_SIZE));
936 }
937 fd_addr = (unsigned long)lp->fd_buf;
938
939
940 lp->rfd_base = (struct RxFD *)fd_addr;
941 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
942 for (i = 0; i < RX_FD_NUM; i++)
943 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
944 lp->rfd_cur = lp->rfd_base;
945 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
946
947
948 lp->tfd_base = (struct TxFD *)fd_addr;
949 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
950 for (i = 0; i < TX_FD_NUM; i++) {
951 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
952 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
953 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
954 }
955 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
956 lp->tfd_start = 0;
957 lp->tfd_end = 0;
958
959
960 lp->fbl_ptr = (struct FrFD *)fd_addr;
961 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
962 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
963
964
965
966
967
968 lp->fbl_count = 0;
969 for (i = 0; i < RX_BUF_NUM; i++) {
970 if (lp->rx_skbs[i].skb) {
971 if (i != lp->fbl_count) {
972 lp->rx_skbs[lp->fbl_count].skb =
973 lp->rx_skbs[i].skb;
974 lp->rx_skbs[lp->fbl_count].skb_dma =
975 lp->rx_skbs[i].skb_dma;
976 }
977 lp->fbl_count++;
978 }
979 }
980 for (i = 0; i < RX_BUF_NUM; i++) {
981 if (i >= lp->fbl_count) {
982 lp->fbl_ptr->bd[i].BuffData = 0;
983 lp->fbl_ptr->bd[i].BDCtl = 0;
984 continue;
985 }
986 lp->fbl_ptr->bd[i].BuffData =
987 cpu_to_le32(lp->rx_skbs[i].skb_dma);
988
989 lp->fbl_ptr->bd[i].BDCtl =
990 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
991 RX_BUF_SIZE);
992 }
993
994 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
995 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
996 return 0;
997}
998
999static void
1000tc35815_clear_queues(struct net_device *dev)
1001{
1002 struct tc35815_local *lp = netdev_priv(dev);
1003 int i;
1004
1005 for (i = 0; i < TX_FD_NUM; i++) {
1006 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1007 struct sk_buff *skb =
1008 fdsystem != 0xffffffff ?
1009 lp->tx_skbs[fdsystem].skb : NULL;
1010#ifdef DEBUG
1011 if (lp->tx_skbs[i].skb != skb) {
1012 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1013 panic_queues(dev);
1014 }
1015#else
1016 BUG_ON(lp->tx_skbs[i].skb != skb);
1017#endif
1018 if (skb) {
1019 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1020 lp->tx_skbs[i].skb = NULL;
1021 lp->tx_skbs[i].skb_dma = 0;
1022 dev_kfree_skb_any(skb);
1023 }
1024 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1025 }
1026
1027 tc35815_init_queues(dev);
1028}
1029
1030static void
1031tc35815_free_queues(struct net_device *dev)
1032{
1033 struct tc35815_local *lp = netdev_priv(dev);
1034 int i;
1035
1036 if (lp->tfd_base) {
1037 for (i = 0; i < TX_FD_NUM; i++) {
1038 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1039 struct sk_buff *skb =
1040 fdsystem != 0xffffffff ?
1041 lp->tx_skbs[fdsystem].skb : NULL;
1042#ifdef DEBUG
1043 if (lp->tx_skbs[i].skb != skb) {
1044 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1045 panic_queues(dev);
1046 }
1047#else
1048 BUG_ON(lp->tx_skbs[i].skb != skb);
1049#endif
1050 if (skb) {
1051 dev_kfree_skb(skb);
1052 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1053 lp->tx_skbs[i].skb = NULL;
1054 lp->tx_skbs[i].skb_dma = 0;
1055 }
1056 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1057 }
1058 }
1059
1060 lp->rfd_base = NULL;
1061 lp->rfd_limit = NULL;
1062 lp->rfd_cur = NULL;
1063 lp->fbl_ptr = NULL;
1064
1065 for (i = 0; i < RX_BUF_NUM; i++) {
1066 if (lp->rx_skbs[i].skb) {
1067 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1068 lp->rx_skbs[i].skb_dma);
1069 lp->rx_skbs[i].skb = NULL;
1070 }
1071 }
1072 if (lp->fd_buf) {
1073 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1074 lp->fd_buf, lp->fd_buf_dma);
1075 lp->fd_buf = NULL;
1076 }
1077}
1078
1079static void
1080dump_txfd(struct TxFD *fd)
1081{
1082 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1083 le32_to_cpu(fd->fd.FDNext),
1084 le32_to_cpu(fd->fd.FDSystem),
1085 le32_to_cpu(fd->fd.FDStat),
1086 le32_to_cpu(fd->fd.FDCtl));
1087 printk("BD: ");
1088 printk(" %08x %08x",
1089 le32_to_cpu(fd->bd.BuffData),
1090 le32_to_cpu(fd->bd.BDCtl));
1091 printk("\n");
1092}
1093
1094static int
1095dump_rxfd(struct RxFD *fd)
1096{
1097 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1098 if (bd_count > 8)
1099 bd_count = 8;
1100 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1101 le32_to_cpu(fd->fd.FDNext),
1102 le32_to_cpu(fd->fd.FDSystem),
1103 le32_to_cpu(fd->fd.FDStat),
1104 le32_to_cpu(fd->fd.FDCtl));
1105 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1106 return 0;
1107 printk("BD: ");
1108 for (i = 0; i < bd_count; i++)
1109 printk(" %08x %08x",
1110 le32_to_cpu(fd->bd[i].BuffData),
1111 le32_to_cpu(fd->bd[i].BDCtl));
1112 printk("\n");
1113 return bd_count;
1114}
1115
1116#ifdef DEBUG
1117static void
1118dump_frfd(struct FrFD *fd)
1119{
1120 int i;
1121 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1122 le32_to_cpu(fd->fd.FDNext),
1123 le32_to_cpu(fd->fd.FDSystem),
1124 le32_to_cpu(fd->fd.FDStat),
1125 le32_to_cpu(fd->fd.FDCtl));
1126 printk("BD: ");
1127 for (i = 0; i < RX_BUF_NUM; i++)
1128 printk(" %08x %08x",
1129 le32_to_cpu(fd->bd[i].BuffData),
1130 le32_to_cpu(fd->bd[i].BDCtl));
1131 printk("\n");
1132}
1133
1134static void
1135panic_queues(struct net_device *dev)
1136{
1137 struct tc35815_local *lp = netdev_priv(dev);
1138 int i;
1139
1140 printk("TxFD base %p, start %u, end %u\n",
1141 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1142 printk("RxFD base %p limit %p cur %p\n",
1143 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1144 printk("FrFD %p\n", lp->fbl_ptr);
1145 for (i = 0; i < TX_FD_NUM; i++)
1146 dump_txfd(&lp->tfd_base[i]);
1147 for (i = 0; i < RX_FD_NUM; i++) {
1148 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1149 i += (bd_count + 1) / 2;
1150 }
1151 dump_frfd(lp->fbl_ptr);
1152 panic("%s: Illegal queue state.", dev->name);
1153}
1154#endif
1155
1156static void print_eth(const u8 *add)
1157{
1158 printk(KERN_DEBUG "print_eth(%p)\n", add);
1159 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1160 add + 6, add, add[12], add[13]);
1161}
1162
1163static int tc35815_tx_full(struct net_device *dev)
1164{
1165 struct tc35815_local *lp = netdev_priv(dev);
1166 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1167}
1168
1169static void tc35815_restart(struct net_device *dev)
1170{
1171 struct tc35815_local *lp = netdev_priv(dev);
1172 int ret;
1173
1174 if (lp->phy_dev) {
1175 ret = phy_init_hw(lp->phy_dev);
1176 if (ret)
1177 printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
1178 }
1179
1180 spin_lock_bh(&lp->rx_lock);
1181 spin_lock_irq(&lp->lock);
1182 tc35815_chip_reset(dev);
1183 tc35815_clear_queues(dev);
1184 tc35815_chip_init(dev);
1185
1186 tc35815_set_multicast_list(dev);
1187 spin_unlock_irq(&lp->lock);
1188 spin_unlock_bh(&lp->rx_lock);
1189
1190 netif_wake_queue(dev);
1191}
1192
1193static void tc35815_restart_work(struct work_struct *work)
1194{
1195 struct tc35815_local *lp =
1196 container_of(work, struct tc35815_local, restart_work);
1197 struct net_device *dev = lp->dev;
1198
1199 tc35815_restart(dev);
1200}
1201
1202static void tc35815_schedule_restart(struct net_device *dev)
1203{
1204 struct tc35815_local *lp = netdev_priv(dev);
1205 struct tc35815_regs __iomem *tr =
1206 (struct tc35815_regs __iomem *)dev->base_addr;
1207 unsigned long flags;
1208
1209
1210 spin_lock_irqsave(&lp->lock, flags);
1211 tc_writel(0, &tr->Int_En);
1212 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1213 schedule_work(&lp->restart_work);
1214 spin_unlock_irqrestore(&lp->lock, flags);
1215}
1216
1217static void tc35815_tx_timeout(struct net_device *dev)
1218{
1219 struct tc35815_regs __iomem *tr =
1220 (struct tc35815_regs __iomem *)dev->base_addr;
1221
1222 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1223 dev->name, tc_readl(&tr->Tx_Stat));
1224
1225
1226 tc35815_schedule_restart(dev);
1227 dev->stats.tx_errors++;
1228}
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238static int
1239tc35815_open(struct net_device *dev)
1240{
1241 struct tc35815_local *lp = netdev_priv(dev);
1242
1243
1244
1245
1246
1247 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1248 dev->name, dev))
1249 return -EAGAIN;
1250
1251 tc35815_chip_reset(dev);
1252
1253 if (tc35815_init_queues(dev) != 0) {
1254 free_irq(dev->irq, dev);
1255 return -EAGAIN;
1256 }
1257
1258 napi_enable(&lp->napi);
1259
1260
1261 spin_lock_irq(&lp->lock);
1262 tc35815_chip_init(dev);
1263 spin_unlock_irq(&lp->lock);
1264
1265 netif_carrier_off(dev);
1266
1267 phy_start(lp->phy_dev);
1268
1269
1270
1271
1272 netif_start_queue(dev);
1273
1274 return 0;
1275}
1276
1277
1278
1279
1280
1281
1282static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1283{
1284 struct tc35815_local *lp = netdev_priv(dev);
1285 struct TxFD *txfd;
1286 unsigned long flags;
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302 spin_lock_irqsave(&lp->lock, flags);
1303
1304
1305 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1306 TX_FD_NUM / 2)
1307 tc35815_txdone(dev);
1308
1309 if (netif_msg_pktdata(lp))
1310 print_eth(skb->data);
1311#ifdef DEBUG
1312 if (lp->tx_skbs[lp->tfd_start].skb) {
1313 printk("%s: tx_skbs conflict.\n", dev->name);
1314 panic_queues(dev);
1315 }
1316#else
1317 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1318#endif
1319 lp->tx_skbs[lp->tfd_start].skb = skb;
1320 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1321
1322
1323 txfd = &lp->tfd_base[lp->tfd_start];
1324 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1325 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1326 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1327 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1328
1329 if (lp->tfd_start == lp->tfd_end) {
1330 struct tc35815_regs __iomem *tr =
1331 (struct tc35815_regs __iomem *)dev->base_addr;
1332
1333 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1334 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1335 if (netif_msg_tx_queued(lp)) {
1336 printk("%s: starting TxFD.\n", dev->name);
1337 dump_txfd(txfd);
1338 }
1339 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1340 } else {
1341 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1342 if (netif_msg_tx_queued(lp)) {
1343 printk("%s: queueing TxFD.\n", dev->name);
1344 dump_txfd(txfd);
1345 }
1346 }
1347 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1348
1349
1350
1351
1352
1353 if (tc35815_tx_full(dev)) {
1354 if (netif_msg_tx_queued(lp))
1355 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1356 netif_stop_queue(dev);
1357 }
1358
1359
1360
1361
1362
1363 spin_unlock_irqrestore(&lp->lock, flags);
1364 return NETDEV_TX_OK;
1365}
1366
1367#define FATAL_ERROR_INT \
1368 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1369static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1370{
1371 static int count;
1372 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1373 dev->name, status);
1374 if (status & Int_IntPCI)
1375 printk(" IntPCI");
1376 if (status & Int_DmParErr)
1377 printk(" DmParErr");
1378 if (status & Int_IntNRAbt)
1379 printk(" IntNRAbt");
1380 printk("\n");
1381 if (count++ > 100)
1382 panic("%s: Too many fatal errors.", dev->name);
1383 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1384
1385 tc35815_schedule_restart(dev);
1386}
1387
1388static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1389{
1390 struct tc35815_local *lp = netdev_priv(dev);
1391 int ret = -1;
1392
1393
1394 if (status & FATAL_ERROR_INT) {
1395 tc35815_fatal_error_interrupt(dev, status);
1396 return 0;
1397 }
1398
1399 if (status & Int_IntFDAEx) {
1400 if (netif_msg_rx_err(lp))
1401 dev_warn(&dev->dev,
1402 "Free Descriptor Area Exhausted (%#x).\n",
1403 status);
1404 dev->stats.rx_dropped++;
1405 ret = 0;
1406 }
1407 if (status & Int_IntBLEx) {
1408 if (netif_msg_rx_err(lp))
1409 dev_warn(&dev->dev,
1410 "Buffer List Exhausted (%#x).\n",
1411 status);
1412 dev->stats.rx_dropped++;
1413 ret = 0;
1414 }
1415 if (status & Int_IntExBD) {
1416 if (netif_msg_rx_err(lp))
1417 dev_warn(&dev->dev,
1418 "Excessive Buffer Descriptiors (%#x).\n",
1419 status);
1420 dev->stats.rx_length_errors++;
1421 ret = 0;
1422 }
1423
1424
1425 if (status & Int_IntMacRx) {
1426
1427 ret = tc35815_rx(dev, limit);
1428 lp->lstats.rx_ints++;
1429 }
1430 if (status & Int_IntMacTx) {
1431
1432 lp->lstats.tx_ints++;
1433 spin_lock_irq(&lp->lock);
1434 tc35815_txdone(dev);
1435 spin_unlock_irq(&lp->lock);
1436 if (ret < 0)
1437 ret = 0;
1438 }
1439 return ret;
1440}
1441
1442
1443
1444
1445
1446static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1447{
1448 struct net_device *dev = dev_id;
1449 struct tc35815_local *lp = netdev_priv(dev);
1450 struct tc35815_regs __iomem *tr =
1451 (struct tc35815_regs __iomem *)dev->base_addr;
1452 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1453
1454 if (!(dmactl & DMA_IntMask)) {
1455
1456 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1457 if (napi_schedule_prep(&lp->napi))
1458 __napi_schedule(&lp->napi);
1459 else {
1460 printk(KERN_ERR "%s: interrupt taken in poll\n",
1461 dev->name);
1462 BUG();
1463 }
1464 (void)tc_readl(&tr->Int_Src);
1465 return IRQ_HANDLED;
1466 }
1467 return IRQ_NONE;
1468}
1469
1470#ifdef CONFIG_NET_POLL_CONTROLLER
1471static void tc35815_poll_controller(struct net_device *dev)
1472{
1473 disable_irq(dev->irq);
1474 tc35815_interrupt(dev->irq, dev);
1475 enable_irq(dev->irq);
1476}
1477#endif
1478
1479
1480static int
1481tc35815_rx(struct net_device *dev, int limit)
1482{
1483 struct tc35815_local *lp = netdev_priv(dev);
1484 unsigned int fdctl;
1485 int i;
1486 int received = 0;
1487
1488 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1489 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1490 int pkt_len = fdctl & FD_FDLength_MASK;
1491 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1492#ifdef DEBUG
1493 struct RxFD *next_rfd;
1494#endif
1495#if (RX_CTL_CMD & Rx_StripCRC) == 0
1496 pkt_len -= ETH_FCS_LEN;
1497#endif
1498
1499 if (netif_msg_rx_status(lp))
1500 dump_rxfd(lp->rfd_cur);
1501 if (status & Rx_Good) {
1502 struct sk_buff *skb;
1503 unsigned char *data;
1504 int cur_bd;
1505
1506 if (--limit < 0)
1507 break;
1508 BUG_ON(bd_count > 1);
1509 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1510 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1511#ifdef DEBUG
1512 if (cur_bd >= RX_BUF_NUM) {
1513 printk("%s: invalid BDID.\n", dev->name);
1514 panic_queues(dev);
1515 }
1516 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1517 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1518 if (!lp->rx_skbs[cur_bd].skb) {
1519 printk("%s: NULL skb.\n", dev->name);
1520 panic_queues(dev);
1521 }
1522#else
1523 BUG_ON(cur_bd >= RX_BUF_NUM);
1524#endif
1525 skb = lp->rx_skbs[cur_bd].skb;
1526 prefetch(skb->data);
1527 lp->rx_skbs[cur_bd].skb = NULL;
1528 pci_unmap_single(lp->pci_dev,
1529 lp->rx_skbs[cur_bd].skb_dma,
1530 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1531 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1532 memmove(skb->data, skb->data - NET_IP_ALIGN,
1533 pkt_len);
1534 data = skb_put(skb, pkt_len);
1535 if (netif_msg_pktdata(lp))
1536 print_eth(data);
1537 skb->protocol = eth_type_trans(skb, dev);
1538 netif_receive_skb(skb);
1539 received++;
1540 dev->stats.rx_packets++;
1541 dev->stats.rx_bytes += pkt_len;
1542 } else {
1543 dev->stats.rx_errors++;
1544 if (netif_msg_rx_err(lp))
1545 dev_info(&dev->dev, "Rx error (status %x)\n",
1546 status & Rx_Stat_Mask);
1547
1548 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1549 status &= ~(Rx_LongErr|Rx_CRCErr);
1550 status |= Rx_Over;
1551 }
1552 if (status & Rx_LongErr)
1553 dev->stats.rx_length_errors++;
1554 if (status & Rx_Over)
1555 dev->stats.rx_fifo_errors++;
1556 if (status & Rx_CRCErr)
1557 dev->stats.rx_crc_errors++;
1558 if (status & Rx_Align)
1559 dev->stats.rx_frame_errors++;
1560 }
1561
1562 if (bd_count > 0) {
1563
1564 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1565 unsigned char id =
1566 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1567#ifdef DEBUG
1568 if (id >= RX_BUF_NUM) {
1569 printk("%s: invalid BDID.\n", dev->name);
1570 panic_queues(dev);
1571 }
1572#else
1573 BUG_ON(id >= RX_BUF_NUM);
1574#endif
1575
1576 lp->fbl_count--;
1577 while (lp->fbl_count < RX_BUF_NUM)
1578 {
1579 unsigned char curid =
1580 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1581 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1582#ifdef DEBUG
1583 bdctl = le32_to_cpu(bd->BDCtl);
1584 if (bdctl & BD_CownsBD) {
1585 printk("%s: Freeing invalid BD.\n",
1586 dev->name);
1587 panic_queues(dev);
1588 }
1589#endif
1590
1591 if (!lp->rx_skbs[curid].skb) {
1592 lp->rx_skbs[curid].skb =
1593 alloc_rxbuf_skb(dev,
1594 lp->pci_dev,
1595 &lp->rx_skbs[curid].skb_dma);
1596 if (!lp->rx_skbs[curid].skb)
1597 break;
1598 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1599 }
1600
1601 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1602 (curid << BD_RxBDID_SHIFT) |
1603 RX_BUF_SIZE);
1604 lp->fbl_count++;
1605 }
1606 }
1607
1608
1609#ifdef DEBUG
1610 next_rfd = fd_bus_to_virt(lp,
1611 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1612 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1613 printk("%s: RxFD FDNext invalid.\n", dev->name);
1614 panic_queues(dev);
1615 }
1616#endif
1617 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1618
1619#ifdef DEBUG
1620 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1621#else
1622 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1623#endif
1624 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1625 lp->rfd_cur++;
1626 }
1627 if (lp->rfd_cur > lp->rfd_limit)
1628 lp->rfd_cur = lp->rfd_base;
1629#ifdef DEBUG
1630 if (lp->rfd_cur != next_rfd)
1631 printk("rfd_cur = %p, next_rfd %p\n",
1632 lp->rfd_cur, next_rfd);
1633#endif
1634 }
1635
1636 return received;
1637}
1638
1639static int tc35815_poll(struct napi_struct *napi, int budget)
1640{
1641 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1642 struct net_device *dev = lp->dev;
1643 struct tc35815_regs __iomem *tr =
1644 (struct tc35815_regs __iomem *)dev->base_addr;
1645 int received = 0, handled;
1646 u32 status;
1647
1648 spin_lock(&lp->rx_lock);
1649 status = tc_readl(&tr->Int_Src);
1650 do {
1651
1652 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1653 &tr->Int_Src);
1654
1655 handled = tc35815_do_interrupt(dev, status, budget - received);
1656 if (status & (Int_BLEx | Int_FDAEx))
1657 tc_writel(status & (Int_BLEx | Int_FDAEx),
1658 &tr->Int_Src);
1659 if (handled >= 0) {
1660 received += handled;
1661 if (received >= budget)
1662 break;
1663 }
1664 status = tc_readl(&tr->Int_Src);
1665 } while (status);
1666 spin_unlock(&lp->rx_lock);
1667
1668 if (received < budget) {
1669 napi_complete(napi);
1670
1671 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1672 }
1673 return received;
1674}
1675
1676#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1677
1678static void
1679tc35815_check_tx_stat(struct net_device *dev, int status)
1680{
1681 struct tc35815_local *lp = netdev_priv(dev);
1682 const char *msg = NULL;
1683
1684
1685 if (status & Tx_ExColl)
1686 dev->stats.collisions += 16;
1687 if (status & Tx_TxColl_MASK)
1688 dev->stats.collisions += status & Tx_TxColl_MASK;
1689
1690
1691 if (lp->chiptype == TC35815_TX4939)
1692 status &= ~Tx_NCarr;
1693
1694 if (!lp->link || lp->duplex == DUPLEX_FULL)
1695 status &= ~Tx_NCarr;
1696
1697 if (!(status & TX_STA_ERR)) {
1698
1699 dev->stats.tx_packets++;
1700 return;
1701 }
1702
1703 dev->stats.tx_errors++;
1704 if (status & Tx_ExColl) {
1705 dev->stats.tx_aborted_errors++;
1706 msg = "Excessive Collision.";
1707 }
1708 if (status & Tx_Under) {
1709 dev->stats.tx_fifo_errors++;
1710 msg = "Tx FIFO Underrun.";
1711 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1712 lp->lstats.tx_underrun++;
1713 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1714 struct tc35815_regs __iomem *tr =
1715 (struct tc35815_regs __iomem *)dev->base_addr;
1716 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1717 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1718 }
1719 }
1720 }
1721 if (status & Tx_Defer) {
1722 dev->stats.tx_fifo_errors++;
1723 msg = "Excessive Deferral.";
1724 }
1725 if (status & Tx_NCarr) {
1726 dev->stats.tx_carrier_errors++;
1727 msg = "Lost Carrier Sense.";
1728 }
1729 if (status & Tx_LateColl) {
1730 dev->stats.tx_aborted_errors++;
1731 msg = "Late Collision.";
1732 }
1733 if (status & Tx_TxPar) {
1734 dev->stats.tx_fifo_errors++;
1735 msg = "Transmit Parity Error.";
1736 }
1737 if (status & Tx_SQErr) {
1738 dev->stats.tx_heartbeat_errors++;
1739 msg = "Signal Quality Error.";
1740 }
1741 if (msg && netif_msg_tx_err(lp))
1742 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1743}
1744
1745
1746
1747
1748static void
1749tc35815_txdone(struct net_device *dev)
1750{
1751 struct tc35815_local *lp = netdev_priv(dev);
1752 struct TxFD *txfd;
1753 unsigned int fdctl;
1754
1755 txfd = &lp->tfd_base[lp->tfd_end];
1756 while (lp->tfd_start != lp->tfd_end &&
1757 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1758 int status = le32_to_cpu(txfd->fd.FDStat);
1759 struct sk_buff *skb;
1760 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1761 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1762
1763 if (netif_msg_tx_done(lp)) {
1764 printk("%s: complete TxFD.\n", dev->name);
1765 dump_txfd(txfd);
1766 }
1767 tc35815_check_tx_stat(dev, status);
1768
1769 skb = fdsystem != 0xffffffff ?
1770 lp->tx_skbs[fdsystem].skb : NULL;
1771#ifdef DEBUG
1772 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1773 printk("%s: tx_skbs mismatch.\n", dev->name);
1774 panic_queues(dev);
1775 }
1776#else
1777 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1778#endif
1779 if (skb) {
1780 dev->stats.tx_bytes += skb->len;
1781 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1782 lp->tx_skbs[lp->tfd_end].skb = NULL;
1783 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1784 dev_kfree_skb_any(skb);
1785 }
1786 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1787
1788 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1789 txfd = &lp->tfd_base[lp->tfd_end];
1790#ifdef DEBUG
1791 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1792 printk("%s: TxFD FDNext invalid.\n", dev->name);
1793 panic_queues(dev);
1794 }
1795#endif
1796 if (fdnext & FD_Next_EOL) {
1797
1798 if (lp->tfd_end != lp->tfd_start) {
1799 struct tc35815_regs __iomem *tr =
1800 (struct tc35815_regs __iomem *)dev->base_addr;
1801 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1802 struct TxFD *txhead = &lp->tfd_base[head];
1803 int qlen = (lp->tfd_start + TX_FD_NUM
1804 - lp->tfd_end) % TX_FD_NUM;
1805
1806#ifdef DEBUG
1807 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1808 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1809 panic_queues(dev);
1810 }
1811#endif
1812
1813 if (lp->lstats.max_tx_qlen < qlen)
1814 lp->lstats.max_tx_qlen = qlen;
1815
1816
1817
1818 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1819 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1820 if (netif_msg_tx_queued(lp)) {
1821 printk("%s: start TxFD on queue.\n",
1822 dev->name);
1823 dump_txfd(txfd);
1824 }
1825 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1826 }
1827 break;
1828 }
1829 }
1830
1831
1832
1833
1834
1835 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1836 netif_wake_queue(dev);
1837}
1838
1839
1840static int
1841tc35815_close(struct net_device *dev)
1842{
1843 struct tc35815_local *lp = netdev_priv(dev);
1844
1845 netif_stop_queue(dev);
1846 napi_disable(&lp->napi);
1847 if (lp->phy_dev)
1848 phy_stop(lp->phy_dev);
1849 cancel_work_sync(&lp->restart_work);
1850
1851
1852 tc35815_chip_reset(dev);
1853 free_irq(dev->irq, dev);
1854
1855 tc35815_free_queues(dev);
1856
1857 return 0;
1858
1859}
1860
1861
1862
1863
1864
1865static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1866{
1867 struct tc35815_regs __iomem *tr =
1868 (struct tc35815_regs __iomem *)dev->base_addr;
1869 if (netif_running(dev))
1870
1871 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1872
1873 return &dev->stats;
1874}
1875
1876static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1877{
1878 struct tc35815_local *lp = netdev_priv(dev);
1879 struct tc35815_regs __iomem *tr =
1880 (struct tc35815_regs __iomem *)dev->base_addr;
1881 int cam_index = index * 6;
1882 u32 cam_data;
1883 u32 saved_addr;
1884
1885 saved_addr = tc_readl(&tr->CAM_Adr);
1886
1887 if (netif_msg_hw(lp))
1888 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1889 dev->name, index, addr);
1890 if (index & 1) {
1891
1892 tc_writel(cam_index - 2, &tr->CAM_Adr);
1893 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1894 cam_data |= addr[0] << 8 | addr[1];
1895 tc_writel(cam_data, &tr->CAM_Data);
1896
1897 tc_writel(cam_index + 2, &tr->CAM_Adr);
1898 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1899 tc_writel(cam_data, &tr->CAM_Data);
1900 } else {
1901
1902 tc_writel(cam_index, &tr->CAM_Adr);
1903 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1904 tc_writel(cam_data, &tr->CAM_Data);
1905
1906 tc_writel(cam_index + 4, &tr->CAM_Adr);
1907 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1908 cam_data |= addr[4] << 24 | (addr[5] << 16);
1909 tc_writel(cam_data, &tr->CAM_Data);
1910 }
1911
1912 tc_writel(saved_addr, &tr->CAM_Adr);
1913}
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923static void
1924tc35815_set_multicast_list(struct net_device *dev)
1925{
1926 struct tc35815_regs __iomem *tr =
1927 (struct tc35815_regs __iomem *)dev->base_addr;
1928
1929 if (dev->flags & IFF_PROMISC) {
1930
1931
1932 struct tc35815_local *lp = netdev_priv(dev);
1933
1934 if (!lp->link)
1935 return;
1936
1937 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1938 } else if ((dev->flags & IFF_ALLMULTI) ||
1939 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1940
1941
1942 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1943 } else if (!netdev_mc_empty(dev)) {
1944 struct netdev_hw_addr *ha;
1945 int i;
1946 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1947
1948 tc_writel(0, &tr->CAM_Ctl);
1949
1950 i = 0;
1951 netdev_for_each_mc_addr(ha, dev) {
1952
1953 tc35815_set_cam_entry(dev, i + 2, ha->addr);
1954 ena_bits |= CAM_Ena_Bit(i + 2);
1955 i++;
1956 }
1957 tc_writel(ena_bits, &tr->CAM_Ena);
1958 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1959 } else {
1960 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1961 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1962 }
1963}
1964
1965static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1966{
1967 struct tc35815_local *lp = netdev_priv(dev);
1968
1969 strlcpy(info->driver, MODNAME, sizeof(info->driver));
1970 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1971 strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
1972}
1973
1974static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1975{
1976 struct tc35815_local *lp = netdev_priv(dev);
1977
1978 if (!lp->phy_dev)
1979 return -ENODEV;
1980 return phy_ethtool_gset(lp->phy_dev, cmd);
1981}
1982
1983static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1984{
1985 struct tc35815_local *lp = netdev_priv(dev);
1986
1987 if (!lp->phy_dev)
1988 return -ENODEV;
1989 return phy_ethtool_sset(lp->phy_dev, cmd);
1990}
1991
1992static u32 tc35815_get_msglevel(struct net_device *dev)
1993{
1994 struct tc35815_local *lp = netdev_priv(dev);
1995 return lp->msg_enable;
1996}
1997
1998static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
1999{
2000 struct tc35815_local *lp = netdev_priv(dev);
2001 lp->msg_enable = datum;
2002}
2003
2004static int tc35815_get_sset_count(struct net_device *dev, int sset)
2005{
2006 struct tc35815_local *lp = netdev_priv(dev);
2007
2008 switch (sset) {
2009 case ETH_SS_STATS:
2010 return sizeof(lp->lstats) / sizeof(int);
2011 default:
2012 return -EOPNOTSUPP;
2013 }
2014}
2015
2016static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2017{
2018 struct tc35815_local *lp = netdev_priv(dev);
2019 data[0] = lp->lstats.max_tx_qlen;
2020 data[1] = lp->lstats.tx_ints;
2021 data[2] = lp->lstats.rx_ints;
2022 data[3] = lp->lstats.tx_underrun;
2023}
2024
2025static struct {
2026 const char str[ETH_GSTRING_LEN];
2027} ethtool_stats_keys[] = {
2028 { "max_tx_qlen" },
2029 { "tx_ints" },
2030 { "rx_ints" },
2031 { "tx_underrun" },
2032};
2033
2034static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2035{
2036 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2037}
2038
2039static const struct ethtool_ops tc35815_ethtool_ops = {
2040 .get_drvinfo = tc35815_get_drvinfo,
2041 .get_settings = tc35815_get_settings,
2042 .set_settings = tc35815_set_settings,
2043 .get_link = ethtool_op_get_link,
2044 .get_msglevel = tc35815_get_msglevel,
2045 .set_msglevel = tc35815_set_msglevel,
2046 .get_strings = tc35815_get_strings,
2047 .get_sset_count = tc35815_get_sset_count,
2048 .get_ethtool_stats = tc35815_get_ethtool_stats,
2049};
2050
2051static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2052{
2053 struct tc35815_local *lp = netdev_priv(dev);
2054
2055 if (!netif_running(dev))
2056 return -EINVAL;
2057 if (!lp->phy_dev)
2058 return -ENODEV;
2059 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
2060}
2061
2062static void tc35815_chip_reset(struct net_device *dev)
2063{
2064 struct tc35815_regs __iomem *tr =
2065 (struct tc35815_regs __iomem *)dev->base_addr;
2066 int i;
2067
2068 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2069 udelay(4);
2070 i = 0;
2071 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2072 if (i++ > 100) {
2073 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2074 break;
2075 }
2076 mdelay(1);
2077 }
2078 tc_writel(0, &tr->MAC_Ctl);
2079
2080
2081 tc_writel(0, &tr->DMA_Ctl);
2082 tc_writel(0, &tr->TxThrsh);
2083 tc_writel(0, &tr->TxPollCtr);
2084 tc_writel(0, &tr->RxFragSize);
2085 tc_writel(0, &tr->Int_En);
2086 tc_writel(0, &tr->FDA_Bas);
2087 tc_writel(0, &tr->FDA_Lim);
2088 tc_writel(0xffffffff, &tr->Int_Src);
2089 tc_writel(0, &tr->CAM_Ctl);
2090 tc_writel(0, &tr->Tx_Ctl);
2091 tc_writel(0, &tr->Rx_Ctl);
2092 tc_writel(0, &tr->CAM_Ena);
2093 (void)tc_readl(&tr->Miss_Cnt);
2094
2095
2096 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2097 for (i = 0; i < 0x1000; i += 4) {
2098 tc_writel(i, &tr->CAM_Adr);
2099 tc_writel(0, &tr->CAM_Data);
2100 }
2101 tc_writel(0, &tr->DMA_Ctl);
2102}
2103
2104static void tc35815_chip_init(struct net_device *dev)
2105{
2106 struct tc35815_local *lp = netdev_priv(dev);
2107 struct tc35815_regs __iomem *tr =
2108 (struct tc35815_regs __iomem *)dev->base_addr;
2109 unsigned long txctl = TX_CTL_CMD;
2110
2111
2112 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2113
2114
2115 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2116 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2117
2118
2119 if (HAVE_DMA_RXALIGN(lp))
2120 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2121 else
2122 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2123 tc_writel(0, &tr->TxPollCtr);
2124 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2125 tc_writel(INT_EN_CMD, &tr->Int_En);
2126
2127
2128 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2129 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2130 &tr->FDA_Lim);
2131
2132
2133
2134
2135
2136 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr);
2137 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl);
2138
2139
2140
2141 if (lp->chiptype == TC35815_TX4939)
2142 txctl &= ~Tx_EnLCarr;
2143
2144 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2145 txctl &= ~Tx_EnLCarr;
2146 tc_writel(txctl, &tr->Tx_Ctl);
2147}
2148
2149#ifdef CONFIG_PM
2150static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2151{
2152 struct net_device *dev = pci_get_drvdata(pdev);
2153 struct tc35815_local *lp = netdev_priv(dev);
2154 unsigned long flags;
2155
2156 pci_save_state(pdev);
2157 if (!netif_running(dev))
2158 return 0;
2159 netif_device_detach(dev);
2160 if (lp->phy_dev)
2161 phy_stop(lp->phy_dev);
2162 spin_lock_irqsave(&lp->lock, flags);
2163 tc35815_chip_reset(dev);
2164 spin_unlock_irqrestore(&lp->lock, flags);
2165 pci_set_power_state(pdev, PCI_D3hot);
2166 return 0;
2167}
2168
2169static int tc35815_resume(struct pci_dev *pdev)
2170{
2171 struct net_device *dev = pci_get_drvdata(pdev);
2172 struct tc35815_local *lp = netdev_priv(dev);
2173
2174 pci_restore_state(pdev);
2175 if (!netif_running(dev))
2176 return 0;
2177 pci_set_power_state(pdev, PCI_D0);
2178 tc35815_restart(dev);
2179 netif_carrier_off(dev);
2180 if (lp->phy_dev)
2181 phy_start(lp->phy_dev);
2182 netif_device_attach(dev);
2183 return 0;
2184}
2185#endif
2186
2187static struct pci_driver tc35815_pci_driver = {
2188 .name = MODNAME,
2189 .id_table = tc35815_pci_tbl,
2190 .probe = tc35815_init_one,
2191 .remove = tc35815_remove_one,
2192#ifdef CONFIG_PM
2193 .suspend = tc35815_suspend,
2194 .resume = tc35815_resume,
2195#endif
2196};
2197
2198module_param_named(speed, options.speed, int, 0);
2199MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2200module_param_named(duplex, options.duplex, int, 0);
2201MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2202
2203module_pci_driver(tc35815_pci_driver);
2204MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2205MODULE_LICENSE("GPL");
2206