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17#ifndef WIL6210_TXRX_H
18#define WIL6210_TXRX_H
19
20#define BUF_SW_OWNED (1)
21#define BUF_HW_OWNED (0)
22
23
24#define RX_BUF_LEN (2048)
25#define TX_BUF_LEN (2048)
26
27#define WIL6210_RTAP_SIZE (128)
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33
34struct vring_dma_addr {
35 __le32 addr_low;
36 __le16 addr_high;
37} __packed;
38
39static inline dma_addr_t wil_desc_addr(struct vring_dma_addr *addr)
40{
41 return le32_to_cpu(addr->addr_low) |
42 ((u64)le16_to_cpu(addr->addr_high) << 32);
43}
44
45static inline void wil_desc_addr_set(struct vring_dma_addr *addr,
46 dma_addr_t pa)
47{
48 addr->addr_low = cpu_to_le32(lower_32_bits(pa));
49 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa));
50}
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90struct vring_tx_mac {
91 u32 d[3];
92 u32 ucode_cmd;
93} __packed;
94
95
96#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
97#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
98#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
99
100#define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
101#define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
102#define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
103
104#define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
105#define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
106#define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
107
108#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
109#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
110#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
111
112#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
113#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
114#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
115
116#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
117#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
118#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
119
120#define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
121#define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
122#define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
123
124#define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
125#define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
126#define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
127
128#define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
129#define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
130#define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
131
132
133#define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
134#define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
135#define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
136
137#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
138#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
139#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
140
141#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
142#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
143#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
144
145#define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
146#define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
147#define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
148
149#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
150#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
151#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
152
153#define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
154#define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
155#define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
156
157#define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
158#define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
159#define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
160
161#define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
162#define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
163#define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
164
165#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
166#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
167#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
168
169
170#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
171#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
172#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
173
174#define MAC_CFG_DESC_TX_2_RESERVED_POS 8
175#define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
176#define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
177
178#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
179#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
180#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
181
182#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
183#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
184#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
185
186#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
187#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
188#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
189
190
191#define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
192#define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
193#define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
194
195
196#define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
197#define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
198#define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
199
200#define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
201#define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
202#define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
203
204#define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9
205#define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1
206#define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200
207
208#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
209#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
210#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
211
212#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
213#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
214#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
215
216#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
217#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
218#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
219
220#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
221#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
222#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
223
224#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
225#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
226#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
227
228#define DMA_CFG_DESC_TX_0_QID_POS 16
229#define DMA_CFG_DESC_TX_0_QID_LEN 5
230#define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
231
232#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
233#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
234#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
235
236#define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
237#define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
238#define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000
239
240
241#define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0
242#define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7
243#define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F
244
245#define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7
246#define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1
247#define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80
248
249
250#define TX_DMA_STATUS_DU BIT(0)
251
252struct vring_tx_dma {
253 u32 d0;
254 struct vring_dma_addr addr;
255 u8 ip_length;
256 u8 b11;
257 u8 error;
258 u8 status;
259 __le16 length;
260} __packed;
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305struct vring_rx_mac {
306 u32 d0;
307 u32 d1;
308 u16 w4;
309 u16 pn_15_0;
310 u32 pn_47_16;
311} __packed;
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344#define RX_DMA_D0_CMD_DMA_IT BIT(10)
345
346
347#define RX_DMA_ERROR_L3_ERR BIT(4)
348#define RX_DMA_ERROR_L4_ERR BIT(5)
349
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351
352#define RX_DMA_STATUS_DU BIT(0)
353#define RX_DMA_STATUS_ERROR BIT(2)
354
355#define RX_DMA_STATUS_L3_IDENT BIT(4)
356#define RX_DMA_STATUS_L4_IDENT BIT(5)
357#define RX_DMA_STATUS_PHY_INFO BIT(6)
358
359struct vring_rx_dma {
360 u32 d0;
361 struct vring_dma_addr addr;
362 u8 ip_length;
363 u8 b11;
364 u8 error;
365 u8 status;
366 __le16 length;
367} __packed;
368
369struct vring_tx_desc {
370 struct vring_tx_mac mac;
371 struct vring_tx_dma dma;
372} __packed;
373
374struct vring_rx_desc {
375 struct vring_rx_mac mac;
376 struct vring_rx_dma dma;
377} __packed;
378
379union vring_desc {
380 struct vring_tx_desc tx;
381 struct vring_rx_desc rx;
382} __packed;
383
384static inline int wil_rxdesc_tid(struct vring_rx_desc *d)
385{
386 return WIL_GET_BITS(d->mac.d0, 0, 3);
387}
388
389static inline int wil_rxdesc_cid(struct vring_rx_desc *d)
390{
391 return WIL_GET_BITS(d->mac.d0, 4, 6);
392}
393
394static inline int wil_rxdesc_mid(struct vring_rx_desc *d)
395{
396 return WIL_GET_BITS(d->mac.d0, 8, 9);
397}
398
399static inline int wil_rxdesc_ftype(struct vring_rx_desc *d)
400{
401 return WIL_GET_BITS(d->mac.d0, 10, 11);
402}
403
404static inline int wil_rxdesc_subtype(struct vring_rx_desc *d)
405{
406 return WIL_GET_BITS(d->mac.d0, 12, 15);
407}
408
409static inline int wil_rxdesc_seq(struct vring_rx_desc *d)
410{
411 return WIL_GET_BITS(d->mac.d0, 16, 27);
412}
413
414static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d)
415{
416 return WIL_GET_BITS(d->mac.d0, 28, 31);
417}
418
419static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d)
420{
421 return WIL_GET_BITS(d->mac.d1, 8, 9);
422}
423
424static inline int wil_rxdesc_mcs(struct vring_rx_desc *d)
425{
426 return WIL_GET_BITS(d->mac.d1, 21, 24);
427}
428
429static inline int wil_rxdesc_phy_length(struct vring_rx_desc *d)
430{
431 return WIL_GET_BITS(d->dma.d0, 16, 29);
432}
433
434static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb)
435{
436 return (void *)skb->cb;
437}
438
439#endif
440