LXR linux/drivers/net/wireless/ti/wlcore/wlcore.h

   1/*
   2 * This file is part of wlcore
   3 *
   4 * Copyright (C) 2011 Texas Instruments Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * version 2 as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18 * 02110-1301 USA
  19 *
  20 */
  21
  22#ifndef __WLCORE_H__
  23#define __WLCORE_H__
  24
  25#include <linux/platform_device.h>
  26
  27#include "wlcore_i.h"
  28#include "event.h"
  29#include "boot.h"
  30
  31/* The maximum number of Tx descriptors in all chip families */
  32#define WLCORE_MAX_TX_DESCRIPTORS 32
  33
  34/*
  35 * We always allocate this number of mac addresses. If we don't
  36 * have enough allocated addresses, the LAA bit is used
  37 */
  38#define WLCORE_NUM_MAC_ADDRESSES 3
  39
  40/* wl12xx/wl18xx maximum transmission power (in dBm) */
  41#define WLCORE_MAX_TXPWR        25
  42
  43/* forward declaration */
  44struct wl1271_tx_hw_descr;
  45enum wl_rx_buf_align;
  46struct wl1271_rx_descriptor;
  47
  48struct wlcore_ops {
  49        int (*setup)(struct wl1271 *wl);
  50        int (*identify_chip)(struct wl1271 *wl);
  51        int (*identify_fw)(struct wl1271 *wl);
  52        int (*boot)(struct wl1271 *wl);
  53        int (*plt_init)(struct wl1271 *wl);
  54        int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
  55                           void *buf, size_t len);
  56        int (*ack_event)(struct wl1271 *wl);
  57        int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
  58                              bool *timeout);
  59        int (*process_mailbox_events)(struct wl1271 *wl);
  60        u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
  61        void (*set_tx_desc_blocks)(struct wl1271 *wl,
  62                                   struct wl1271_tx_hw_descr *desc,
  63                                   u32 blks, u32 spare_blks);
  64        void (*set_tx_desc_data_len)(struct wl1271 *wl,
  65                                     struct wl1271_tx_hw_descr *desc,
  66                                     struct sk_buff *skb);
  67        enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
  68                                                 u32 rx_desc);
  69        int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
  70        u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
  71                                 u32 data_len);
  72        int (*tx_delayed_compl)(struct wl1271 *wl);
  73        void (*tx_immediate_compl)(struct wl1271 *wl);
  74        int (*hw_init)(struct wl1271 *wl);
  75        int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
  76        u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
  77                                    struct wl12xx_vif *wlvif);
  78        int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
  79        int (*get_mac)(struct wl1271 *wl);
  80        void (*set_tx_desc_csum)(struct wl1271 *wl,
  81                                 struct wl1271_tx_hw_descr *desc,
  82                                 struct sk_buff *skb);
  83        void (*set_rx_csum)(struct wl1271 *wl,
  84                            struct wl1271_rx_descriptor *desc,
  85                            struct sk_buff *skb);
  86        u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
  87                                          struct wl12xx_vif *wlvif);
  88        int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
  89        int (*handle_static_data)(struct wl1271 *wl,
  90                                  struct wl1271_static_data *static_data);
  91        int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
  92                          struct cfg80211_scan_request *req);
  93        int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
  94        int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
  95                                struct cfg80211_sched_scan_request *req,
  96                                struct ieee80211_sched_scan_ies *ies);
  97        void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
  98        int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
  99        int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
 100                       struct ieee80211_vif *vif,
 101                       struct ieee80211_sta *sta,
 102                       struct ieee80211_key_conf *key_conf);
 103        int (*channel_switch)(struct wl1271 *wl,
 104                              struct wl12xx_vif *wlvif,
 105                              struct ieee80211_channel_switch *ch_switch);
 106        u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
 107        void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
 108                              struct ieee80211_sta *sta, u32 changed);
 109        int (*set_peer_cap)(struct wl1271 *wl,
 110                            struct ieee80211_sta_ht_cap *ht_cap,
 111                            bool allow_ht_operation,
 112                            u32 rate_set, u8 hlid);
 113        u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr);
 114        bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid,
 115                              struct wl1271_link *lnk);
 116        bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid,
 117                             struct wl1271_link *lnk);
 118};
 119
 120enum wlcore_partitions {
 121        PART_DOWN,
 122        PART_WORK,
 123        PART_BOOT,
 124        PART_DRPW,
 125        PART_TOP_PRCM_ELP_SOC,
 126        PART_PHY_INIT,
 127
 128        PART_TABLE_LEN,
 129};
 130
 131struct wlcore_partition {
 132        u32 size;
 133        u32 start;
 134};
 135
 136struct wlcore_partition_set {
 137        struct wlcore_partition mem;
 138        struct wlcore_partition reg;
 139        struct wlcore_partition mem2;
 140        struct wlcore_partition mem3;
 141};
 142
 143enum wlcore_registers {
 144        /* register addresses, used with partition translation */
 145        REG_ECPU_CONTROL,
 146        REG_INTERRUPT_NO_CLEAR,
 147        REG_INTERRUPT_ACK,
 148        REG_COMMAND_MAILBOX_PTR,
 149        REG_EVENT_MAILBOX_PTR,
 150        REG_INTERRUPT_TRIG,
 151        REG_INTERRUPT_MASK,
 152        REG_PC_ON_RECOVERY,
 153        REG_CHIP_ID_B,
 154        REG_CMD_MBOX_ADDRESS,
 155
 156        /* data access memory addresses, used with partition translation */
 157        REG_SLV_MEM_DATA,
 158        REG_SLV_REG_DATA,
 159
 160        /* raw data access memory addresses */
 161        REG_RAW_FW_STATUS_ADDR,
 162
 163        REG_TABLE_LEN,
 164};
 165
 166struct wl1271_stats {
 167        void *fw_stats;
 168        unsigned long fw_stats_update;
 169        size_t fw_stats_len;
 170
 171        unsigned int retry_count;
 172        unsigned int excessive_retries;
 173};
 174
 175struct wl1271 {
 176        bool initialized;
 177        struct ieee80211_hw *hw;
 178        bool mac80211_registered;
 179
 180        struct device *dev;
 181        struct platform_device *pdev;
 182
 183        void *if_priv;
 184
 185        struct wl1271_if_operations *if_ops;
 186
 187        int irq;
 188
 189        spinlock_t wl_lock;
 190
 191        enum wlcore_state state;
 192        enum wl12xx_fw_type fw_type;
 193        bool plt;
 194        enum plt_mode plt_mode;
 195        u8 fem_manuf;
 196        u8 last_vif_count;
 197        struct mutex mutex;
 198
 199        unsigned long flags;
 200
 201        struct wlcore_partition_set curr_part;
 202
 203        struct wl1271_chip chip;
 204
 205        int cmd_box_addr;
 206
 207        u8 *fw;
 208        size_t fw_len;
 209        void *nvs;
 210        size_t nvs_len;
 211
 212        s8 hw_pg_ver;
 213
 214        /* address read from the fuse ROM */
 215        u32 fuse_oui_addr;
 216        u32 fuse_nic_addr;
 217
 218        /* we have up to 2 MAC addresses */
 219        struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
 220        int channel;
 221        u8 system_hlid;
 222
 223        unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
 224        unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
 225        unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
 226        unsigned long rate_policies_map[
 227                        BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
 228        unsigned long klv_templates_map[
 229                        BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
 230
 231        u8 session_ids[WL12XX_MAX_LINKS];
 232
 233        struct list_head wlvif_list;
 234
 235        u8 sta_count;
 236        u8 ap_count;
 237
 238        struct wl1271_acx_mem_map *target_mem_map;
 239
 240        /* Accounting for allocated / available TX blocks on HW */
 241        u32 tx_blocks_freed;
 242        u32 tx_blocks_available;
 243        u32 tx_allocated_blocks;
 244        u32 tx_results_count;
 245
 246        /* Accounting for allocated / available Tx packets in HW */
 247        u32 tx_pkts_freed[NUM_TX_QUEUES];
 248        u32 tx_allocated_pkts[NUM_TX_QUEUES];
 249
 250        /* Transmitted TX packets counter for chipset interface */
 251        u32 tx_packets_count;
 252
 253        /* Time-offset between host and chipset clocks */
 254        s64 time_offset;
 255
 256        /* Frames scheduled for transmission, not handled yet */
 257        int tx_queue_count[NUM_TX_QUEUES];
 258        unsigned long queue_stop_reasons[
 259                                NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES];
 260
 261        /* Frames received, not handled yet by mac80211 */
 262        struct sk_buff_head deferred_rx_queue;
 263
 264        /* Frames sent, not returned yet to mac80211 */
 265        struct sk_buff_head deferred_tx_queue;
 266
 267        struct work_struct tx_work;
 268        struct workqueue_struct *freezable_wq;
 269
 270        /* Pending TX frames */
 271        unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
 272        struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
 273        int tx_frames_cnt;
 274
 275        /* FW Rx counter */
 276        u32 rx_counter;
 277
 278        /* Intermediate buffer, used for packet aggregation */
 279        u8 *aggr_buf;
 280        u32 aggr_buf_size;
 281
 282        /* Reusable dummy packet template */
 283        struct sk_buff *dummy_packet;
 284
 285        /* Network stack work  */
 286        struct work_struct netstack_work;
 287
 288        /* FW log buffer */
 289        u8 *fwlog;
 290
 291        /* Number of valid bytes in the FW log buffer */
 292        ssize_t fwlog_size;
 293
 294        /* FW log end marker */
 295        u32 fwlog_end;
 296
 297        /* FW memory block size */
 298        u32 fw_mem_block_size;
 299
 300        /* Sysfs FW log entry readers wait queue */
 301        wait_queue_head_t fwlog_waitq;
 302
 303        /* Hardware recovery work */
 304        struct work_struct recovery_work;
 305        bool watchdog_recovery;
 306
 307        /* Reg domain last configuration */
 308        u32 reg_ch_conf_last[2];
 309        /* Reg domain pending configuration */
 310        u32 reg_ch_conf_pending[2];
 311
 312        /* Pointer that holds DMA-friendly block for the mailbox */
 313        void *mbox;
 314
 315        /* The mbox event mask */
 316        u32 event_mask;
 317        /* events to unmask only when ap interface is up */
 318        u32 ap_event_mask;
 319
 320        /* Mailbox pointers */
 321        u32 mbox_size;
 322        u32 mbox_ptr[2];
 323
 324        /* Are we currently scanning */
 325        struct wl12xx_vif *scan_wlvif;
 326        struct wl1271_scan scan;
 327        struct delayed_work scan_complete_work;
 328
 329        struct ieee80211_vif *roc_vif;
 330        struct delayed_work roc_complete_work;
 331
 332        struct wl12xx_vif *sched_vif;
 333
 334        /* The current band */
 335        enum ieee80211_band band;
 336
 337        struct completion *elp_compl;
 338        struct delayed_work elp_work;
 339
 340        /* in dBm */
 341        int power_level;
 342
 343        struct wl1271_stats stats;
 344
 345        __le32 *buffer_32;
 346        u32 buffer_cmd;
 347        u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
 348
 349        struct wl_fw_status_1 *fw_status_1;
 350        struct wl_fw_status_2 *fw_status_2;
 351        struct wl1271_tx_hw_res_if *tx_res_if;
 352
 353        /* Current chipset configuration */
 354        struct wlcore_conf conf;
 355
 356        bool sg_enabled;
 357
 358        bool enable_11a;
 359
 360        int recovery_count;
 361
 362        /* Most recently reported noise in dBm */
 363        s8 noise;
 364
 365        /* bands supported by this instance of wl12xx */
 366        struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
 367
 368        /*
 369         * wowlan trigger was configured during suspend.
 370         * (currently, only "ANY" trigger is supported)
 371         */
 372        bool wow_enabled;
 373        bool irq_wake_enabled;
 374
 375        /*
 376         * AP-mode - links indexed by HLID. The global and broadcast links
 377         * are always active.
 378         */
 379        struct wl1271_link links[WL12XX_MAX_LINKS];
 380
 381        /* number of currently active links */
 382        int active_link_count;
 383
 384        /* Fast/slow links bitmap according to FW */
 385        u32 fw_fast_lnk_map;
 386
 387        /* AP-mode - a bitmap of links currently in PS mode according to FW */
 388        u32 ap_fw_ps_map;
 389
 390        /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
 391        unsigned long ap_ps_map;
 392
 393        /* Quirks of specific hardware revisions */
 394        unsigned int quirks;
 395
 396        /* Platform limitations */
 397        unsigned int platform_quirks;
 398
 399        /* number of currently active RX BA sessions */
 400        int ba_rx_session_count;
 401
 402        /* Maximum number of supported RX BA sessions */
 403        int ba_rx_session_count_max;
 404
 405        /* AP-mode - number of currently connected stations */
 406        int active_sta_count;
 407
 408        /* last wlvif we transmitted from */
 409        struct wl12xx_vif *last_wlvif;
 410
 411        /* work to fire when Tx is stuck */
 412        struct delayed_work tx_watchdog_work;
 413
 414        struct wlcore_ops *ops;
 415        /* pointer to the lower driver partition table */
 416        const struct wlcore_partition_set *ptable;
 417        /* pointer to the lower driver register table */
 418        const int *rtable;
 419        /* name of the firmwares to load - for PLT, single role, multi-role */
 420        const char *plt_fw_name;
 421        const char *sr_fw_name;
 422        const char *mr_fw_name;
 423
 424        u8 scan_templ_id_2_4;
 425        u8 scan_templ_id_5;
 426        u8 sched_scan_templ_id_2_4;
 427        u8 sched_scan_templ_id_5;
 428        u8 max_channels_5;
 429
 430        /* per-chip-family private structure */
 431        void *priv;
 432
 433        /* number of TX descriptors the HW supports. */
 434        u32 num_tx_desc;
 435        /* number of RX descriptors the HW supports. */
 436        u32 num_rx_desc;
 437
 438        /* translate HW Tx rates to standard rate-indices */
 439        const u8 **band_rate_to_idx;
 440
 441        /* size of table for HW rates that can be received from chip */
 442        u8 hw_tx_rate_tbl_size;
 443
 444        /* this HW rate and below are considered HT rates for this chip */
 445        u8 hw_min_ht_rate;
 446
 447        /* HW HT (11n) capabilities */
 448        struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
 449
 450        /* size of the private FW status data */
 451        size_t fw_status_priv_len;
 452
 453        /* RX Data filter rule state - enabled/disabled */
 454        bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
 455
 456        /* size of the private static data */
 457        size_t static_data_priv_len;
 458
 459        /* the current channel type */
 460        enum nl80211_channel_type channel_type;
 461
 462        /* mutex for protecting the tx_flush function */
 463        struct mutex flush_mutex;
 464
 465        /* sleep auth value currently configured to FW */
 466        int sleep_auth;
 467
 468        /* the number of allocated MAC addresses in this chip */
 469        int num_mac_addr;
 470
 471        /* minimum FW version required for the driver to work in single-role */
 472        unsigned int min_sr_fw_ver[NUM_FW_VER];
 473
 474        /* minimum FW version required for the driver to work in multi-role */
 475        unsigned int min_mr_fw_ver[NUM_FW_VER];
 476
 477        struct completion nvs_loading_complete;
 478
 479        /* number of concurrent channels the HW supports */
 480        u32 num_channels;
 481};
 482
 483int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
 484int wlcore_remove(struct platform_device *pdev);
 485struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
 486                                     u32 mbox_size);
 487int wlcore_free_hw(struct wl1271 *wl);
 488int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
 489                   struct ieee80211_vif *vif,
 490                   struct ieee80211_sta *sta,
 491                   struct ieee80211_key_conf *key_conf);
 492void wlcore_regdomain_config(struct wl1271 *wl);
 493void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif,
 494                              struct wl1271_station *wl_sta, bool in_conn);
 495
 496static inline void
 497wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
 498                  struct ieee80211_sta_ht_cap *ht_cap)
 499{
 500        memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
 501}
 502
 503/* Tell wlcore not to care about this element when checking the version */
 504#define WLCORE_FW_VER_IGNORE    -1
 505
 506static inline void
 507wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
 508                      unsigned int iftype_sr, unsigned int major_sr,
 509                      unsigned int subtype_sr, unsigned int minor_sr,
 510                      unsigned int iftype_mr, unsigned int major_mr,
 511                      unsigned int subtype_mr, unsigned int minor_mr)
 512{
 513        wl->min_sr_fw_ver[FW_VER_CHIP] = chip;
 514        wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr;
 515        wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr;
 516        wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr;
 517        wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr;
 518
 519        wl->min_mr_fw_ver[FW_VER_CHIP] = chip;
 520        wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr;
 521        wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr;
 522        wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr;
 523        wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr;
 524}
 525
 526/* Firmware image load chunk size */
 527#define CHUNK_SIZE      16384
 528
 529/* Quirks */
 530
 531/* Each RX/TX transaction requires an end-of-transaction transfer */
 532#define WLCORE_QUIRK_END_OF_TRANSACTION         BIT(0)
 533
 534/* the first start_role(sta) sometimes doesn't work on wl12xx */
 535#define WLCORE_QUIRK_START_STA_FAILS            BIT(1)
 536
 537/* wl127x and SPI don't support SDIO block size alignment */
 538#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN         BIT(2)
 539
 540/* means aggregated Rx packets are aligned to a SDIO block */
 541#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN         BIT(3)
 542
 543/* Older firmwares did not implement the FW logger over bus feature */
 544#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED      BIT(4)
 545
 546/* Older firmwares use an old NVS format */
 547#define WLCORE_QUIRK_LEGACY_NVS                 BIT(5)
 548
 549/* pad only the last frame in the aggregate buffer */
 550#define WLCORE_QUIRK_TX_PAD_LAST_FRAME          BIT(7)
 551
 552/* extra header space is required for TKIP */
 553#define WLCORE_QUIRK_TKIP_HEADER_SPACE          BIT(8)
 554
 555/* Some firmwares not support sched scans while connected */
 556#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN   BIT(9)
 557
 558/* separate probe response templates for one-shot and sched scans */
 559#define WLCORE_QUIRK_DUAL_PROBE_TMPL            BIT(10)
 560
 561/* Firmware requires reg domain configuration for active calibration */
 562#define WLCORE_QUIRK_REGDOMAIN_CONF             BIT(11)
 563
 564/* The FW only support a zero session id for AP */
 565#define WLCORE_QUIRK_AP_ZERO_SESSION_ID         BIT(12)
 566
 567/* TODO: move all these common registers and values elsewhere */
 568#define HW_ACCESS_ELP_CTRL_REG          0x1FFFC
 569
 570/* ELP register commands */
 571#define ELPCTRL_WAKE_UP             0x1
 572#define ELPCTRL_WAKE_UP_WLAN_READY  0x5
 573#define ELPCTRL_SLEEP               0x0
 574/* ELP WLAN_READY bit */
 575#define ELPCTRL_WLAN_READY          0x2
 576
 577/*************************************************************************
 578
 579    Interrupt Trigger Register (Host -> WiLink)
 580
 581**************************************************************************/
 582
 583/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
 584
 585/*
 586 * The host sets this bit to inform the Wlan
 587 * FW that a TX packet is in the XFER
 588 * Buffer #0.
 589 */
 590#define INTR_TRIG_TX_PROC0 BIT(2)
 591
 592/*
 593 * The host sets this bit to inform the FW
 594 * that it read a packet from RX XFER
 595 * Buffer #0.
 596 */
 597#define INTR_TRIG_RX_PROC0 BIT(3)
 598
 599#define INTR_TRIG_DEBUG_ACK BIT(4)
 600
 601#define INTR_TRIG_STATE_CHANGED BIT(5)
 602
 603/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
 604
 605/*
 606 * The host sets this bit to inform the FW
 607 * that it read a packet from RX XFER
 608 * Buffer #1.
 609 */
 610#define INTR_TRIG_RX_PROC1 BIT(17)
 611
 612/*
 613 * The host sets this bit to inform the Wlan
 614 * hardware that a TX packet is in the XFER
 615 * Buffer #1.
 616 */
 617#define INTR_TRIG_TX_PROC1 BIT(18)
 618
 619#define ACX_SLV_SOFT_RESET_BIT  BIT(1)
 620#define SOFT_RESET_MAX_TIME     1000000
 621#define SOFT_RESET_STALL_TIME   1000
 622
 623#define ECPU_CONTROL_HALT       0x00000101
 624
 625#define WELP_ARM_COMMAND_VAL    0x4
 626
 627#endif /* __WLCORE_H__ */
 628