linux/drivers/staging/dgap/dgap_fep5.h
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   1/*
   2 * Copyright 2003 Digi International (www.digi.com)
   3 *      Scott H Kilau <Scott_Kilau at digi dot com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2, or (at your option)
   8 * any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  13 * PURPOSE.  See the GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 *
  19 *      NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!!
  20 *
  21 ************************************************************************ 
  22 ***    FEP Version 5 dependent definitions
  23 ************************************************************************/
  24
  25#ifndef __DGAP_FEP5_H
  26#define __DGAP_FEP5_H
  27
  28/************************************************************************
  29 *      FEP memory offsets
  30 ************************************************************************/
  31#define START           0x0004L         /* Execution start address      */
  32
  33#define CMDBUF          0x0d10L         /* Command (cm_t) structure offset */
  34#define CMDSTART        0x0400L         /* Start of command buffer      */   
  35#define CMDMAX          0x0800L         /* End of command buffer        */
  36
  37#define EVBUF           0x0d18L         /* Event (ev_t) structure       */
  38#define EVSTART         0x0800L         /* Start of event buffer        */
  39#define EVMAX           0x0c00L         /* End of event buffer          */
  40#define FEP5_PLUS       0x0E40          /* ASCII '5' and ASCII 'A' is here  */
  41#define ECS_SEG         0x0E44          /* Segment of the extended channel structure */
  42#define LINE_SPEED      0x10            /* Offset into ECS_SEG for line speed   */
  43                                        /* if the fep has extended capabilities */
  44
  45/* BIOS MAGIC SPOTS */
  46#define ERROR           0x0C14L         /* BIOS error code              */
  47#define SEQUENCE        0x0C12L         /* BIOS sequence indicator      */
  48#define POSTAREA        0x0C00L         /* POST complete message area   */
  49
  50/* FEP MAGIC SPOTS */
  51#define FEPSTAT         POSTAREA        /* OS here when FEP comes up    */
  52#define NCHAN           0x0C02L         /* number of ports FEP sees     */
  53#define PANIC           0x0C10L         /* PANIC area for FEP           */
  54#define KMEMEM          0x0C30L         /* Memory for KME use           */   
  55#define CONFIG          0x0CD0L         /* Concentrator configuration info */
  56#define CONFIGSIZE      0x0030          /* configuration info size      */
  57#define DOWNREQ         0x0D00          /* Download request buffer pointer */
  58
  59#define CHANBUF         0x1000L         /* Async channel (bs_t) structs */
  60#define FEPOSSIZE       0x1FFF          /* 8K FEPOS                     */
  61
  62#define XEMPORTS    0xC02       /*
  63                                 * Offset in board memory where FEP5 stores
  64                                 * how many ports it has detected.
  65                                 * NOTE: FEP5 reports 64 ports when the user
  66                                 * has the cable in EBI OUT instead of EBI IN.
  67                                 */
  68
  69#define FEPCLR      0x00
  70#define FEPMEM      0x02 
  71#define FEPRST      0x04 
  72#define FEPINT      0x08
  73#define FEPMASK     0x0e
  74#define FEPWIN      0x80
  75
  76#define LOWMEM      0x0100
  77#define HIGHMEM     0x7f00
  78
  79#define FEPTIMEOUT 200000
  80
  81#define ENABLE_INTR             0x0e04          /* Enable interrupts flag */
  82#define FEPPOLL_MIN             1               /* minimum of 1 millisecond */  
  83#define FEPPOLL_MAX             20              /* maximum of 20 milliseconds */
  84#define FEPPOLL                 0x0c26          /* Fep event poll interval */   
  85
  86#define IALTPIN                 0x0080          /* Input flag to swap DSR <-> DCD */
  87
  88/************************************************************************ 
  89 * Command structure definition.
  90 ************************************************************************/
  91struct cm_t {
  92        volatile unsigned short cm_head;        /* Command buffer head offset   */
  93        volatile unsigned short cm_tail;        /* Command buffer tail offset   */
  94        volatile unsigned short cm_start;       /* start offset of buffer       */
  95        volatile unsigned short cm_max;         /* last offset of buffer        */
  96};
  97
  98/************************************************************************
  99 * Event structure definition.
 100 ************************************************************************/
 101struct ev_t {
 102        volatile unsigned short ev_head;        /* Command buffer head offset   */
 103        volatile unsigned short ev_tail;        /* Command buffer tail offset   */
 104        volatile unsigned short ev_start;       /* start offset of buffer       */
 105        volatile unsigned short ev_max;         /* last offset of buffer        */
 106};
 107
 108/************************************************************************
 109 * Download buffer structure.
 110 ************************************************************************/
 111struct downld_t {
 112        uchar   dl_type;                /* Header                       */
 113        uchar   dl_seq;                 /* Download sequence            */
 114        ushort  dl_srev;                /* Software revision number     */
 115        ushort  dl_lrev;                /* Low revision number          */
 116        ushort  dl_hrev;                /* High revision number         */
 117        ushort  dl_seg;                 /* Start segment address        */
 118        ushort  dl_size;                /* Number of bytes to download  */
 119        uchar   dl_data[1024];          /* Download data                */
 120};
 121
 122/************************************************************************ 
 123 * Per channel buffer structure
 124 ************************************************************************
 125 *              Base Structure Entries Usage Meanings to Host           * 
 126 *                                                                      * 
 127 *        W = read write        R = read only                           * 
 128 *        C = changed by commands only                                  * 
 129 *        U = unknown (may be changed w/o notice)                       *
 130 ************************************************************************/
 131struct bs_t {
 132        volatile unsigned short  tp_jmp;        /* Transmit poll jump            */
 133        volatile unsigned short  tc_jmp;        /* Cooked procedure jump         */
 134        volatile unsigned short  ri_jmp;        /* Not currently used            */
 135        volatile unsigned short  rp_jmp;        /* Receive poll jump             */
 136
 137        volatile unsigned short  tx_seg;        /* W  Tx segment         */
 138        volatile unsigned short  tx_head;       /* W  Tx buffer head offset     */
 139        volatile unsigned short  tx_tail;       /* R  Tx buffer tail offset     */
 140        volatile unsigned short  tx_max;        /* W  Tx buffer size - 1         */
 141 
 142        volatile unsigned short  rx_seg;        /* W  Rx segment                */
 143        volatile unsigned short  rx_head;       /* W  Rx buffer head offset     */
 144        volatile unsigned short  rx_tail;       /* R  Rx buffer tail offset     */
 145        volatile unsigned short  rx_max;        /* W  Rx buffer size - 1         */
 146
 147        volatile unsigned short  tx_lw;         /* W  Tx buffer low water mark  */
 148        volatile unsigned short  rx_lw;         /* W  Rx buffer low water mark  */
 149        volatile unsigned short  rx_hw;         /* W  Rx buffer high water mark */
 150        volatile unsigned short  incr;          /* W  Increment to next channel */
 151
 152        volatile unsigned short  fepdev;        /* U  SCC device base address    */
 153        volatile unsigned short  edelay;        /* W  Exception delay            */
 154        volatile unsigned short  blen;          /* W  Break length              */
 155        volatile unsigned short  btime;         /* U  Break complete time       */
 156
 157        volatile unsigned short  iflag;         /* C  UNIX input flags          */
 158        volatile unsigned short  oflag;         /* C  UNIX output flags         */
 159        volatile unsigned short  cflag;         /* C  UNIX control flags        */
 160        volatile unsigned short  wfill[13];     /* U  Reserved for expansion    */
 161
 162        volatile unsigned char   num;           /* U  Channel number            */
 163        volatile unsigned char   ract;          /* U  Receiver active counter   */
 164        volatile unsigned char   bstat;         /* U  Break status bits         */
 165        volatile unsigned char   tbusy;         /* W  Transmit busy             */
 166        volatile unsigned char   iempty;        /* W  Transmit empty event enable */
 167        volatile unsigned char   ilow;          /* W  Transmit low-water event enable */
 168        volatile unsigned char   idata;         /* W  Receive data interrupt enable */
 169        volatile unsigned char   eflag;         /* U  Host event flags          */
 170
 171        volatile unsigned char   tflag;         /* U  Transmit flags            */
 172        volatile unsigned char   rflag;         /* U  Receive flags             */
 173        volatile unsigned char   xmask;         /* U  Transmit ready flags      */
 174        volatile unsigned char   xval;          /* U  Transmit ready value      */
 175        volatile unsigned char   m_stat;        /* RC Modem status bits          */
 176        volatile unsigned char   m_change;      /* U  Modem bits which changed  */
 177        volatile unsigned char   m_int;         /* W  Modem interrupt enable bits */
 178        volatile unsigned char   m_last;        /* U  Last modem status         */
 179
 180        volatile unsigned char   mtran;         /* C   Unreported modem trans   */
 181        volatile unsigned char   orun;          /* C   Buffer overrun occurred  */
 182        volatile unsigned char   astartc;       /* W   Auxiliary Xon char       */  
 183        volatile unsigned char   astopc;        /* W   Auxiliary Xoff char      */
 184        volatile unsigned char   startc;        /* W   Xon character             */
 185        volatile unsigned char   stopc;         /* W   Xoff character           */
 186        volatile unsigned char   vnextc;        /* W   Vnext character           */
 187        volatile unsigned char   hflow;         /* C   Software flow control    */
 188
 189        volatile unsigned char   fillc;         /* U   Delay Fill character     */
 190        volatile unsigned char   ochar;         /* U   Saved output character   */
 191        volatile unsigned char   omask;         /* U   Output character mask    */
 192
 193        volatile unsigned char   bfill[13];     /* U   Reserved for expansion   */  
 194
 195        volatile unsigned char   scc[16];       /* U   SCC registers            */
 196};
 197
 198
 199/************************************************************************   
 200 * FEP supported functions
 201 ************************************************************************/
 202#define SRLOW           0xe0            /* Set receive low water        */
 203#define SRHIGH          0xe1            /* Set receive high water       */
 204#define FLUSHTX         0xe2            /* Flush transmit buffer        */
 205#define PAUSETX         0xe3            /* Pause data transmission      */
 206#define RESUMETX        0xe4            /* Resume data transmission     */
 207#define SMINT           0xe5            /* Set Modem Interrupt          */
 208#define SAFLOWC         0xe6            /* Set Aux. flow control chars  */
 209#define SBREAK          0xe8            /* Send break                   */
 210#define SMODEM          0xe9            /* Set 8530 modem control lines */  
 211#define SIFLAG          0xea            /* Set UNIX iflags              */
 212#define SFLOWC          0xeb            /* Set flow control characters  */
 213#define STLOW           0xec            /* Set transmit low water mark  */
 214#define RPAUSE          0xee            /* Pause receive                */
 215#define RRESUME         0xef            /* Resume receive               */  
 216#define CHRESET         0xf0            /* Reset Channel                */
 217#define BUFSETALL       0xf2            /* Set Tx & Rx buffer size avail*/
 218#define SOFLAG          0xf3            /* Set UNIX oflags              */
 219#define SHFLOW          0xf4            /* Set hardware handshake       */
 220#define SCFLAG          0xf5            /* Set UNIX cflags              */
 221#define SVNEXT          0xf6            /* Set VNEXT character          */
 222#define SPINTFC         0xfc            /* Reserved                     */
 223#define SCOMMODE        0xfd            /* Set RS232/422 mode           */
 224
 225
 226/************************************************************************ 
 227 *      Modes for SCOMMODE
 228 ************************************************************************/
 229#define MODE_232        0x00
 230#define MODE_422        0x01
 231
 232
 233/************************************************************************ 
 234 *      Event flags.
 235 ************************************************************************/
 236#define IFBREAK         0x01            /* Break received               */  
 237#define IFTLW           0x02            /* Transmit low water           */
 238#define IFTEM           0x04            /* Transmitter empty            */
 239#define IFDATA          0x08            /* Receive data present         */
 240#define IFMODEM         0x20            /* Modem status change          */
 241
 242/************************************************************************   
 243 *      Modem flags
 244 ************************************************************************/
 245#       define  DM_RTS          0x02    /* Request to send              */
 246#       define  DM_CD           0x80    /* Carrier detect               */
 247#       define  DM_DSR          0x20    /* Data set ready               */
 248#       define  DM_CTS          0x10    /* Clear to send                */
 249#       define  DM_RI           0x40    /* Ring indicator               */
 250#       define  DM_DTR          0x01    /* Data terminal ready          */
 251
 252
 253#endif
 254