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25#ifndef __TWL_H_
26#define __TWL_H_
27
28#include <linux/types.h>
29#include <linux/phy/phy.h>
30#include <linux/input/matrix_keypad.h>
31
32
33
34
35
36
37
38
39
40
41
42
43
44enum twl_module_ids {
45 TWL_MODULE_USB,
46 TWL_MODULE_PIH,
47 TWL_MODULE_MAIN_CHARGE,
48 TWL_MODULE_PM_MASTER,
49 TWL_MODULE_PM_RECEIVER,
50
51 TWL_MODULE_RTC,
52 TWL_MODULE_PWM,
53 TWL_MODULE_LED,
54 TWL_MODULE_SECURED_REG,
55
56 TWL_MODULE_LAST,
57};
58
59
60enum twl4030_module_ids {
61 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST,
62 TWL4030_MODULE_GPIO,
63 TWL4030_MODULE_INTBR,
64 TWL4030_MODULE_TEST,
65 TWL4030_MODULE_KEYPAD,
66
67 TWL4030_MODULE_MADC,
68 TWL4030_MODULE_INTERRUPTS,
69 TWL4030_MODULE_PRECHARGE,
70 TWL4030_MODULE_BACKUP,
71 TWL4030_MODULE_INT,
72
73 TWL5031_MODULE_ACCESSORY,
74 TWL5031_MODULE_INTERRUPTS,
75
76 TWL4030_MODULE_LAST,
77};
78
79
80enum twl6030_module_ids {
81 TWL6030_MODULE_ID0 = TWL_MODULE_LAST,
82 TWL6030_MODULE_ID1,
83 TWL6030_MODULE_ID2,
84 TWL6030_MODULE_GPADC,
85 TWL6030_MODULE_GASGAUGE,
86
87 TWL6030_MODULE_LAST,
88};
89
90
91#define TWL4030_MODULE_LED TWL_MODULE_LED
92
93#define GPIO_INTR_OFFSET 0
94#define KEYPAD_INTR_OFFSET 1
95#define BCI_INTR_OFFSET 2
96#define MADC_INTR_OFFSET 3
97#define USB_INTR_OFFSET 4
98#define CHARGERFAULT_INTR_OFFSET 5
99#define BCI_PRES_INTR_OFFSET 9
100#define USB_PRES_INTR_OFFSET 10
101#define RTC_INTR_OFFSET 11
102
103
104
105
106#define PWR_INTR_OFFSET 0
107#define HOTDIE_INTR_OFFSET 12
108#define SMPSLDO_INTR_OFFSET 13
109#define BATDETECT_INTR_OFFSET 14
110#define SIMDETECT_INTR_OFFSET 15
111#define MMCDETECT_INTR_OFFSET 16
112#define GASGAUGE_INTR_OFFSET 17
113#define USBOTG_INTR_OFFSET 4
114#define CHARGER_INTR_OFFSET 2
115#define RSV_INTR_OFFSET 0
116
117
118#define REG_INT_STS_A 0x00
119#define REG_INT_STS_B 0x01
120#define REG_INT_STS_C 0x02
121
122#define REG_INT_MSK_LINE_A 0x03
123#define REG_INT_MSK_LINE_B 0x04
124#define REG_INT_MSK_LINE_C 0x05
125
126#define REG_INT_MSK_STS_A 0x06
127#define REG_INT_MSK_STS_B 0x07
128#define REG_INT_MSK_STS_C 0x08
129
130
131#define TWL6030_PWR_INT_MASK 0x07
132#define TWL6030_RTC_INT_MASK 0x18
133#define TWL6030_HOTDIE_INT_MASK 0x20
134#define TWL6030_SMPSLDOA_INT_MASK 0xC0
135
136
137#define TWL6030_SMPSLDOB_INT_MASK 0x01
138#define TWL6030_BATDETECT_INT_MASK 0x02
139#define TWL6030_SIMDETECT_INT_MASK 0x04
140#define TWL6030_MMCDETECT_INT_MASK 0x08
141#define TWL6030_GPADC_INT_MASK 0x60
142#define TWL6030_GASGAUGE_INT_MASK 0x80
143
144
145#define TWL6030_USBOTG_INT_MASK 0x0F
146#define TWL6030_CHARGER_CTRL_INT_MASK 0x10
147#define TWL6030_CHARGER_FAULT_INT_MASK 0x60
148
149#define TWL6030_MMCCTRL 0xEE
150#define VMMC_AUTO_OFF (0x1 << 3)
151#define SW_FC (0x1 << 2)
152#define STS_MMC 0x1
153
154#define TWL6030_CFG_INPUT_PUPD3 0xF2
155#define MMC_PU (0x1 << 3)
156#define MMC_PD (0x1 << 2)
157
158#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
159#define TWL_SIL_REV(rev) ((rev) >> 24)
160#define TWL_SIL_5030 0x09002F
161#define TWL5030_REV_1_0 0x00
162#define TWL5030_REV_1_1 0x10
163#define TWL5030_REV_1_2 0x30
164
165#define TWL4030_CLASS_ID 0x4030
166#define TWL6030_CLASS_ID 0x6030
167unsigned int twl_rev(void);
168#define GET_TWL_REV (twl_rev())
169#define TWL_CLASS_IS(class, id) \
170static inline int twl_class_is_ ##class(void) \
171{ \
172 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
173}
174
175TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
176TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
177
178
179int twl_set_regcache_bypass(u8 mod_no, bool enable);
180
181
182
183
184int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
185int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
186
187
188
189
190static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) {
191 return twl_i2c_write(mod_no, &val, reg, 1);
192}
193
194static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) {
195 return twl_i2c_read(mod_no, val, reg, 1);
196}
197
198int twl_get_type(void);
199int twl_get_version(void);
200int twl_get_hfclk_rate(void);
201
202int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
203int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
204
205
206#ifdef CONFIG_TWL4030_CORE
207int twl6030_mmc_card_detect_config(void);
208#else
209static inline int twl6030_mmc_card_detect_config(void)
210{
211 pr_debug("twl6030_mmc_card_detect_config not supported\n");
212 return 0;
213}
214#endif
215
216
217#ifdef CONFIG_TWL4030_CORE
218int twl6030_mmc_card_detect(struct device *dev, int slot);
219#else
220static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
221{
222 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
223 return -EIO;
224}
225#endif
226
227
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233
234
235
236
237#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
238#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
239#define TWL4030_SIH_CTRL_COR_MASK BIT(2)
240
241
242
243
244
245
246
247#define REG_GPIODATAIN1 0x0
248#define REG_GPIODATAIN2 0x1
249#define REG_GPIODATAIN3 0x2
250#define REG_GPIODATADIR1 0x3
251#define REG_GPIODATADIR2 0x4
252#define REG_GPIODATADIR3 0x5
253#define REG_GPIODATAOUT1 0x6
254#define REG_GPIODATAOUT2 0x7
255#define REG_GPIODATAOUT3 0x8
256#define REG_CLEARGPIODATAOUT1 0x9
257#define REG_CLEARGPIODATAOUT2 0xA
258#define REG_CLEARGPIODATAOUT3 0xB
259#define REG_SETGPIODATAOUT1 0xC
260#define REG_SETGPIODATAOUT2 0xD
261#define REG_SETGPIODATAOUT3 0xE
262#define REG_GPIO_DEBEN1 0xF
263#define REG_GPIO_DEBEN2 0x10
264#define REG_GPIO_DEBEN3 0x11
265#define REG_GPIO_CTRL 0x12
266#define REG_GPIOPUPDCTR1 0x13
267#define REG_GPIOPUPDCTR2 0x14
268#define REG_GPIOPUPDCTR3 0x15
269#define REG_GPIOPUPDCTR4 0x16
270#define REG_GPIOPUPDCTR5 0x17
271#define REG_GPIO_ISR1A 0x19
272#define REG_GPIO_ISR2A 0x1A
273#define REG_GPIO_ISR3A 0x1B
274#define REG_GPIO_IMR1A 0x1C
275#define REG_GPIO_IMR2A 0x1D
276#define REG_GPIO_IMR3A 0x1E
277#define REG_GPIO_ISR1B 0x1F
278#define REG_GPIO_ISR2B 0x20
279#define REG_GPIO_ISR3B 0x21
280#define REG_GPIO_IMR1B 0x22
281#define REG_GPIO_IMR2B 0x23
282#define REG_GPIO_IMR3B 0x24
283#define REG_GPIO_EDR1 0x28
284#define REG_GPIO_EDR2 0x29
285#define REG_GPIO_EDR3 0x2A
286#define REG_GPIO_EDR4 0x2B
287#define REG_GPIO_EDR5 0x2C
288#define REG_GPIO_SIH_CTRL 0x2D
289
290
291
292
293#define TWL4030_GPIO_MAX 18
294
295
296
297
298
299
300
301#define REG_IDCODE_7_0 0x00
302#define REG_IDCODE_15_8 0x01
303#define REG_IDCODE_16_23 0x02
304#define REG_IDCODE_31_24 0x03
305#define REG_GPPUPDCTR1 0x0F
306#define REG_UNLOCK_TEST_REG 0x12
307
308
309
310#define I2C_SCL_CTRL_PU BIT(0)
311#define I2C_SDA_CTRL_PU BIT(2)
312#define SR_I2C_SCL_CTRL_PU BIT(4)
313#define SR_I2C_SDA_CTRL_PU BIT(6)
314
315#define TWL_EEPROM_R_UNLOCK 0x49
316
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323
324#define TWL4030_KEYPAD_KEYP_ISR1 0x11
325#define TWL4030_KEYPAD_KEYP_IMR1 0x12
326#define TWL4030_KEYPAD_KEYP_ISR2 0x13
327#define TWL4030_KEYPAD_KEYP_IMR2 0x14
328#define TWL4030_KEYPAD_KEYP_SIR 0x15
329#define TWL4030_KEYPAD_KEYP_EDR 0x16
330#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
331
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338
339#define TWL4030_MADC_ISR1 0x61
340#define TWL4030_MADC_IMR1 0x62
341#define TWL4030_MADC_ISR2 0x63
342#define TWL4030_MADC_IMR2 0x64
343#define TWL4030_MADC_SIR 0x65
344#define TWL4030_MADC_EDR 0x66
345#define TWL4030_MADC_SIH_CTRL 0x67
346
347
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349
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351
352
353#define TWL4030_INTERRUPTS_BCIISR1A 0x0
354#define TWL4030_INTERRUPTS_BCIISR2A 0x1
355#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
356#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
357#define TWL4030_INTERRUPTS_BCIISR1B 0x4
358#define TWL4030_INTERRUPTS_BCIISR2B 0x5
359#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
360#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
361#define TWL4030_INTERRUPTS_BCISIR1 0x8
362#define TWL4030_INTERRUPTS_BCISIR2 0x9
363#define TWL4030_INTERRUPTS_BCIEDR1 0xa
364#define TWL4030_INTERRUPTS_BCIEDR2 0xb
365#define TWL4030_INTERRUPTS_BCIEDR3 0xc
366#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
367
368
369
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371
372
373
374#define TWL4030_INT_PWR_ISR1 0x0
375#define TWL4030_INT_PWR_IMR1 0x1
376#define TWL4030_INT_PWR_ISR2 0x2
377#define TWL4030_INT_PWR_IMR2 0x3
378#define TWL4030_INT_PWR_SIR 0x4
379#define TWL4030_INT_PWR_EDR1 0x5
380#define TWL4030_INT_PWR_EDR2 0x6
381#define TWL4030_INT_PWR_SIH_CTRL 0x7
382
383
384
385
386
387
388#define TWL5031_ACIIMR_LSB 0x05
389#define TWL5031_ACIIMR_MSB 0x06
390#define TWL5031_ACIIDR_LSB 0x07
391#define TWL5031_ACIIDR_MSB 0x08
392#define TWL5031_ACCISR1 0x0F
393#define TWL5031_ACCIMR1 0x10
394#define TWL5031_ACCISR2 0x11
395#define TWL5031_ACCIMR2 0x12
396#define TWL5031_ACCSIR 0x13
397#define TWL5031_ACCEDR1 0x14
398#define TWL5031_ACCSIHCTRL 0x15
399
400
401
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405
406#define TWL5031_INTERRUPTS_BCIISR1 0x0
407#define TWL5031_INTERRUPTS_BCIIMR1 0x1
408#define TWL5031_INTERRUPTS_BCIISR2 0x2
409#define TWL5031_INTERRUPTS_BCIIMR2 0x3
410#define TWL5031_INTERRUPTS_BCISIR 0x4
411#define TWL5031_INTERRUPTS_BCIEDR1 0x5
412#define TWL5031_INTERRUPTS_BCIEDR2 0x6
413#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
414
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419
420
421#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
422#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
423#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
424#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
425#define TWL4030_PM_MASTER_STS_BOOT 0x04
426#define TWL4030_PM_MASTER_CFG_BOOT 0x05
427#define TWL4030_PM_MASTER_SHUNDAN 0x06
428#define TWL4030_PM_MASTER_BOOT_BCI 0x07
429#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
430#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
431#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
432#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
433#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
434#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
435#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
436#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
437#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
438#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
439#define TWL4030_PM_MASTER_STS_P123_STATE 0x13
440#define TWL4030_PM_MASTER_PB_CFG 0x14
441#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
442#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
443#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
444#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
445#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
446#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
447#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
448#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
449#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
450#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
451#define TWL4030_PM_MASTER_MEMORY_DATA 0x24
452
453#define TWL4030_PM_MASTER_KEY_CFG1 0xc0
454#define TWL4030_PM_MASTER_KEY_CFG2 0x0c
455
456#define TWL4030_PM_MASTER_KEY_TST1 0xe0
457#define TWL4030_PM_MASTER_KEY_TST2 0x0e
458
459#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
460
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471
472
473#define DEV_GRP_NULL 0x0
474#define DEV_GRP_P1 0x1
475#define DEV_GRP_P2 0x2
476#define DEV_GRP_P3 0x4
477
478
479#define RES_GRP_RES 0x0
480#define RES_GRP_PP 0x1
481#define RES_GRP_RC 0x2
482#define RES_GRP_PP_RC 0x3
483#define RES_GRP_PR 0x4
484#define RES_GRP_PP_PR 0x5
485#define RES_GRP_RC_PR 0x6
486#define RES_GRP_ALL 0x7
487
488#define RES_TYPE2_R0 0x0
489
490#define RES_TYPE_ALL 0x7
491
492
493#define RES_STATE_WRST 0xF
494#define RES_STATE_ACTIVE 0xE
495#define RES_STATE_SLEEP 0x8
496#define RES_STATE_OFF 0x0
497
498
499
500
501#define RES_VAUX1 1
502#define RES_VAUX2 2
503#define RES_VAUX3 3
504#define RES_VAUX4 4
505#define RES_VMMC1 5
506#define RES_VMMC2 6
507#define RES_VPLL1 7
508#define RES_VPLL2 8
509#define RES_VSIM 9
510#define RES_VDAC 10
511#define RES_VINTANA1 11
512#define RES_VINTANA2 12
513#define RES_VINTDIG 13
514#define RES_VIO 14
515#define RES_VDD1 15
516#define RES_VDD2 16
517#define RES_VUSB_1V5 17
518#define RES_VUSB_1V8 18
519#define RES_VUSB_3V1 19
520#define RES_VUSBCP 20
521#define RES_REGEN 21
522
523#define RES_NRES_PWRON 22
524#define RES_CLKEN 23
525#define RES_SYSEN 24
526#define RES_HFCLKOUT 25
527#define RES_32KCLKOUT 26
528#define RES_RESET 27
529
530#define RES_MAIN_REF 28
531
532#define TOTAL_RESOURCES 28
533
534
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544
545
546#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
547 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
548 | (type) << 4 | (state))
549
550#define MSG_SINGULAR(devgrp, id, state) \
551 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
552
553#define MSG_BROADCAST_ALL(devgrp, state) \
554 ((devgrp) << 5 | (state))
555
556#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
557#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
558#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
559
560
561struct twl4030_clock_init_data {
562 bool ck32k_lowpwr_enable;
563};
564
565struct twl4030_bci_platform_data {
566 int *battery_tmp_tbl;
567 unsigned int tblsize;
568 int bb_uvolt;
569 int bb_uamp;
570};
571
572
573struct twl4030_gpio_platform_data {
574
575 bool use_leds;
576
577
578 u8 mmc_cd;
579
580
581 u32 debounce;
582
583
584
585
586
587
588 u32 pullups;
589 u32 pulldowns;
590
591 int (*setup)(struct device *dev,
592 unsigned gpio, unsigned ngpio);
593 int (*teardown)(struct device *dev,
594 unsigned gpio, unsigned ngpio);
595};
596
597struct twl4030_madc_platform_data {
598 int irq_line;
599};
600
601
602
603
604
605#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
606
607struct twl4030_keypad_data {
608 const struct matrix_keymap_data *keymap_data;
609 unsigned rows;
610 unsigned cols;
611 bool rep;
612};
613
614enum twl4030_usb_mode {
615 T2_USB_MODE_ULPI = 1,
616 T2_USB_MODE_CEA2011_3PIN = 2,
617};
618
619struct twl4030_usb_data {
620 enum twl4030_usb_mode usb_mode;
621 unsigned long features;
622 struct phy_init_data *init_data;
623
624 int (*phy_init)(struct device *dev);
625 int (*phy_exit)(struct device *dev);
626
627 int (*phy_power)(struct device *dev, int iD, int on);
628
629 int (*phy_set_clock)(struct device *dev, int on);
630
631 int (*phy_suspend)(struct device *dev, int suspend);
632};
633
634struct twl4030_ins {
635 u16 pmb_message;
636 u8 delay;
637};
638
639struct twl4030_script {
640 struct twl4030_ins *script;
641 unsigned size;
642 u8 flags;
643#define TWL4030_WRST_SCRIPT (1<<0)
644#define TWL4030_WAKEUP12_SCRIPT (1<<1)
645#define TWL4030_WAKEUP3_SCRIPT (1<<2)
646#define TWL4030_SLEEP_SCRIPT (1<<3)
647};
648
649struct twl4030_resconfig {
650 u8 resource;
651 u8 devgroup;
652 u8 type;
653 u8 type2;
654 u8 remap_off;
655 u8 remap_sleep;
656};
657
658struct twl4030_power_data {
659 struct twl4030_script **scripts;
660 unsigned num;
661 struct twl4030_resconfig *resource_config;
662#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
663 bool use_poweroff;
664};
665
666extern int twl4030_remove_script(u8 flags);
667extern void twl4030_power_off(void);
668
669struct twl4030_codec_data {
670 unsigned int digimic_delay;
671 unsigned int ramp_delay_value;
672 unsigned int offset_cncl_path;
673 unsigned int hs_extmute:1;
674 int hs_extmute_gpio;
675};
676
677struct twl4030_vibra_data {
678 unsigned int coexist;
679};
680
681struct twl4030_audio_data {
682 unsigned int audio_mclk;
683 struct twl4030_codec_data *codec;
684 struct twl4030_vibra_data *vibra;
685
686
687 int audpwron_gpio;
688 int naudint_irq;
689 unsigned int irq_base;
690};
691
692struct twl4030_platform_data {
693 struct twl4030_clock_init_data *clock;
694 struct twl4030_bci_platform_data *bci;
695 struct twl4030_gpio_platform_data *gpio;
696 struct twl4030_madc_platform_data *madc;
697 struct twl4030_keypad_data *keypad;
698 struct twl4030_usb_data *usb;
699 struct twl4030_power_data *power;
700 struct twl4030_audio_data *audio;
701
702
703 struct regulator_init_data *vdac;
704 struct regulator_init_data *vaux1;
705 struct regulator_init_data *vaux2;
706 struct regulator_init_data *vaux3;
707 struct regulator_init_data *vdd1;
708 struct regulator_init_data *vdd2;
709 struct regulator_init_data *vdd3;
710
711 struct regulator_init_data *vpll1;
712 struct regulator_init_data *vpll2;
713 struct regulator_init_data *vmmc1;
714 struct regulator_init_data *vmmc2;
715 struct regulator_init_data *vsim;
716 struct regulator_init_data *vaux4;
717 struct regulator_init_data *vio;
718 struct regulator_init_data *vintana1;
719 struct regulator_init_data *vintana2;
720 struct regulator_init_data *vintdig;
721
722 struct regulator_init_data *vmmc;
723 struct regulator_init_data *vpp;
724 struct regulator_init_data *vusim;
725 struct regulator_init_data *vana;
726 struct regulator_init_data *vcxio;
727 struct regulator_init_data *vusb;
728 struct regulator_init_data *clk32kg;
729 struct regulator_init_data *v1v8;
730 struct regulator_init_data *v2v1;
731
732 struct regulator_init_data *ldo1;
733 struct regulator_init_data *ldo2;
734 struct regulator_init_data *ldo3;
735 struct regulator_init_data *ldo4;
736 struct regulator_init_data *ldo5;
737 struct regulator_init_data *ldo6;
738 struct regulator_init_data *ldo7;
739 struct regulator_init_data *ldoln;
740 struct regulator_init_data *ldousb;
741
742 struct regulator_init_data *smps3;
743 struct regulator_init_data *smps4;
744 struct regulator_init_data *vio6025;
745};
746
747struct twl_regulator_driver_data {
748 int (*set_voltage)(void *data, int target_uV);
749 int (*get_voltage)(void *data);
750 void *data;
751 unsigned long features;
752};
753
754#define TWL4030_VAUX2 BIT(0)
755#define TPS_SUBSET BIT(1)
756#define TWL5031 BIT(2)
757#define TWL6030_CLASS BIT(3)
758#define TWL6032_SUBCLASS BIT(4)
759#define TWL4030_ALLOW_UNSUPPORTED BIT(5)
760
761
762
763
764
765
766
767int twl4030_sih_setup(struct device *dev, int module, int irq_base);
768
769
770#define TWL4030_VDAC_DEV_GRP 0x3B
771#define TWL4030_VDAC_DEDICATED 0x3E
772#define TWL4030_VAUX1_DEV_GRP 0x17
773#define TWL4030_VAUX1_DEDICATED 0x1A
774#define TWL4030_VAUX2_DEV_GRP 0x1B
775#define TWL4030_VAUX2_DEDICATED 0x1E
776#define TWL4030_VAUX3_DEV_GRP 0x1F
777#define TWL4030_VAUX3_DEDICATED 0x22
778
779static inline int twl4030charger_usb_en(int enable) { return 0; }
780
781
782
783
784
785
786
787
788
789
790
791#define TWL4030_REG_VDD1 0
792#define TWL4030_REG_VDD2 1
793#define TWL4030_REG_VIO 2
794
795
796#define TWL4030_REG_VDAC 3
797#define TWL4030_REG_VPLL1 4
798#define TWL4030_REG_VPLL2 5
799#define TWL4030_REG_VMMC1 6
800#define TWL4030_REG_VMMC2 7
801#define TWL4030_REG_VSIM 8
802#define TWL4030_REG_VAUX1 9
803#define TWL4030_REG_VAUX2_4030 10
804#define TWL4030_REG_VAUX2 11
805#define TWL4030_REG_VAUX3 12
806#define TWL4030_REG_VAUX4 13
807
808
809#define TWL4030_REG_VINTANA1 14
810#define TWL4030_REG_VINTANA2 15
811#define TWL4030_REG_VINTDIG 16
812#define TWL4030_REG_VUSB1V5 17
813#define TWL4030_REG_VUSB1V8 18
814#define TWL4030_REG_VUSB3V1 19
815
816
817
818#define TWL6030_REG_VDD1 30
819#define TWL6030_REG_VDD2 31
820#define TWL6030_REG_VDD3 32
821
822
823#define TWL6030_REG_VMEM 33
824#define TWL6030_REG_V2V1 34
825#define TWL6030_REG_V1V29 35
826#define TWL6030_REG_V1V8 36
827
828
829#define TWL6030_REG_VAUX1_6030 37
830#define TWL6030_REG_VAUX2_6030 38
831#define TWL6030_REG_VAUX3_6030 39
832#define TWL6030_REG_VMMC 40
833#define TWL6030_REG_VPP 41
834#define TWL6030_REG_VUSIM 42
835#define TWL6030_REG_VANA 43
836#define TWL6030_REG_VCXIO 44
837#define TWL6030_REG_VDAC 45
838#define TWL6030_REG_VUSB 46
839
840
841#define TWL6030_REG_VRTC 47
842#define TWL6030_REG_CLK32KG 48
843
844
845#define TWL6032_REG_LDO2 49
846#define TWL6032_REG_LDO4 50
847#define TWL6032_REG_LDO3 51
848#define TWL6032_REG_LDO5 52
849#define TWL6032_REG_LDO1 53
850#define TWL6032_REG_LDO7 54
851#define TWL6032_REG_LDO6 55
852#define TWL6032_REG_LDOLN 56
853#define TWL6032_REG_LDOUSB 57
854
855
856#define TWL6032_REG_SMPS3 58
857#define TWL6032_REG_SMPS4 59
858#define TWL6032_REG_VIO 60
859
860
861#endif
862