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8#ifndef __MACH_PRCMU_H
9#define __MACH_PRCMU_H
10
11#include <linux/interrupt.h>
12#include <linux/notifier.h>
13#include <linux/err.h>
14
15#include <dt-bindings/mfd/dbx500-prcmu.h>
16
17
18#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
19#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
20
21
22enum prcmu_wakeup_index {
23 PRCMU_WAKEUP_INDEX_RTC,
24 PRCMU_WAKEUP_INDEX_RTT0,
25 PRCMU_WAKEUP_INDEX_RTT1,
26 PRCMU_WAKEUP_INDEX_HSI0,
27 PRCMU_WAKEUP_INDEX_HSI1,
28 PRCMU_WAKEUP_INDEX_USB,
29 PRCMU_WAKEUP_INDEX_ABB,
30 PRCMU_WAKEUP_INDEX_ABB_FIFO,
31 PRCMU_WAKEUP_INDEX_ARM,
32 PRCMU_WAKEUP_INDEX_CD_IRQ,
33 NUM_PRCMU_WAKEUP_INDICES
34};
35#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
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52
53#define EPOD_ID_SVAMMDSP 0
54#define EPOD_ID_SVAPIPE 1
55#define EPOD_ID_SIAMMDSP 2
56#define EPOD_ID_SIAPIPE 3
57#define EPOD_ID_SGA 4
58#define EPOD_ID_B2R2_MCDE 5
59#define EPOD_ID_ESRAM12 6
60#define EPOD_ID_ESRAM34 7
61#define NUM_EPOD_ID 8
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70
71
72#define EPOD_STATE_NO_CHANGE 0x00
73#define EPOD_STATE_OFF 0x01
74#define EPOD_STATE_RAMRET 0x02
75#define EPOD_STATE_ON_CLK_OFF 0x03
76#define EPOD_STATE_ON 0x04
77
78
79
80
81#define PRCMU_CLKSRC_CLK38M 0x00
82#define PRCMU_CLKSRC_ACLK 0x01
83#define PRCMU_CLKSRC_SYSCLK 0x02
84#define PRCMU_CLKSRC_LCDCLK 0x03
85#define PRCMU_CLKSRC_SDMMCCLK 0x04
86#define PRCMU_CLKSRC_TVCLK 0x05
87#define PRCMU_CLKSRC_TIMCLK 0x06
88#define PRCMU_CLKSRC_CLK009 0x07
89
90#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
91#define PRCMU_CLKSRC_I2CCLK 0x41
92#define PRCMU_CLKSRC_MSP02CLK 0x42
93#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
94#define PRCMU_CLKSRC_HSIRXCLK 0x44
95#define PRCMU_CLKSRC_HSITXCLK 0x45
96#define PRCMU_CLKSRC_ARMCLKFIX 0x46
97#define PRCMU_CLKSRC_HDMICLK 0x47
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104
105enum prcmu_wdog_id {
106 PRCMU_WDOG_ALL = 0x00,
107 PRCMU_WDOG_CPU1 = 0x01,
108 PRCMU_WDOG_CPU2 = 0x02,
109};
110
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118
119enum ape_opp {
120 APE_OPP_INIT = 0x00,
121 APE_NO_CHANGE = 0x01,
122 APE_100_OPP = 0x02,
123 APE_50_OPP = 0x03,
124 APE_50_PARTLY_25_OPP = 0xFF,
125};
126
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136
137enum arm_opp {
138 ARM_OPP_INIT = 0x00,
139 ARM_NO_CHANGE = 0x01,
140 ARM_100_OPP = 0x02,
141 ARM_50_OPP = 0x03,
142 ARM_MAX_OPP = 0x04,
143 ARM_MAX_FREQ100OPP = 0x05,
144 ARM_EXTCLK = 0x07
145};
146
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152
153enum ddr_opp {
154 DDR_100_OPP = 0x00,
155 DDR_50_OPP = 0x01,
156 DDR_25_OPP = 0x02,
157};
158
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160
161
162#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
163#define ESRAM0_DEEP_SLEEP_STATE_RET 2
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170
171
172enum ddr_pwrst {
173 DDR_PWR_STATE_UNCHANGED = 0x00,
174 DDR_PWR_STATE_ON = 0x01,
175 DDR_PWR_STATE_OFFLOWLAT = 0x02,
176 DDR_PWR_STATE_OFFHIGHLAT = 0x03
177};
178
179#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
180
181struct prcmu_pdata
182{
183 bool enable_set_ddr_opp;
184 bool enable_ape_opp_100_voltage;
185 struct ab8500_platform_data *ab_platdata;
186 int ab_irq;
187 int irq_base;
188 u32 version_offset;
189 u32 legacy_offset;
190 u32 adt_offset;
191};
192
193#define PRCMU_FW_PROJECT_U8500 2
194#define PRCMU_FW_PROJECT_U8400 3
195#define PRCMU_FW_PROJECT_U9500 4
196#define PRCMU_FW_PROJECT_U8500_MBB 5
197#define PRCMU_FW_PROJECT_U8500_C1 6
198#define PRCMU_FW_PROJECT_U8500_C2 7
199#define PRCMU_FW_PROJECT_U8500_C3 8
200#define PRCMU_FW_PROJECT_U8500_C4 9
201#define PRCMU_FW_PROJECT_U9500_MBL 10
202#define PRCMU_FW_PROJECT_U8500_MBL 11
203#define PRCMU_FW_PROJECT_U8500_MBL2 12
204#define PRCMU_FW_PROJECT_U8520 13
205#define PRCMU_FW_PROJECT_U8420 14
206#define PRCMU_FW_PROJECT_A9420 20
207
208#define PRCMU_FW_PROJECT_U9540 32
209
210#define PRCMU_FW_PROJECT_L8540 64
211
212#define PRCMU_FW_PROJECT_L8580 96
213
214#define PRCMU_FW_PROJECT_NAME_LEN 20
215struct prcmu_fw_version {
216 u32 project;
217 u8 api_version;
218 u8 func_version;
219 u8 errata;
220 char project_name[PRCMU_FW_PROJECT_NAME_LEN];
221};
222
223#include <linux/mfd/db8500-prcmu.h>
224
225#if defined(CONFIG_UX500_SOC_DB8500)
226
227static inline void prcmu_early_init(u32 phy_base, u32 size)
228{
229 return db8500_prcmu_early_init(phy_base, size);
230}
231
232static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
233 bool keep_ap_pll)
234{
235 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
236 keep_ap_pll);
237}
238
239static inline u8 prcmu_get_power_state_result(void)
240{
241 return db8500_prcmu_get_power_state_result();
242}
243
244static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
245{
246 return db8500_prcmu_set_epod(epod_id, epod_state);
247}
248
249static inline void prcmu_enable_wakeups(u32 wakeups)
250{
251 db8500_prcmu_enable_wakeups(wakeups);
252}
253
254static inline void prcmu_disable_wakeups(void)
255{
256 prcmu_enable_wakeups(0);
257}
258
259static inline void prcmu_config_abb_event_readout(u32 abb_events)
260{
261 db8500_prcmu_config_abb_event_readout(abb_events);
262}
263
264static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
265{
266 db8500_prcmu_get_abb_event_buffer(buf);
267}
268
269int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
270int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
271int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
272
273int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
274
275static inline int prcmu_request_clock(u8 clock, bool enable)
276{
277 return db8500_prcmu_request_clock(clock, enable);
278}
279
280unsigned long prcmu_clock_rate(u8 clock);
281long prcmu_round_clock_rate(u8 clock, unsigned long rate);
282int prcmu_set_clock_rate(u8 clock, unsigned long rate);
283
284static inline int prcmu_set_ddr_opp(u8 opp)
285{
286 return db8500_prcmu_set_ddr_opp(opp);
287}
288static inline int prcmu_get_ddr_opp(void)
289{
290 return db8500_prcmu_get_ddr_opp();
291}
292
293static inline int prcmu_set_arm_opp(u8 opp)
294{
295 return db8500_prcmu_set_arm_opp(opp);
296}
297
298static inline int prcmu_get_arm_opp(void)
299{
300 return db8500_prcmu_get_arm_opp();
301}
302
303static inline int prcmu_set_ape_opp(u8 opp)
304{
305 return db8500_prcmu_set_ape_opp(opp);
306}
307
308static inline int prcmu_get_ape_opp(void)
309{
310 return db8500_prcmu_get_ape_opp();
311}
312
313static inline int prcmu_request_ape_opp_100_voltage(bool enable)
314{
315 return db8500_prcmu_request_ape_opp_100_voltage(enable);
316}
317
318static inline void prcmu_system_reset(u16 reset_code)
319{
320 return db8500_prcmu_system_reset(reset_code);
321}
322
323static inline u16 prcmu_get_reset_code(void)
324{
325 return db8500_prcmu_get_reset_code();
326}
327
328int prcmu_ac_wake_req(void);
329void prcmu_ac_sleep_req(void);
330static inline void prcmu_modem_reset(void)
331{
332 return db8500_prcmu_modem_reset();
333}
334
335static inline bool prcmu_is_ac_wake_requested(void)
336{
337 return db8500_prcmu_is_ac_wake_requested();
338}
339
340static inline int prcmu_set_display_clocks(void)
341{
342 return db8500_prcmu_set_display_clocks();
343}
344
345static inline int prcmu_disable_dsipll(void)
346{
347 return db8500_prcmu_disable_dsipll();
348}
349
350static inline int prcmu_enable_dsipll(void)
351{
352 return db8500_prcmu_enable_dsipll();
353}
354
355static inline int prcmu_config_esram0_deep_sleep(u8 state)
356{
357 return db8500_prcmu_config_esram0_deep_sleep(state);
358}
359
360static inline int prcmu_config_hotdog(u8 threshold)
361{
362 return db8500_prcmu_config_hotdog(threshold);
363}
364
365static inline int prcmu_config_hotmon(u8 low, u8 high)
366{
367 return db8500_prcmu_config_hotmon(low, high);
368}
369
370static inline int prcmu_start_temp_sense(u16 cycles32k)
371{
372 return db8500_prcmu_start_temp_sense(cycles32k);
373}
374
375static inline int prcmu_stop_temp_sense(void)
376{
377 return db8500_prcmu_stop_temp_sense();
378}
379
380static inline u32 prcmu_read(unsigned int reg)
381{
382 return db8500_prcmu_read(reg);
383}
384
385static inline void prcmu_write(unsigned int reg, u32 value)
386{
387 db8500_prcmu_write(reg, value);
388}
389
390static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
391{
392 db8500_prcmu_write_masked(reg, mask, value);
393}
394
395static inline int prcmu_enable_a9wdog(u8 id)
396{
397 return db8500_prcmu_enable_a9wdog(id);
398}
399
400static inline int prcmu_disable_a9wdog(u8 id)
401{
402 return db8500_prcmu_disable_a9wdog(id);
403}
404
405static inline int prcmu_kick_a9wdog(u8 id)
406{
407 return db8500_prcmu_kick_a9wdog(id);
408}
409
410static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
411{
412 return db8500_prcmu_load_a9wdog(id, timeout);
413}
414
415static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
416{
417 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
418}
419#else
420
421static inline void prcmu_early_init(u32 phy_base, u32 size) {}
422
423static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
424 bool keep_ap_pll)
425{
426 return 0;
427}
428
429static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
430{
431 return 0;
432}
433
434static inline void prcmu_enable_wakeups(u32 wakeups) {}
435
436static inline void prcmu_disable_wakeups(void) {}
437
438static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
439{
440 return -ENOSYS;
441}
442
443static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
444{
445 return -ENOSYS;
446}
447
448static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
449 u8 size)
450{
451 return -ENOSYS;
452}
453
454static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
455{
456 return 0;
457}
458
459static inline int prcmu_request_clock(u8 clock, bool enable)
460{
461 return 0;
462}
463
464static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
465{
466 return 0;
467}
468
469static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
470{
471 return 0;
472}
473
474static inline unsigned long prcmu_clock_rate(u8 clock)
475{
476 return 0;
477}
478
479static inline int prcmu_set_ape_opp(u8 opp)
480{
481 return 0;
482}
483
484static inline int prcmu_get_ape_opp(void)
485{
486 return APE_100_OPP;
487}
488
489static inline int prcmu_request_ape_opp_100_voltage(bool enable)
490{
491 return 0;
492}
493
494static inline int prcmu_set_arm_opp(u8 opp)
495{
496 return 0;
497}
498
499static inline int prcmu_get_arm_opp(void)
500{
501 return ARM_100_OPP;
502}
503
504static inline int prcmu_set_ddr_opp(u8 opp)
505{
506 return 0;
507}
508
509static inline int prcmu_get_ddr_opp(void)
510{
511 return DDR_100_OPP;
512}
513
514static inline void prcmu_system_reset(u16 reset_code) {}
515
516static inline u16 prcmu_get_reset_code(void)
517{
518 return 0;
519}
520
521static inline int prcmu_ac_wake_req(void)
522{
523 return 0;
524}
525
526static inline void prcmu_ac_sleep_req(void) {}
527
528static inline void prcmu_modem_reset(void) {}
529
530static inline bool prcmu_is_ac_wake_requested(void)
531{
532 return false;
533}
534
535static inline int prcmu_set_display_clocks(void)
536{
537 return 0;
538}
539
540static inline int prcmu_disable_dsipll(void)
541{
542 return 0;
543}
544
545static inline int prcmu_enable_dsipll(void)
546{
547 return 0;
548}
549
550static inline int prcmu_config_esram0_deep_sleep(u8 state)
551{
552 return 0;
553}
554
555static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
556
557static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
558{
559 *buf = NULL;
560}
561
562static inline int prcmu_config_hotdog(u8 threshold)
563{
564 return 0;
565}
566
567static inline int prcmu_config_hotmon(u8 low, u8 high)
568{
569 return 0;
570}
571
572static inline int prcmu_start_temp_sense(u16 cycles32k)
573{
574 return 0;
575}
576
577static inline int prcmu_stop_temp_sense(void)
578{
579 return 0;
580}
581
582static inline u32 prcmu_read(unsigned int reg)
583{
584 return 0;
585}
586
587static inline void prcmu_write(unsigned int reg, u32 value) {}
588
589static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
590
591#endif
592
593static inline void prcmu_set(unsigned int reg, u32 bits)
594{
595 prcmu_write_masked(reg, bits, bits);
596}
597
598static inline void prcmu_clear(unsigned int reg, u32 bits)
599{
600 prcmu_write_masked(reg, bits, 0);
601}
602
603
604#define PRCMU_QOS_APE_OPP 1
605#define PRCMU_QOS_DDR_OPP 2
606#define PRCMU_QOS_ARM_OPP 3
607#define PRCMU_QOS_DEFAULT_VALUE -1
608
609#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
610
611unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
612void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
613void prcmu_qos_force_opp(int, s32);
614int prcmu_qos_requirement(int pm_qos_class);
615int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
616int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
617void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
618int prcmu_qos_add_notifier(int prcmu_qos_class,
619 struct notifier_block *notifier);
620int prcmu_qos_remove_notifier(int prcmu_qos_class,
621 struct notifier_block *notifier);
622
623#else
624
625static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
626{
627 return 0;
628}
629
630static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
631
632static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
633
634static inline int prcmu_qos_requirement(int prcmu_qos_class)
635{
636 return 0;
637}
638
639static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
640 char *name, s32 value)
641{
642 return 0;
643}
644
645static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
646 char *name, s32 new_value)
647{
648 return 0;
649}
650
651static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
652{
653}
654
655static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
656 struct notifier_block *notifier)
657{
658 return 0;
659}
660static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
661 struct notifier_block *notifier)
662{
663 return 0;
664}
665
666#endif
667
668#endif
669