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33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/if_ether.h>
37#include <linux/pci.h>
38#include <linux/completion.h>
39#include <linux/radix-tree.h>
40#include <linux/cpu_rmap.h>
41
42#include <linux/atomic.h>
43
44#include <linux/clocksource.h>
45
46#define MAX_MSIX_P_PORT 17
47#define MAX_MSIX 64
48#define MSIX_LEGACY_SZ 4
49#define MIN_MSIX_P_PORT 5
50
51enum {
52 MLX4_FLAG_MSI_X = 1 << 0,
53 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
54 MLX4_FLAG_MASTER = 1 << 2,
55 MLX4_FLAG_SLAVE = 1 << 3,
56 MLX4_FLAG_SRIOV = 1 << 4,
57 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
58};
59
60enum {
61 MLX4_PORT_CAP_IS_SM = 1 << 1,
62 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
63};
64
65enum {
66 MLX4_MAX_PORTS = 2,
67 MLX4_MAX_PORT_PKEYS = 128
68};
69
70
71
72
73
74#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
75#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
76
77enum {
78 MLX4_BOARD_ID_LEN = 64
79};
80
81enum {
82 MLX4_MAX_NUM_PF = 16,
83 MLX4_MAX_NUM_VF = 64,
84 MLX4_MFUNC_MAX = 80,
85 MLX4_MAX_EQ_NUM = 1024,
86 MLX4_MFUNC_EQ_NUM = 4,
87 MLX4_MFUNC_MAX_EQES = 8,
88 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
89};
90
91
92
93
94
95
96
97
98enum {
99 MLX4_STEERING_MODE_A0,
100 MLX4_STEERING_MODE_B0,
101 MLX4_STEERING_MODE_DEVICE_MANAGED
102};
103
104static inline const char *mlx4_steering_mode_str(int steering_mode)
105{
106 switch (steering_mode) {
107 case MLX4_STEERING_MODE_A0:
108 return "A0 steering";
109
110 case MLX4_STEERING_MODE_B0:
111 return "B0 steering";
112
113 case MLX4_STEERING_MODE_DEVICE_MANAGED:
114 return "Device managed flow steering";
115
116 default:
117 return "Unrecognize steering mode";
118 }
119}
120
121enum {
122 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
123 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
124};
125
126enum {
127 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
128 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
129 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
130 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
131 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
132 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
133 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
134 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
135 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
136 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
137 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
138 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
139 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
140 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
141 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
142 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
143 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
144 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
145 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
146 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
147 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
148 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
149 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
150 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
151 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
152 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
153 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
154 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
155 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
156 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
157};
158
159enum {
160 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
161 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
162 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
163 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
164 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
165 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
166 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
167 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
168 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
169 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
170 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
171};
172
173enum {
174 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
175 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
176};
177
178enum {
179 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
180};
181
182enum {
183 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
184};
185
186
187#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
188
189enum {
190 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
191 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
192 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
193 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
194 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
195 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
196};
197
198enum mlx4_event {
199 MLX4_EVENT_TYPE_COMP = 0x00,
200 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
201 MLX4_EVENT_TYPE_COMM_EST = 0x02,
202 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
203 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
204 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
205 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
206 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
207 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
208 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
209 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
210 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
211 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
212 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
213 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
214 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
215 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
216 MLX4_EVENT_TYPE_CMD = 0x0a,
217 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
218 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
219 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
220 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
221 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
222 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
223 MLX4_EVENT_TYPE_NONE = 0xff,
224};
225
226enum {
227 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
228 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
229};
230
231enum {
232 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
233};
234
235enum slave_port_state {
236 SLAVE_PORT_DOWN = 0,
237 SLAVE_PENDING_UP,
238 SLAVE_PORT_UP,
239};
240
241enum slave_port_gen_event {
242 SLAVE_PORT_GEN_EVENT_DOWN = 0,
243 SLAVE_PORT_GEN_EVENT_UP,
244 SLAVE_PORT_GEN_EVENT_NONE,
245};
246
247enum slave_port_state_event {
248 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
249 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
250 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
251 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
252};
253
254enum {
255 MLX4_PERM_LOCAL_READ = 1 << 10,
256 MLX4_PERM_LOCAL_WRITE = 1 << 11,
257 MLX4_PERM_REMOTE_READ = 1 << 12,
258 MLX4_PERM_REMOTE_WRITE = 1 << 13,
259 MLX4_PERM_ATOMIC = 1 << 14,
260 MLX4_PERM_BIND_MW = 1 << 15,
261};
262
263enum {
264 MLX4_OPCODE_NOP = 0x00,
265 MLX4_OPCODE_SEND_INVAL = 0x01,
266 MLX4_OPCODE_RDMA_WRITE = 0x08,
267 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
268 MLX4_OPCODE_SEND = 0x0a,
269 MLX4_OPCODE_SEND_IMM = 0x0b,
270 MLX4_OPCODE_LSO = 0x0e,
271 MLX4_OPCODE_RDMA_READ = 0x10,
272 MLX4_OPCODE_ATOMIC_CS = 0x11,
273 MLX4_OPCODE_ATOMIC_FA = 0x12,
274 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
275 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
276 MLX4_OPCODE_BIND_MW = 0x18,
277 MLX4_OPCODE_FMR = 0x19,
278 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
279 MLX4_OPCODE_CONFIG_CMD = 0x1f,
280
281 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
282 MLX4_RECV_OPCODE_SEND = 0x01,
283 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
284 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
285
286 MLX4_CQE_OPCODE_ERROR = 0x1e,
287 MLX4_CQE_OPCODE_RESIZE = 0x16,
288};
289
290enum {
291 MLX4_STAT_RATE_OFFSET = 5
292};
293
294enum mlx4_protocol {
295 MLX4_PROT_IB_IPV6 = 0,
296 MLX4_PROT_ETH,
297 MLX4_PROT_IB_IPV4,
298 MLX4_PROT_FCOE
299};
300
301enum {
302 MLX4_MTT_FLAG_PRESENT = 1
303};
304
305enum mlx4_qp_region {
306 MLX4_QP_REGION_FW = 0,
307 MLX4_QP_REGION_ETH_ADDR,
308 MLX4_QP_REGION_FC_ADDR,
309 MLX4_QP_REGION_FC_EXCH,
310 MLX4_NUM_QP_REGION
311};
312
313enum mlx4_port_type {
314 MLX4_PORT_TYPE_NONE = 0,
315 MLX4_PORT_TYPE_IB = 1,
316 MLX4_PORT_TYPE_ETH = 2,
317 MLX4_PORT_TYPE_AUTO = 3
318};
319
320enum mlx4_special_vlan_idx {
321 MLX4_NO_VLAN_IDX = 0,
322 MLX4_VLAN_MISS_IDX,
323 MLX4_VLAN_REGULAR
324};
325
326enum mlx4_steer_type {
327 MLX4_MC_STEER = 0,
328 MLX4_UC_STEER,
329 MLX4_NUM_STEERS
330};
331
332enum {
333 MLX4_NUM_FEXCH = 64 * 1024,
334};
335
336enum {
337 MLX4_MAX_FAST_REG_PAGES = 511,
338};
339
340enum {
341 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
342 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
343 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
344};
345
346
347enum {
348 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
349 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
350 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
351 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
352 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
353};
354
355#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
356 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
357
358static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
359{
360 return (major << 32) | (minor << 16) | subminor;
361}
362
363struct mlx4_phys_caps {
364 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
365 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
366 u32 num_phys_eqs;
367 u32 base_sqpn;
368 u32 base_proxy_sqpn;
369 u32 base_tunnel_sqpn;
370};
371
372struct mlx4_caps {
373 u64 fw_ver;
374 u32 function;
375 int num_ports;
376 int vl_cap[MLX4_MAX_PORTS + 1];
377 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
378 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
379 u64 def_mac[MLX4_MAX_PORTS + 1];
380 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
381 int gid_table_len[MLX4_MAX_PORTS + 1];
382 int pkey_table_len[MLX4_MAX_PORTS + 1];
383 int trans_type[MLX4_MAX_PORTS + 1];
384 int vendor_oui[MLX4_MAX_PORTS + 1];
385 int wavelength[MLX4_MAX_PORTS + 1];
386 u64 trans_code[MLX4_MAX_PORTS + 1];
387 int local_ca_ack_delay;
388 int num_uars;
389 u32 uar_page_size;
390 int bf_reg_size;
391 int bf_regs_per_page;
392 int max_sq_sg;
393 int max_rq_sg;
394 int num_qps;
395 int max_wqes;
396 int max_sq_desc_sz;
397 int max_rq_desc_sz;
398 int max_qp_init_rdma;
399 int max_qp_dest_rdma;
400 u32 *qp0_proxy;
401 u32 *qp1_proxy;
402 u32 *qp0_tunnel;
403 u32 *qp1_tunnel;
404 int num_srqs;
405 int max_srq_wqes;
406 int max_srq_sge;
407 int reserved_srqs;
408 int num_cqs;
409 int max_cqes;
410 int reserved_cqs;
411 int num_eqs;
412 int reserved_eqs;
413 int num_comp_vectors;
414 int comp_pool;
415 int num_mpts;
416 int max_fmr_maps;
417 int num_mtts;
418 int fmr_reserved_mtts;
419 int reserved_mtts;
420 int reserved_mrws;
421 int reserved_uars;
422 int num_mgms;
423 int num_amgms;
424 int reserved_mcgs;
425 int num_qp_per_mgm;
426 int steering_mode;
427 int fs_log_max_ucast_qp_range_size;
428 int num_pds;
429 int reserved_pds;
430 int max_xrcds;
431 int reserved_xrcds;
432 int mtt_entry_sz;
433 u32 max_msg_sz;
434 u32 page_size_cap;
435 u64 flags;
436 u64 flags2;
437 u32 bmme_flags;
438 u32 reserved_lkey;
439 u16 stat_rate_support;
440 u8 port_width_cap[MLX4_MAX_PORTS + 1];
441 int max_gso_sz;
442 int max_rss_tbl_sz;
443 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
444 int reserved_qps;
445 int reserved_qps_base[MLX4_NUM_QP_REGION];
446 int log_num_macs;
447 int log_num_vlans;
448 int log_num_prios;
449 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
450 u8 supported_type[MLX4_MAX_PORTS + 1];
451 u8 suggested_type[MLX4_MAX_PORTS + 1];
452 u8 default_sense[MLX4_MAX_PORTS + 1];
453 u32 port_mask[MLX4_MAX_PORTS + 1];
454 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
455 u32 max_counters;
456 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
457 u16 sqp_demux;
458 u32 eqe_size;
459 u32 cqe_size;
460 u8 eqe_factor;
461 u32 userspace_caps;
462 u32 function_caps;
463 u16 hca_core_clock;
464 u64 phys_port_id[MLX4_MAX_PORTS + 1];
465 int tunnel_offload_mode;
466};
467
468struct mlx4_buf_list {
469 void *buf;
470 dma_addr_t map;
471};
472
473struct mlx4_buf {
474 struct mlx4_buf_list direct;
475 struct mlx4_buf_list *page_list;
476 int nbufs;
477 int npages;
478 int page_shift;
479};
480
481struct mlx4_mtt {
482 u32 offset;
483 int order;
484 int page_shift;
485};
486
487enum {
488 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
489};
490
491struct mlx4_db_pgdir {
492 struct list_head list;
493 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
494 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
495 unsigned long *bits[2];
496 __be32 *db_page;
497 dma_addr_t db_dma;
498};
499
500struct mlx4_ib_user_db_page;
501
502struct mlx4_db {
503 __be32 *db;
504 union {
505 struct mlx4_db_pgdir *pgdir;
506 struct mlx4_ib_user_db_page *user_page;
507 } u;
508 dma_addr_t dma;
509 int index;
510 int order;
511};
512
513struct mlx4_hwq_resources {
514 struct mlx4_db db;
515 struct mlx4_mtt mtt;
516 struct mlx4_buf buf;
517};
518
519struct mlx4_mr {
520 struct mlx4_mtt mtt;
521 u64 iova;
522 u64 size;
523 u32 key;
524 u32 pd;
525 u32 access;
526 int enabled;
527};
528
529enum mlx4_mw_type {
530 MLX4_MW_TYPE_1 = 1,
531 MLX4_MW_TYPE_2 = 2,
532};
533
534struct mlx4_mw {
535 u32 key;
536 u32 pd;
537 enum mlx4_mw_type type;
538 int enabled;
539};
540
541struct mlx4_fmr {
542 struct mlx4_mr mr;
543 struct mlx4_mpt_entry *mpt;
544 __be64 *mtts;
545 dma_addr_t dma_handle;
546 int max_pages;
547 int max_maps;
548 int maps;
549 u8 page_shift;
550};
551
552struct mlx4_uar {
553 unsigned long pfn;
554 int index;
555 struct list_head bf_list;
556 unsigned free_bf_bmap;
557 void __iomem *map;
558 void __iomem *bf_map;
559};
560
561struct mlx4_bf {
562 unsigned long offset;
563 int buf_size;
564 struct mlx4_uar *uar;
565 void __iomem *reg;
566};
567
568struct mlx4_cq {
569 void (*comp) (struct mlx4_cq *);
570 void (*event) (struct mlx4_cq *, enum mlx4_event);
571
572 struct mlx4_uar *uar;
573
574 u32 cons_index;
575
576 __be32 *set_ci_db;
577 __be32 *arm_db;
578 int arm_sn;
579
580 int cqn;
581 unsigned vector;
582
583 atomic_t refcount;
584 struct completion free;
585};
586
587struct mlx4_qp {
588 void (*event) (struct mlx4_qp *, enum mlx4_event);
589
590 int qpn;
591
592 atomic_t refcount;
593 struct completion free;
594};
595
596struct mlx4_srq {
597 void (*event) (struct mlx4_srq *, enum mlx4_event);
598
599 int srqn;
600 int max;
601 int max_gs;
602 int wqe_shift;
603
604 atomic_t refcount;
605 struct completion free;
606};
607
608struct mlx4_av {
609 __be32 port_pd;
610 u8 reserved1;
611 u8 g_slid;
612 __be16 dlid;
613 u8 reserved2;
614 u8 gid_index;
615 u8 stat_rate;
616 u8 hop_limit;
617 __be32 sl_tclass_flowlabel;
618 u8 dgid[16];
619};
620
621struct mlx4_eth_av {
622 __be32 port_pd;
623 u8 reserved1;
624 u8 smac_idx;
625 u16 reserved2;
626 u8 reserved3;
627 u8 gid_index;
628 u8 stat_rate;
629 u8 hop_limit;
630 __be32 sl_tclass_flowlabel;
631 u8 dgid[16];
632 u32 reserved4[2];
633 __be16 vlan;
634 u8 mac[ETH_ALEN];
635};
636
637union mlx4_ext_av {
638 struct mlx4_av ib;
639 struct mlx4_eth_av eth;
640};
641
642struct mlx4_counter {
643 u8 reserved1[3];
644 u8 counter_mode;
645 __be32 num_ifc;
646 u32 reserved2[2];
647 __be64 rx_frames;
648 __be64 rx_bytes;
649 __be64 tx_frames;
650 __be64 tx_bytes;
651};
652
653struct mlx4_quotas {
654 int qp;
655 int cq;
656 int srq;
657 int mpt;
658 int mtt;
659 int counter;
660 int xrcd;
661};
662
663struct mlx4_dev {
664 struct pci_dev *pdev;
665 unsigned long flags;
666 unsigned long num_slaves;
667 struct mlx4_caps caps;
668 struct mlx4_phys_caps phys_caps;
669 struct mlx4_quotas quotas;
670 struct radix_tree_root qp_table_tree;
671 u8 rev_id;
672 char board_id[MLX4_BOARD_ID_LEN];
673 int num_vfs;
674 int numa_node;
675 int oper_log_mgm_entry_size;
676 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
677 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
678};
679
680struct mlx4_eqe {
681 u8 reserved1;
682 u8 type;
683 u8 reserved2;
684 u8 subtype;
685 union {
686 u32 raw[6];
687 struct {
688 __be32 cqn;
689 } __packed comp;
690 struct {
691 u16 reserved1;
692 __be16 token;
693 u32 reserved2;
694 u8 reserved3[3];
695 u8 status;
696 __be64 out_param;
697 } __packed cmd;
698 struct {
699 __be32 qpn;
700 } __packed qp;
701 struct {
702 __be32 srqn;
703 } __packed srq;
704 struct {
705 __be32 cqn;
706 u32 reserved1;
707 u8 reserved2[3];
708 u8 syndrome;
709 } __packed cq_err;
710 struct {
711 u32 reserved1[2];
712 __be32 port;
713 } __packed port_change;
714 struct {
715 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
716 u32 reserved;
717 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
718 } __packed comm_channel_arm;
719 struct {
720 u8 port;
721 u8 reserved[3];
722 __be64 mac;
723 } __packed mac_update;
724 struct {
725 __be32 slave_id;
726 } __packed flr_event;
727 struct {
728 __be16 current_temperature;
729 __be16 warning_threshold;
730 } __packed warming;
731 struct {
732 u8 reserved[3];
733 u8 port;
734 union {
735 struct {
736 __be16 mstr_sm_lid;
737 __be16 port_lid;
738 __be32 changed_attr;
739 u8 reserved[3];
740 u8 mstr_sm_sl;
741 __be64 gid_prefix;
742 } __packed port_info;
743 struct {
744 __be32 block_ptr;
745 __be32 tbl_entries_mask;
746 } __packed tbl_change_info;
747 } params;
748 } __packed port_mgmt_change;
749 } event;
750 u8 slave_id;
751 u8 reserved3[2];
752 u8 owner;
753} __packed;
754
755struct mlx4_init_port_param {
756 int set_guid0;
757 int set_node_guid;
758 int set_si_guid;
759 u16 mtu;
760 int port_width_cap;
761 u16 vl_cap;
762 u16 max_gid;
763 u16 max_pkey;
764 u64 guid0;
765 u64 node_guid;
766 u64 si_guid;
767};
768
769#define mlx4_foreach_port(port, dev, type) \
770 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
771 if ((type) == (dev)->caps.port_mask[(port)])
772
773#define mlx4_foreach_non_ib_transport_port(port, dev) \
774 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
775 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
776
777#define mlx4_foreach_ib_transport_port(port, dev) \
778 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
779 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
780 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
781
782#define MLX4_INVALID_SLAVE_ID 0xFF
783
784void handle_port_mgmt_change_event(struct work_struct *work);
785
786static inline int mlx4_master_func_num(struct mlx4_dev *dev)
787{
788 return dev->caps.function;
789}
790
791static inline int mlx4_is_master(struct mlx4_dev *dev)
792{
793 return dev->flags & MLX4_FLAG_MASTER;
794}
795
796static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
797{
798 return dev->phys_caps.base_sqpn + 8 +
799 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
800}
801
802static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
803{
804 return (qpn < dev->phys_caps.base_sqpn + 8 +
805 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
806}
807
808static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
809{
810 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
811
812 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
813 return 1;
814
815 return 0;
816}
817
818static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
819{
820 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
821}
822
823static inline int mlx4_is_slave(struct mlx4_dev *dev)
824{
825 return dev->flags & MLX4_FLAG_SLAVE;
826}
827
828int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
829 struct mlx4_buf *buf);
830void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
831static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
832{
833 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
834 return buf->direct.buf + offset;
835 else
836 return buf->page_list[offset >> PAGE_SHIFT].buf +
837 (offset & (PAGE_SIZE - 1));
838}
839
840int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
841void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
842int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
843void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
844
845int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
846void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
847int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
848void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
849
850int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
851 struct mlx4_mtt *mtt);
852void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
853u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
854
855int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
856 int npages, int page_shift, struct mlx4_mr *mr);
857int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
858int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
859int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
860 struct mlx4_mw *mw);
861void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
862int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
863int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
864 int start_index, int npages, u64 *page_list);
865int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
866 struct mlx4_buf *buf);
867
868int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
869void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
870
871int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
872 int size, int max_direct);
873void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
874 int size);
875
876int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
877 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
878 unsigned vector, int collapsed, int timestamp_en);
879void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
880
881int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
882void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
883
884int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
885void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
886
887int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
888 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
889void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
890int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
891int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
892
893int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
894int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
895
896int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
897 int block_mcast_loopback, enum mlx4_protocol prot);
898int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
899 enum mlx4_protocol prot);
900int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
901 u8 port, int block_mcast_loopback,
902 enum mlx4_protocol protocol, u64 *reg_id);
903int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
904 enum mlx4_protocol protocol, u64 reg_id);
905
906enum {
907 MLX4_DOMAIN_UVERBS = 0x1000,
908 MLX4_DOMAIN_ETHTOOL = 0x2000,
909 MLX4_DOMAIN_RFS = 0x3000,
910 MLX4_DOMAIN_NIC = 0x5000,
911};
912
913enum mlx4_net_trans_rule_id {
914 MLX4_NET_TRANS_RULE_ID_ETH = 0,
915 MLX4_NET_TRANS_RULE_ID_IB,
916 MLX4_NET_TRANS_RULE_ID_IPV6,
917 MLX4_NET_TRANS_RULE_ID_IPV4,
918 MLX4_NET_TRANS_RULE_ID_TCP,
919 MLX4_NET_TRANS_RULE_ID_UDP,
920 MLX4_NET_TRANS_RULE_ID_VXLAN,
921 MLX4_NET_TRANS_RULE_NUM,
922};
923
924extern const u16 __sw_id_hw[];
925
926static inline int map_hw_to_sw_id(u16 header_id)
927{
928
929 int i;
930 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
931 if (header_id == __sw_id_hw[i])
932 return i;
933 }
934 return -EINVAL;
935}
936
937enum mlx4_net_trans_promisc_mode {
938 MLX4_FS_REGULAR = 1,
939 MLX4_FS_ALL_DEFAULT,
940 MLX4_FS_MC_DEFAULT,
941 MLX4_FS_UC_SNIFFER,
942 MLX4_FS_MC_SNIFFER,
943 MLX4_FS_MODE_NUM,
944};
945
946struct mlx4_spec_eth {
947 u8 dst_mac[ETH_ALEN];
948 u8 dst_mac_msk[ETH_ALEN];
949 u8 src_mac[ETH_ALEN];
950 u8 src_mac_msk[ETH_ALEN];
951 u8 ether_type_enable;
952 __be16 ether_type;
953 __be16 vlan_id_msk;
954 __be16 vlan_id;
955};
956
957struct mlx4_spec_tcp_udp {
958 __be16 dst_port;
959 __be16 dst_port_msk;
960 __be16 src_port;
961 __be16 src_port_msk;
962};
963
964struct mlx4_spec_ipv4 {
965 __be32 dst_ip;
966 __be32 dst_ip_msk;
967 __be32 src_ip;
968 __be32 src_ip_msk;
969};
970
971struct mlx4_spec_ib {
972 __be32 l3_qpn;
973 __be32 qpn_msk;
974 u8 dst_gid[16];
975 u8 dst_gid_msk[16];
976};
977
978struct mlx4_spec_vxlan {
979 __be32 vni;
980 __be32 vni_mask;
981
982};
983
984struct mlx4_spec_list {
985 struct list_head list;
986 enum mlx4_net_trans_rule_id id;
987 union {
988 struct mlx4_spec_eth eth;
989 struct mlx4_spec_ib ib;
990 struct mlx4_spec_ipv4 ipv4;
991 struct mlx4_spec_tcp_udp tcp_udp;
992 struct mlx4_spec_vxlan vxlan;
993 };
994};
995
996enum mlx4_net_trans_hw_rule_queue {
997 MLX4_NET_TRANS_Q_FIFO,
998 MLX4_NET_TRANS_Q_LIFO,
999};
1000
1001struct mlx4_net_trans_rule {
1002 struct list_head list;
1003 enum mlx4_net_trans_hw_rule_queue queue_mode;
1004 bool exclusive;
1005 bool allow_loopback;
1006 enum mlx4_net_trans_promisc_mode promisc_mode;
1007 u8 port;
1008 u16 priority;
1009 u32 qpn;
1010};
1011
1012struct mlx4_net_trans_rule_hw_ctrl {
1013 __be16 prio;
1014 u8 type;
1015 u8 flags;
1016 u8 rsvd1;
1017 u8 funcid;
1018 u8 vep;
1019 u8 port;
1020 __be32 qpn;
1021 __be32 rsvd2;
1022};
1023
1024struct mlx4_net_trans_rule_hw_ib {
1025 u8 size;
1026 u8 rsvd1;
1027 __be16 id;
1028 u32 rsvd2;
1029 __be32 l3_qpn;
1030 __be32 qpn_mask;
1031 u8 dst_gid[16];
1032 u8 dst_gid_msk[16];
1033} __packed;
1034
1035struct mlx4_net_trans_rule_hw_eth {
1036 u8 size;
1037 u8 rsvd;
1038 __be16 id;
1039 u8 rsvd1[6];
1040 u8 dst_mac[6];
1041 u16 rsvd2;
1042 u8 dst_mac_msk[6];
1043 u16 rsvd3;
1044 u8 src_mac[6];
1045 u16 rsvd4;
1046 u8 src_mac_msk[6];
1047 u8 rsvd5;
1048 u8 ether_type_enable;
1049 __be16 ether_type;
1050 __be16 vlan_tag_msk;
1051 __be16 vlan_tag;
1052} __packed;
1053
1054struct mlx4_net_trans_rule_hw_tcp_udp {
1055 u8 size;
1056 u8 rsvd;
1057 __be16 id;
1058 __be16 rsvd1[3];
1059 __be16 dst_port;
1060 __be16 rsvd2;
1061 __be16 dst_port_msk;
1062 __be16 rsvd3;
1063 __be16 src_port;
1064 __be16 rsvd4;
1065 __be16 src_port_msk;
1066} __packed;
1067
1068struct mlx4_net_trans_rule_hw_ipv4 {
1069 u8 size;
1070 u8 rsvd;
1071 __be16 id;
1072 __be32 rsvd1;
1073 __be32 dst_ip;
1074 __be32 dst_ip_msk;
1075 __be32 src_ip;
1076 __be32 src_ip_msk;
1077} __packed;
1078
1079struct mlx4_net_trans_rule_hw_vxlan {
1080 u8 size;
1081 u8 rsvd;
1082 __be16 id;
1083 __be32 rsvd1;
1084 __be32 vni;
1085 __be32 vni_mask;
1086} __packed;
1087
1088struct _rule_hw {
1089 union {
1090 struct {
1091 u8 size;
1092 u8 rsvd;
1093 __be16 id;
1094 };
1095 struct mlx4_net_trans_rule_hw_eth eth;
1096 struct mlx4_net_trans_rule_hw_ib ib;
1097 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1098 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1099 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1100 };
1101};
1102
1103enum {
1104 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1105 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1106 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1107 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1108 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1109};
1110
1111
1112int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1113 enum mlx4_net_trans_promisc_mode mode);
1114int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1115 enum mlx4_net_trans_promisc_mode mode);
1116int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1117int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1118int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1119int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1120int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1121
1122int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1123void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1124int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1125int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1126void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1127int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1128 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1129int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1130 u8 promisc);
1131int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1132int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1133 u8 *pg, u16 *ratelimit);
1134int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering);
1135int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1136int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1137int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1138void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1139
1140int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1141 int npages, u64 iova, u32 *lkey, u32 *rkey);
1142int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1143 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1144int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1145void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1146 u32 *lkey, u32 *rkey);
1147int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1148int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1149int mlx4_test_interrupts(struct mlx4_dev *dev);
1150int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1151 int *vector);
1152void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1153
1154int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1155int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1156int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1157
1158int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1159void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1160
1161int mlx4_flow_attach(struct mlx4_dev *dev,
1162 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1163int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1164int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1165 enum mlx4_net_trans_promisc_mode flow_type);
1166int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1167 enum mlx4_net_trans_rule_id id);
1168int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1169
1170void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1171 int i, int val);
1172
1173int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1174
1175int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1176int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1177int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1178int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1179int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1180enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1181int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1182
1183void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1184__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1185
1186int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1187 u32 max_range_qpn);
1188
1189cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1190
1191#endif
1192
