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10#ifndef LINUX_MMC_HOST_H
11#define LINUX_MMC_HOST_H
12
13#include <linux/leds.h>
14#include <linux/mutex.h>
15#include <linux/sched.h>
16#include <linux/device.h>
17#include <linux/fault-inject.h>
18
19#include <linux/mmc/core.h>
20#include <linux/mmc/pm.h>
21
22struct mmc_ios {
23 unsigned int clock;
24 unsigned short vdd;
25
26
27
28 unsigned char bus_mode;
29
30#define MMC_BUSMODE_OPENDRAIN 1
31#define MMC_BUSMODE_PUSHPULL 2
32
33 unsigned char chip_select;
34
35#define MMC_CS_DONTCARE 0
36#define MMC_CS_HIGH 1
37#define MMC_CS_LOW 2
38
39 unsigned char power_mode;
40
41#define MMC_POWER_OFF 0
42#define MMC_POWER_UP 1
43#define MMC_POWER_ON 2
44
45 unsigned char bus_width;
46
47#define MMC_BUS_WIDTH_1 0
48#define MMC_BUS_WIDTH_4 2
49#define MMC_BUS_WIDTH_8 3
50
51 unsigned char timing;
52
53#define MMC_TIMING_LEGACY 0
54#define MMC_TIMING_MMC_HS 1
55#define MMC_TIMING_SD_HS 2
56#define MMC_TIMING_UHS_SDR12 3
57#define MMC_TIMING_UHS_SDR25 4
58#define MMC_TIMING_UHS_SDR50 5
59#define MMC_TIMING_UHS_SDR104 6
60#define MMC_TIMING_UHS_DDR50 7
61#define MMC_TIMING_MMC_HS200 8
62
63#define MMC_SDR_MODE 0
64#define MMC_1_2V_DDR_MODE 1
65#define MMC_1_8V_DDR_MODE 2
66#define MMC_1_2V_SDR_MODE 3
67#define MMC_1_8V_SDR_MODE 4
68
69 unsigned char signal_voltage;
70
71#define MMC_SIGNAL_VOLTAGE_330 0
72#define MMC_SIGNAL_VOLTAGE_180 1
73#define MMC_SIGNAL_VOLTAGE_120 2
74
75 unsigned char drv_type;
76
77#define MMC_SET_DRIVER_TYPE_B 0
78#define MMC_SET_DRIVER_TYPE_A 1
79#define MMC_SET_DRIVER_TYPE_C 2
80#define MMC_SET_DRIVER_TYPE_D 3
81};
82
83struct mmc_host_ops {
84
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87
88 int (*enable)(struct mmc_host *host);
89 int (*disable)(struct mmc_host *host);
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98 void (*post_req)(struct mmc_host *host, struct mmc_request *req,
99 int err);
100 void (*pre_req)(struct mmc_host *host, struct mmc_request *req,
101 bool is_first_req);
102 void (*request)(struct mmc_host *host, struct mmc_request *req);
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123 void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
124 int (*get_ro)(struct mmc_host *host);
125 int (*get_cd)(struct mmc_host *host);
126
127 void (*enable_sdio_irq)(struct mmc_host *host, int enable);
128
129
130 void (*init_card)(struct mmc_host *host, struct mmc_card *card);
131
132 int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
133
134
135 int (*card_busy)(struct mmc_host *host);
136
137
138 int (*execute_tuning)(struct mmc_host *host, u32 opcode);
139 int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv);
140 void (*hw_reset)(struct mmc_host *host);
141 void (*card_event)(struct mmc_host *host);
142};
143
144struct mmc_card;
145struct device;
146
147struct mmc_async_req {
148
149 struct mmc_request *mrq;
150
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153
154 int (*err_check) (struct mmc_card *, struct mmc_async_req *);
155};
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168
169struct mmc_slot {
170 int cd_irq;
171 struct mutex lock;
172 void *handler_priv;
173};
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182
183struct mmc_context_info {
184 bool is_done_rcv;
185 bool is_new_req;
186 bool is_waiting_last_req;
187 wait_queue_head_t wait;
188 spinlock_t lock;
189};
190
191struct regulator;
192
193struct mmc_supply {
194 struct regulator *vmmc;
195 struct regulator *vqmmc;
196};
197
198struct mmc_host {
199 struct device *parent;
200 struct device class_dev;
201 int index;
202 const struct mmc_host_ops *ops;
203 unsigned int f_min;
204 unsigned int f_max;
205 unsigned int f_init;
206 u32 ocr_avail;
207 u32 ocr_avail_sdio;
208 u32 ocr_avail_sd;
209 u32 ocr_avail_mmc;
210 struct notifier_block pm_notify;
211 u32 max_current_330;
212 u32 max_current_300;
213 u32 max_current_180;
214
215#define MMC_VDD_165_195 0x00000080
216#define MMC_VDD_20_21 0x00000100
217#define MMC_VDD_21_22 0x00000200
218#define MMC_VDD_22_23 0x00000400
219#define MMC_VDD_23_24 0x00000800
220#define MMC_VDD_24_25 0x00001000
221#define MMC_VDD_25_26 0x00002000
222#define MMC_VDD_26_27 0x00004000
223#define MMC_VDD_27_28 0x00008000
224#define MMC_VDD_28_29 0x00010000
225#define MMC_VDD_29_30 0x00020000
226#define MMC_VDD_30_31 0x00040000
227#define MMC_VDD_31_32 0x00080000
228#define MMC_VDD_32_33 0x00100000
229#define MMC_VDD_33_34 0x00200000
230#define MMC_VDD_34_35 0x00400000
231#define MMC_VDD_35_36 0x00800000
232
233 u32 caps;
234
235#define MMC_CAP_4_BIT_DATA (1 << 0)
236#define MMC_CAP_MMC_HIGHSPEED (1 << 1)
237#define MMC_CAP_SD_HIGHSPEED (1 << 2)
238#define MMC_CAP_SDIO_IRQ (1 << 3)
239#define MMC_CAP_SPI (1 << 4)
240#define MMC_CAP_NEEDS_POLL (1 << 5)
241#define MMC_CAP_8_BIT_DATA (1 << 6)
242#define MMC_CAP_AGGRESSIVE_PM (1 << 7)
243#define MMC_CAP_NONREMOVABLE (1 << 8)
244#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9)
245#define MMC_CAP_ERASE (1 << 10)
246#define MMC_CAP_1_8V_DDR (1 << 11)
247
248#define MMC_CAP_1_2V_DDR (1 << 12)
249
250#define MMC_CAP_POWER_OFF_CARD (1 << 13)
251#define MMC_CAP_BUS_WIDTH_TEST (1 << 14)
252#define MMC_CAP_UHS_SDR12 (1 << 15)
253#define MMC_CAP_UHS_SDR25 (1 << 16)
254#define MMC_CAP_UHS_SDR50 (1 << 17)
255#define MMC_CAP_UHS_SDR104 (1 << 18)
256#define MMC_CAP_UHS_DDR50 (1 << 19)
257#define MMC_CAP_RUNTIME_RESUME (1 << 20)
258#define MMC_CAP_DRIVER_TYPE_A (1 << 23)
259#define MMC_CAP_DRIVER_TYPE_C (1 << 24)
260#define MMC_CAP_DRIVER_TYPE_D (1 << 25)
261#define MMC_CAP_CMD23 (1 << 30)
262#define MMC_CAP_HW_RESET (1 << 31)
263
264 u32 caps2;
265
266#define MMC_CAP2_BOOTPART_NOACC (1 << 0)
267#define MMC_CAP2_CACHE_CTRL (1 << 1)
268#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2)
269#define MMC_CAP2_NO_MULTI_READ (1 << 3)
270#define MMC_CAP2_NO_SLEEP_CMD (1 << 4)
271#define MMC_CAP2_HS200_1_8V_SDR (1 << 5)
272#define MMC_CAP2_HS200_1_2V_SDR (1 << 6)
273#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
274 MMC_CAP2_HS200_1_2V_SDR)
275#define MMC_CAP2_BROKEN_VOLTAGE (1 << 7)
276#define MMC_CAP2_HC_ERASE_SZ (1 << 9)
277#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10)
278#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11)
279#define MMC_CAP2_PACKED_RD (1 << 12)
280#define MMC_CAP2_PACKED_WR (1 << 13)
281#define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \
282 MMC_CAP2_PACKED_WR)
283#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14)
284#define MMC_CAP2_SANITIZE (1 << 15)
285
286 mmc_pm_flag_t pm_caps;
287
288#ifdef CONFIG_MMC_CLKGATE
289 int clk_requests;
290 unsigned int clk_delay;
291 bool clk_gated;
292 struct delayed_work clk_gate_work;
293 unsigned int clk_old;
294 spinlock_t clk_lock;
295 struct mutex clk_gate_mutex;
296 struct device_attribute clkgate_delay_attr;
297 unsigned long clkgate_delay;
298#endif
299
300
301 unsigned int max_seg_size;
302 unsigned short max_segs;
303 unsigned short unused;
304 unsigned int max_req_size;
305 unsigned int max_blk_size;
306 unsigned int max_blk_count;
307 unsigned int max_discard_to;
308
309
310 spinlock_t lock;
311
312 struct mmc_ios ios;
313
314
315 unsigned int use_spi_crc:1;
316 unsigned int claimed:1;
317 unsigned int bus_dead:1;
318#ifdef CONFIG_MMC_DEBUG
319 unsigned int removed:1;
320#endif
321
322 int rescan_disable;
323 int rescan_entered;
324
325 struct mmc_card *card;
326
327 wait_queue_head_t wq;
328 struct task_struct *claimer;
329 int claim_cnt;
330
331 struct delayed_work detect;
332 int detect_change;
333 struct mmc_slot slot;
334
335 const struct mmc_bus_ops *bus_ops;
336 unsigned int bus_refs;
337
338 unsigned int sdio_irqs;
339 struct task_struct *sdio_irq_thread;
340 bool sdio_irq_pending;
341 atomic_t sdio_irq_thread_abort;
342
343 mmc_pm_flag_t pm_flags;
344
345 struct led_trigger *led;
346
347#ifdef CONFIG_REGULATOR
348 bool regulator_enabled;
349#endif
350 struct mmc_supply supply;
351
352 struct dentry *debugfs_root;
353
354 struct mmc_async_req *areq;
355 struct mmc_context_info context_info;
356
357#ifdef CONFIG_FAIL_MMC_REQUEST
358 struct fault_attr fail_mmc_request;
359#endif
360
361 unsigned int actual_clock;
362
363 unsigned int slotno;
364
365 unsigned long private[0] ____cacheline_aligned;
366};
367
368struct mmc_host *mmc_alloc_host(int extra, struct device *);
369int mmc_add_host(struct mmc_host *);
370void mmc_remove_host(struct mmc_host *);
371void mmc_free_host(struct mmc_host *);
372int mmc_of_parse(struct mmc_host *host);
373
374static inline void *mmc_priv(struct mmc_host *host)
375{
376 return (void *)host->private;
377}
378
379#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
380
381#define mmc_dev(x) ((x)->parent)
382#define mmc_classdev(x) (&(x)->class_dev)
383#define mmc_hostname(x) (dev_name(&(x)->class_dev))
384
385int mmc_power_save_host(struct mmc_host *host);
386int mmc_power_restore_host(struct mmc_host *host);
387
388void mmc_detect_change(struct mmc_host *, unsigned long delay);
389void mmc_request_done(struct mmc_host *, struct mmc_request *);
390
391int mmc_cache_ctrl(struct mmc_host *, u8);
392
393static inline void mmc_signal_sdio_irq(struct mmc_host *host)
394{
395 host->ops->enable_sdio_irq(host, 0);
396 host->sdio_irq_pending = true;
397 wake_up_process(host->sdio_irq_thread);
398}
399
400#ifdef CONFIG_REGULATOR
401int mmc_regulator_get_ocrmask(struct regulator *supply);
402int mmc_regulator_set_ocr(struct mmc_host *mmc,
403 struct regulator *supply,
404 unsigned short vdd_bit);
405int mmc_regulator_get_supply(struct mmc_host *mmc);
406#else
407static inline int mmc_regulator_get_ocrmask(struct regulator *supply)
408{
409 return 0;
410}
411
412static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
413 struct regulator *supply,
414 unsigned short vdd_bit)
415{
416 return 0;
417}
418
419static inline int mmc_regulator_get_supply(struct mmc_host *mmc)
420{
421 return 0;
422}
423#endif
424
425int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
426
427
428extern bool mmc_assume_removable;
429
430static inline int mmc_card_is_removable(struct mmc_host *host)
431{
432 return !(host->caps & MMC_CAP_NONREMOVABLE) && mmc_assume_removable;
433}
434
435static inline int mmc_card_keep_power(struct mmc_host *host)
436{
437 return host->pm_flags & MMC_PM_KEEP_POWER;
438}
439
440static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
441{
442 return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
443}
444
445static inline int mmc_host_cmd23(struct mmc_host *host)
446{
447 return host->caps & MMC_CAP_CMD23;
448}
449
450static inline int mmc_boot_partition_access(struct mmc_host *host)
451{
452 return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC);
453}
454
455static inline int mmc_host_uhs(struct mmc_host *host)
456{
457 return host->caps &
458 (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
459 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
460 MMC_CAP_UHS_DDR50);
461}
462
463static inline int mmc_host_packed_wr(struct mmc_host *host)
464{
465 return host->caps2 & MMC_CAP2_PACKED_WR;
466}
467
468#ifdef CONFIG_MMC_CLKGATE
469void mmc_host_clk_hold(struct mmc_host *host);
470void mmc_host_clk_release(struct mmc_host *host);
471unsigned int mmc_host_clk_rate(struct mmc_host *host);
472
473#else
474static inline void mmc_host_clk_hold(struct mmc_host *host)
475{
476}
477
478static inline void mmc_host_clk_release(struct mmc_host *host)
479{
480}
481
482static inline unsigned int mmc_host_clk_rate(struct mmc_host *host)
483{
484 return host->ios.clock;
485}
486#endif
487#endif
488