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16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
19
20#include <linux/mod_devicetable.h>
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/list.h>
26#include <linux/compiler.h>
27#include <linux/errno.h>
28#include <linux/kobject.h>
29#include <linux/atomic.h>
30#include <linux/device.h>
31#include <linux/io.h>
32#include <linux/irqreturn.h>
33#include <uapi/linux/pci.h>
34
35#include <linux/pci_ids.h>
36
37
38
39
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41
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43
44
45
46
47
48
49#define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50
51#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52
53
54struct pci_slot {
55 struct pci_bus *bus;
56 struct list_head list;
57 struct hotplug_slot *hotplug;
58 unsigned char number;
59 struct kobject kobj;
60};
61
62static inline const char *pci_slot_name(const struct pci_slot *slot)
63{
64 return kobject_name(&slot->kobj);
65}
66
67
68enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71};
72
73
74#define PCI_DMA_BIDIRECTIONAL 0
75#define PCI_DMA_TODEVICE 1
76#define PCI_DMA_FROMDEVICE 2
77#define PCI_DMA_NONE 3
78
79
80
81
82enum {
83
84 PCI_STD_RESOURCES,
85 PCI_STD_RESOURCE_END = 5,
86
87
88 PCI_ROM_RESOURCE,
89
90
91#ifdef CONFIG_PCI_IOV
92 PCI_IOV_RESOURCES,
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
94#endif
95
96
97#define PCI_BRIDGE_RESOURCE_NUM 4
98
99 PCI_BRIDGE_RESOURCES,
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
102
103
104 PCI_NUM_RESOURCES,
105
106
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
108};
109
110typedef int __bitwise pci_power_t;
111
112#define PCI_D0 ((pci_power_t __force) 0)
113#define PCI_D1 ((pci_power_t __force) 1)
114#define PCI_D2 ((pci_power_t __force) 2)
115#define PCI_D3hot ((pci_power_t __force) 3)
116#define PCI_D3cold ((pci_power_t __force) 4)
117#define PCI_UNKNOWN ((pci_power_t __force) 5)
118#define PCI_POWER_ERROR ((pci_power_t __force) -1)
119
120
121extern const char *pci_power_names[];
122
123static inline const char *pci_power_name(pci_power_t state)
124{
125 return pci_power_names[1 + (int) state];
126}
127
128#define PCI_PM_D2_DELAY 200
129#define PCI_PM_D3_WAIT 10
130#define PCI_PM_D3COLD_WAIT 100
131#define PCI_PM_BUS_WAIT 50
132
133
134
135
136
137typedef unsigned int __bitwise pci_channel_state_t;
138
139enum pci_channel_state {
140
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142
143
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145
146
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148};
149
150typedef unsigned int __bitwise pcie_reset_state_t;
151
152enum pcie_reset_state {
153
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155
156
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158
159
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
161};
162
163typedef unsigned short __bitwise pci_dev_flags_t;
164enum pci_dev_flags {
165
166
167
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
169
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
171
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
173};
174
175enum pci_irq_reroute_variant {
176 INTEL_IRQ_REROUTE_VARIANT = 1,
177 MAX_IRQ_REROUTE_VARIANTS = 3
178};
179
180typedef unsigned short __bitwise pci_bus_flags_t;
181enum pci_bus_flags {
182 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
183 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
184};
185
186
187enum pcie_link_width {
188 PCIE_LNK_WIDTH_RESRV = 0x00,
189 PCIE_LNK_X1 = 0x01,
190 PCIE_LNK_X2 = 0x02,
191 PCIE_LNK_X4 = 0x04,
192 PCIE_LNK_X8 = 0x08,
193 PCIE_LNK_X12 = 0x0C,
194 PCIE_LNK_X16 = 0x10,
195 PCIE_LNK_X32 = 0x20,
196 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
197};
198
199
200enum pci_bus_speed {
201 PCI_SPEED_33MHz = 0x00,
202 PCI_SPEED_66MHz = 0x01,
203 PCI_SPEED_66MHz_PCIX = 0x02,
204 PCI_SPEED_100MHz_PCIX = 0x03,
205 PCI_SPEED_133MHz_PCIX = 0x04,
206 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
207 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
208 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
209 PCI_SPEED_66MHz_PCIX_266 = 0x09,
210 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
211 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
212 AGP_UNKNOWN = 0x0c,
213 AGP_1X = 0x0d,
214 AGP_2X = 0x0e,
215 AGP_4X = 0x0f,
216 AGP_8X = 0x10,
217 PCI_SPEED_66MHz_PCIX_533 = 0x11,
218 PCI_SPEED_100MHz_PCIX_533 = 0x12,
219 PCI_SPEED_133MHz_PCIX_533 = 0x13,
220 PCIE_SPEED_2_5GT = 0x14,
221 PCIE_SPEED_5_0GT = 0x15,
222 PCIE_SPEED_8_0GT = 0x16,
223 PCI_SPEED_UNKNOWN = 0xff,
224};
225
226struct pci_cap_saved_data {
227 u16 cap_nr;
228 bool cap_extended;
229 unsigned int size;
230 u32 data[0];
231};
232
233struct pci_cap_saved_state {
234 struct hlist_node next;
235 struct pci_cap_saved_data cap;
236};
237
238struct pcie_link_state;
239struct pci_vpd;
240struct pci_sriov;
241struct pci_ats;
242
243
244
245
246struct pci_dev {
247 struct list_head bus_list;
248 struct pci_bus *bus;
249 struct pci_bus *subordinate;
250
251 void *sysdata;
252 struct proc_dir_entry *procent;
253 struct pci_slot *slot;
254
255 unsigned int devfn;
256 unsigned short vendor;
257 unsigned short device;
258 unsigned short subsystem_vendor;
259 unsigned short subsystem_device;
260 unsigned int class;
261 u8 revision;
262 u8 hdr_type;
263 u8 pcie_cap;
264 u8 msi_cap;
265 u8 msix_cap;
266 u8 pcie_mpss:3;
267 u8 rom_base_reg;
268 u8 pin;
269 u16 pcie_flags_reg;
270
271 struct pci_driver *driver;
272 u64 dma_mask;
273
274
275
276
277
278 struct device_dma_parameters dma_parms;
279
280 pci_power_t current_state;
281
282
283 u8 pm_cap;
284 unsigned int pme_support:5;
285
286 unsigned int pme_interrupt:1;
287 unsigned int pme_poll:1;
288 unsigned int d1_support:1;
289 unsigned int d2_support:1;
290 unsigned int no_d1d2:1;
291 unsigned int no_d3cold:1;
292 unsigned int d3cold_allowed:1;
293 unsigned int mmio_always_on:1;
294
295 unsigned int wakeup_prepared:1;
296 unsigned int runtime_d3cold:1;
297
298
299
300 unsigned int d3_delay;
301 unsigned int d3cold_delay;
302
303#ifdef CONFIG_PCIEASPM
304 struct pcie_link_state *link_state;
305#endif
306
307 pci_channel_state_t error_state;
308 struct device dev;
309
310 int cfg_size;
311
312
313
314
315
316 unsigned int irq;
317 struct resource resource[DEVICE_COUNT_RESOURCE];
318
319 bool match_driver;
320
321 unsigned int transparent:1;
322 unsigned int multifunction:1;
323
324 unsigned int is_added:1;
325 unsigned int is_busmaster:1;
326 unsigned int no_msi:1;
327 unsigned int block_cfg_access:1;
328 unsigned int broken_parity_status:1;
329 unsigned int irq_reroute_variant:2;
330 unsigned int msi_enabled:1;
331 unsigned int msix_enabled:1;
332 unsigned int ari_enabled:1;
333 unsigned int is_managed:1;
334 unsigned int needs_freset:1;
335 unsigned int state_saved:1;
336 unsigned int is_physfn:1;
337 unsigned int is_virtfn:1;
338 unsigned int reset_fn:1;
339 unsigned int is_hotplug_bridge:1;
340 unsigned int __aer_firmware_first_valid:1;
341 unsigned int __aer_firmware_first:1;
342 unsigned int broken_intx_masking:1;
343 unsigned int io_window_1k:1;
344 pci_dev_flags_t dev_flags;
345 atomic_t enable_cnt;
346
347 u32 saved_config_space[16];
348 struct hlist_head saved_cap_space;
349 struct bin_attribute *rom_attr;
350 int rom_attr_enabled;
351 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
352 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
353#ifdef CONFIG_PCI_MSI
354 struct list_head msi_list;
355 const struct attribute_group **msi_irq_groups;
356#endif
357 struct pci_vpd *vpd;
358#ifdef CONFIG_PCI_ATS
359 union {
360 struct pci_sriov *sriov;
361 struct pci_dev *physfn;
362 };
363 struct pci_ats *ats;
364#endif
365 phys_addr_t rom;
366 size_t romlen;
367};
368
369static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
370{
371#ifdef CONFIG_PCI_IOV
372 if (dev->is_virtfn)
373 dev = dev->physfn;
374#endif
375 return dev;
376}
377
378struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
379
380#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
381#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
382
383static inline int pci_channel_offline(struct pci_dev *pdev)
384{
385 return (pdev->error_state != pci_channel_io_normal);
386}
387
388struct pci_host_bridge_window {
389 struct list_head list;
390 struct resource *res;
391 resource_size_t offset;
392};
393
394struct pci_host_bridge {
395 struct device dev;
396 struct pci_bus *bus;
397 struct list_head windows;
398 void (*release_fn)(struct pci_host_bridge *);
399 void *release_data;
400};
401
402#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
403void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
404 void (*release_fn)(struct pci_host_bridge *),
405 void *release_data);
406
407int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
408
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420
421
422#define PCI_SUBTRACTIVE_DECODE 0x1
423
424struct pci_bus_resource {
425 struct list_head list;
426 struct resource *res;
427 unsigned int flags;
428};
429
430#define PCI_REGION_FLAG_MASK 0x0fU
431
432struct pci_bus {
433 struct list_head node;
434 struct pci_bus *parent;
435 struct list_head children;
436 struct list_head devices;
437 struct pci_dev *self;
438 struct list_head slots;
439 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
440 struct list_head resources;
441 struct resource busn_res;
442
443 struct pci_ops *ops;
444 struct msi_chip *msi;
445 void *sysdata;
446 struct proc_dir_entry *procdir;
447
448 unsigned char number;
449 unsigned char primary;
450 unsigned char max_bus_speed;
451 unsigned char cur_bus_speed;
452
453 char name[48];
454
455 unsigned short bridge_ctl;
456 pci_bus_flags_t bus_flags;
457 struct device *bridge;
458 struct device dev;
459 struct bin_attribute *legacy_io;
460 struct bin_attribute *legacy_mem;
461 unsigned int is_added:1;
462};
463
464#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
465#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
466
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473
474
475static inline bool pci_is_root_bus(struct pci_bus *pbus)
476{
477 return !(pbus->parent);
478}
479
480static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
481{
482 dev = pci_physfn(dev);
483 if (pci_is_root_bus(dev->bus))
484 return NULL;
485
486 return dev->bus->self;
487}
488
489#ifdef CONFIG_PCI_MSI
490static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
491{
492 return pci_dev->msi_enabled || pci_dev->msix_enabled;
493}
494#else
495static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
496#endif
497
498
499
500
501#define PCIBIOS_SUCCESSFUL 0x00
502#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
503#define PCIBIOS_BAD_VENDOR_ID 0x83
504#define PCIBIOS_DEVICE_NOT_FOUND 0x86
505#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
506#define PCIBIOS_SET_FAILED 0x88
507#define PCIBIOS_BUFFER_TOO_SMALL 0x89
508
509
510
511
512static inline int pcibios_err_to_errno(int err)
513{
514 if (err <= PCIBIOS_SUCCESSFUL)
515 return err;
516
517 switch (err) {
518 case PCIBIOS_FUNC_NOT_SUPPORTED:
519 return -ENOENT;
520 case PCIBIOS_BAD_VENDOR_ID:
521 return -EINVAL;
522 case PCIBIOS_DEVICE_NOT_FOUND:
523 return -ENODEV;
524 case PCIBIOS_BAD_REGISTER_NUMBER:
525 return -EFAULT;
526 case PCIBIOS_SET_FAILED:
527 return -EIO;
528 case PCIBIOS_BUFFER_TOO_SMALL:
529 return -ENOSPC;
530 }
531
532 return -ENOTTY;
533}
534
535
536
537struct pci_ops {
538 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
539 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
540};
541
542
543
544
545
546int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
547 int reg, int len, u32 *val);
548int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
549 int reg, int len, u32 val);
550
551struct pci_bus_region {
552 dma_addr_t start;
553 dma_addr_t end;
554};
555
556struct pci_dynids {
557 spinlock_t lock;
558 struct list_head list;
559};
560
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567
568
569typedef unsigned int __bitwise pci_ers_result_t;
570
571enum pci_ers_result {
572
573 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
574
575
576 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
577
578
579 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
580
581
582 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
583
584
585 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
586
587
588 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
589};
590
591
592struct pci_error_handlers {
593
594 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
595 enum pci_channel_state error);
596
597
598 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
599
600
601 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
602
603
604 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
605
606
607 void (*resume)(struct pci_dev *dev);
608};
609
610
611struct module;
612struct pci_driver {
613 struct list_head node;
614 const char *name;
615 const struct pci_device_id *id_table;
616 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id);
617 void (*remove) (struct pci_dev *dev);
618 int (*suspend) (struct pci_dev *dev, pm_message_t state);
619 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
620 int (*resume_early) (struct pci_dev *dev);
621 int (*resume) (struct pci_dev *dev);
622 void (*shutdown) (struct pci_dev *dev);
623 int (*sriov_configure) (struct pci_dev *dev, int num_vfs);
624 const struct pci_error_handlers *err_handler;
625 struct device_driver driver;
626 struct pci_dynids dynids;
627};
628
629#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
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631
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635
636
637#define DEFINE_PCI_DEVICE_TABLE(_table) \
638 const struct pci_device_id _table[]
639
640
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647
648
649#define PCI_DEVICE(vend,dev) \
650 .vendor = (vend), .device = (dev), \
651 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
652
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661
662
663#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
664 .vendor = (vend), .device = (dev), \
665 .subvendor = (subvend), .subdevice = (subdev)
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674
675
676#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
677 .class = (dev_class), .class_mask = (dev_class_mask), \
678 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
679 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
680
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689
690
691
692#define PCI_VDEVICE(vendor, device) \
693 PCI_VENDOR_ID_##vendor, (device), \
694 PCI_ANY_ID, PCI_ANY_ID, 0, 0
695
696
697#ifdef CONFIG_PCI
698
699void pcie_bus_configure_settings(struct pci_bus *bus);
700
701enum pcie_bus_config_types {
702 PCIE_BUS_TUNE_OFF,
703 PCIE_BUS_SAFE,
704 PCIE_BUS_PERFORMANCE,
705 PCIE_BUS_PEER2PEER,
706};
707
708extern enum pcie_bus_config_types pcie_bus_config;
709
710extern struct bus_type pci_bus_type;
711
712
713
714extern struct list_head pci_root_buses;
715
716int no_pci_devices(void);
717
718void pcibios_resource_survey_bus(struct pci_bus *bus);
719void pcibios_add_bus(struct pci_bus *bus);
720void pcibios_remove_bus(struct pci_bus *bus);
721void pcibios_fixup_bus(struct pci_bus *);
722int __must_check pcibios_enable_device(struct pci_dev *, int mask);
723
724char *pcibios_setup(char *str);
725
726
727resource_size_t pcibios_align_resource(void *, const struct resource *,
728 resource_size_t,
729 resource_size_t);
730void pcibios_update_irq(struct pci_dev *, int irq);
731
732
733void pci_fixup_cardbus(struct pci_bus *);
734
735
736
737void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
738 struct resource *res);
739void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
740 struct pci_bus_region *region);
741void pcibios_scan_specific_bus(int busn);
742struct pci_bus *pci_find_bus(int domain, int busnr);
743void pci_bus_add_devices(const struct pci_bus *bus);
744struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
745 struct pci_ops *ops, void *sysdata);
746struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
747struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
748 struct pci_ops *ops, void *sysdata,
749 struct list_head *resources);
750int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
751int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
752void pci_bus_release_busn_res(struct pci_bus *b);
753struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
754 struct pci_ops *ops, void *sysdata,
755 struct list_head *resources);
756struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
757 int busnr);
758void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
759struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
760 const char *name,
761 struct hotplug_slot *hotplug);
762void pci_destroy_slot(struct pci_slot *slot);
763int pci_scan_slot(struct pci_bus *bus, int devfn);
764struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
765void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
766unsigned int pci_scan_child_bus(struct pci_bus *bus);
767int __must_check pci_bus_add_device(struct pci_dev *dev);
768void pci_read_bridge_bases(struct pci_bus *child);
769struct resource *pci_find_parent_resource(const struct pci_dev *dev,
770 struct resource *res);
771u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
772int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
773u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
774struct pci_dev *pci_dev_get(struct pci_dev *dev);
775void pci_dev_put(struct pci_dev *dev);
776void pci_remove_bus(struct pci_bus *b);
777void pci_stop_and_remove_bus_device(struct pci_dev *dev);
778void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
779void pci_stop_root_bus(struct pci_bus *bus);
780void pci_remove_root_bus(struct pci_bus *bus);
781void pci_setup_cardbus(struct pci_bus *bus);
782void pci_sort_breadthfirst(void);
783#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
784#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
785#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
786
787
788
789enum pci_lost_interrupt_reason {
790 PCI_LOST_IRQ_NO_INFORMATION = 0,
791 PCI_LOST_IRQ_DISABLE_MSI,
792 PCI_LOST_IRQ_DISABLE_MSIX,
793 PCI_LOST_IRQ_DISABLE_ACPI,
794};
795enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
796int pci_find_capability(struct pci_dev *dev, int cap);
797int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
798int pci_find_ext_capability(struct pci_dev *dev, int cap);
799int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
800int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
801int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
802struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
803
804struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
805 struct pci_dev *from);
806struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
807 unsigned int ss_vendor, unsigned int ss_device,
808 struct pci_dev *from);
809struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
810struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
811 unsigned int devfn);
812static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
813 unsigned int devfn)
814{
815 return pci_get_domain_bus_and_slot(0, bus, devfn);
816}
817struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
818int pci_dev_present(const struct pci_device_id *ids);
819
820int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
821 int where, u8 *val);
822int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
823 int where, u16 *val);
824int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
825 int where, u32 *val);
826int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
827 int where, u8 val);
828int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
829 int where, u16 val);
830int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
831 int where, u32 val);
832struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
833
834static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
835{
836 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
837}
838static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
839{
840 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
841}
842static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
843 u32 *val)
844{
845 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
846}
847static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
848{
849 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
850}
851static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
852{
853 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
854}
855static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
856 u32 val)
857{
858 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
859}
860
861int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
862int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
863int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
864int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
865int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
866 u16 clear, u16 set);
867int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
868 u32 clear, u32 set);
869
870static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
871 u16 set)
872{
873 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
874}
875
876static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
877 u32 set)
878{
879 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
880}
881
882static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
883 u16 clear)
884{
885 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
886}
887
888static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
889 u32 clear)
890{
891 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
892}
893
894
895int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
896int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
897int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
898int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
899int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
900int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
901
902int __must_check pci_enable_device(struct pci_dev *dev);
903int __must_check pci_enable_device_io(struct pci_dev *dev);
904int __must_check pci_enable_device_mem(struct pci_dev *dev);
905int __must_check pci_reenable_device(struct pci_dev *);
906int __must_check pcim_enable_device(struct pci_dev *pdev);
907void pcim_pin_device(struct pci_dev *pdev);
908
909static inline int pci_is_enabled(struct pci_dev *pdev)
910{
911 return (atomic_read(&pdev->enable_cnt) > 0);
912}
913
914static inline int pci_is_managed(struct pci_dev *pdev)
915{
916 return pdev->is_managed;
917}
918
919void pci_disable_device(struct pci_dev *dev);
920
921extern unsigned int pcibios_max_latency;
922void pci_set_master(struct pci_dev *dev);
923void pci_clear_master(struct pci_dev *dev);
924
925int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
926int pci_set_cacheline_size(struct pci_dev *dev);
927#define HAVE_PCI_SET_MWI
928int __must_check pci_set_mwi(struct pci_dev *dev);
929int pci_try_set_mwi(struct pci_dev *dev);
930void pci_clear_mwi(struct pci_dev *dev);
931void pci_intx(struct pci_dev *dev, int enable);
932bool pci_intx_mask_supported(struct pci_dev *dev);
933bool pci_check_and_mask_intx(struct pci_dev *dev);
934bool pci_check_and_unmask_intx(struct pci_dev *dev);
935void pci_msi_off(struct pci_dev *dev);
936int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
937int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
938int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
939int pci_wait_for_pending_transaction(struct pci_dev *dev);
940int pcix_get_max_mmrbc(struct pci_dev *dev);
941int pcix_get_mmrbc(struct pci_dev *dev);
942int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
943int pcie_get_readrq(struct pci_dev *dev);
944int pcie_set_readrq(struct pci_dev *dev, int rq);
945int pcie_get_mps(struct pci_dev *dev);
946int pcie_set_mps(struct pci_dev *dev, int mps);
947int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
948 enum pcie_link_width *width);
949int __pci_reset_function(struct pci_dev *dev);
950int __pci_reset_function_locked(struct pci_dev *dev);
951int pci_reset_function(struct pci_dev *dev);
952int pci_try_reset_function(struct pci_dev *dev);
953int pci_probe_reset_slot(struct pci_slot *slot);
954int pci_reset_slot(struct pci_slot *slot);
955int pci_try_reset_slot(struct pci_slot *slot);
956int pci_probe_reset_bus(struct pci_bus *bus);
957int pci_reset_bus(struct pci_bus *bus);
958int pci_try_reset_bus(struct pci_bus *bus);
959void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
960void pci_update_resource(struct pci_dev *dev, int resno);
961int __must_check pci_assign_resource(struct pci_dev *dev, int i);
962int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
963int pci_select_bars(struct pci_dev *dev, unsigned long flags);
964bool pci_device_is_present(struct pci_dev *pdev);
965
966
967int pci_enable_rom(struct pci_dev *pdev);
968void pci_disable_rom(struct pci_dev *pdev);
969void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
970void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
971size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
972void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
973
974
975int pci_save_state(struct pci_dev *dev);
976void pci_restore_state(struct pci_dev *dev);
977struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
978int pci_load_and_free_saved_state(struct pci_dev *dev,
979 struct pci_saved_state **state);
980struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
981struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
982 u16 cap);
983int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
984int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
985 u16 cap, unsigned int size);
986int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
987int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
988pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
989bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
990void pci_pme_active(struct pci_dev *dev, bool enable);
991int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
992 bool runtime, bool enable);
993int pci_wake_from_d3(struct pci_dev *dev, bool enable);
994int pci_prepare_to_sleep(struct pci_dev *dev);
995int pci_back_from_sleep(struct pci_dev *dev);
996bool pci_dev_run_wake(struct pci_dev *dev);
997bool pci_check_pme_status(struct pci_dev *dev);
998void pci_pme_wakeup_bus(struct pci_bus *bus);
999
1000static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1001 bool enable)
1002{
1003 return __pci_enable_wake(dev, state, false, enable);
1004}
1005
1006
1007int pci_save_vc_state(struct pci_dev *dev);
1008void pci_restore_vc_state(struct pci_dev *dev);
1009void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1010
1011
1012void set_pcie_port_type(struct pci_dev *pdev);
1013void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1014
1015
1016int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1017unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1018unsigned int pci_rescan_bus(struct pci_bus *bus);
1019void pci_lock_rescan_remove(void);
1020void pci_unlock_rescan_remove(void);
1021
1022
1023ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1024ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1025
1026
1027resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1028void pci_bus_assign_resources(const struct pci_bus *bus);
1029void pci_bus_size_bridges(struct pci_bus *bus);
1030int pci_claim_resource(struct pci_dev *, int);
1031void pci_assign_unassigned_resources(void);
1032void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1033void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1034void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1035void pdev_enable_device(struct pci_dev *);
1036int pci_enable_resources(struct pci_dev *, int mask);
1037void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1038 int (*)(const struct pci_dev *, u8, u8));
1039#define HAVE_PCI_REQ_REGIONS 2
1040int __must_check pci_request_regions(struct pci_dev *, const char *);
1041int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1042void pci_release_regions(struct pci_dev *);
1043int __must_check pci_request_region(struct pci_dev *, int, const char *);
1044int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1045void pci_release_region(struct pci_dev *, int);
1046int pci_request_selected_regions(struct pci_dev *, int, const char *);
1047int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1048void pci_release_selected_regions(struct pci_dev *, int);
1049
1050
1051struct pci_bus *pci_bus_get(struct pci_bus *bus);
1052void pci_bus_put(struct pci_bus *bus);
1053void pci_add_resource(struct list_head *resources, struct resource *res);
1054void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1055 resource_size_t offset);
1056void pci_free_resource_list(struct list_head *resources);
1057void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1058struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1059void pci_bus_remove_resources(struct pci_bus *bus);
1060
1061#define pci_bus_for_each_resource(bus, res, i) \
1062 for (i = 0; \
1063 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1064 i++)
1065
1066int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1067 struct resource *res, resource_size_t size,
1068 resource_size_t align, resource_size_t min,
1069 unsigned int type_mask,
1070 resource_size_t (*alignf)(void *,
1071 const struct resource *,
1072 resource_size_t,
1073 resource_size_t),
1074 void *alignf_data);
1075
1076static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1077{
1078 struct pci_bus_region region;
1079
1080 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1081 return region.start;
1082}
1083
1084
1085int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1086 const char *mod_name);
1087
1088
1089
1090
1091#define pci_register_driver(driver) \
1092 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1093
1094void pci_unregister_driver(struct pci_driver *dev);
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104#define module_pci_driver(__pci_driver) \
1105 module_driver(__pci_driver, pci_register_driver, \
1106 pci_unregister_driver)
1107
1108struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1109int pci_add_dynid(struct pci_driver *drv,
1110 unsigned int vendor, unsigned int device,
1111 unsigned int subvendor, unsigned int subdevice,
1112 unsigned int class, unsigned int class_mask,
1113 unsigned long driver_data);
1114const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1115 struct pci_dev *dev);
1116int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1117 int pass);
1118
1119void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1120 void *userdata);
1121int pci_cfg_space_size(struct pci_dev *dev);
1122unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1123void pci_setup_bridge(struct pci_bus *bus);
1124resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1125 unsigned long type);
1126
1127#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1128#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1129
1130int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1131 unsigned int command_bits, u32 flags);
1132
1133
1134#include <linux/pci-dma.h>
1135#include <linux/dmapool.h>
1136
1137#define pci_pool dma_pool
1138#define pci_pool_create(name, pdev, size, align, allocation) \
1139 dma_pool_create(name, &pdev->dev, size, align, allocation)
1140#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1141#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1142#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1143
1144enum pci_dma_burst_strategy {
1145 PCI_DMA_BURST_INFINITY,
1146
1147 PCI_DMA_BURST_BOUNDARY,
1148
1149 PCI_DMA_BURST_MULTIPLE,
1150
1151};
1152
1153struct msix_entry {
1154 u32 vector;
1155 u16 entry;
1156};
1157
1158
1159#ifdef CONFIG_PCI_MSI
1160int pci_msi_vec_count(struct pci_dev *dev);
1161int pci_enable_msi_block(struct pci_dev *dev, int nvec);
1162void pci_msi_shutdown(struct pci_dev *dev);
1163void pci_disable_msi(struct pci_dev *dev);
1164int pci_msix_vec_count(struct pci_dev *dev);
1165int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1166void pci_msix_shutdown(struct pci_dev *dev);
1167void pci_disable_msix(struct pci_dev *dev);
1168void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1169void pci_restore_msi_state(struct pci_dev *dev);
1170int pci_msi_enabled(void);
1171int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1172static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1173{
1174 int rc = pci_enable_msi_range(dev, nvec, nvec);
1175 if (rc < 0)
1176 return rc;
1177 return 0;
1178}
1179int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1180 int minvec, int maxvec);
1181static inline int pci_enable_msix_exact(struct pci_dev *dev,
1182 struct msix_entry *entries, int nvec)
1183{
1184 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1185 if (rc < 0)
1186 return rc;
1187 return 0;
1188}
1189#else
1190static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1191static inline int pci_enable_msi_block(struct pci_dev *dev, int nvec)
1192{ return -ENOSYS; }
1193static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1194static inline void pci_disable_msi(struct pci_dev *dev) { }
1195static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1196static inline int pci_enable_msix(struct pci_dev *dev,
1197 struct msix_entry *entries, int nvec)
1198{ return -ENOSYS; }
1199static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1200static inline void pci_disable_msix(struct pci_dev *dev) { }
1201static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) { }
1202static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1203static inline int pci_msi_enabled(void) { return 0; }
1204static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1205 int maxvec)
1206{ return -ENOSYS; }
1207static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1208{ return -ENOSYS; }
1209static inline int pci_enable_msix_range(struct pci_dev *dev,
1210 struct msix_entry *entries, int minvec, int maxvec)
1211{ return -ENOSYS; }
1212static inline int pci_enable_msix_exact(struct pci_dev *dev,
1213 struct msix_entry *entries, int nvec)
1214{ return -ENOSYS; }
1215#endif
1216
1217#ifdef CONFIG_PCIEPORTBUS
1218extern bool pcie_ports_disabled;
1219extern bool pcie_ports_auto;
1220#else
1221#define pcie_ports_disabled true
1222#define pcie_ports_auto false
1223#endif
1224
1225#ifdef CONFIG_PCIEASPM
1226bool pcie_aspm_support_enabled(void);
1227#else
1228static inline bool pcie_aspm_support_enabled(void) { return false; }
1229#endif
1230
1231#ifdef CONFIG_PCIEAER
1232void pci_no_aer(void);
1233bool pci_aer_available(void);
1234#else
1235static inline void pci_no_aer(void) { }
1236static inline bool pci_aer_available(void) { return false; }
1237#endif
1238
1239#ifdef CONFIG_PCIE_ECRC
1240void pcie_set_ecrc_checking(struct pci_dev *dev);
1241void pcie_ecrc_get_policy(char *str);
1242#else
1243static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1244static inline void pcie_ecrc_get_policy(char *str) { }
1245#endif
1246
1247#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1248
1249#ifdef CONFIG_HT_IRQ
1250
1251int ht_create_irq(struct pci_dev *dev, int idx);
1252void ht_destroy_irq(unsigned int irq);
1253#endif
1254
1255void pci_cfg_access_lock(struct pci_dev *dev);
1256bool pci_cfg_access_trylock(struct pci_dev *dev);
1257void pci_cfg_access_unlock(struct pci_dev *dev);
1258
1259
1260
1261
1262
1263
1264#ifdef CONFIG_PCI_DOMAINS
1265extern int pci_domains_supported;
1266#else
1267enum { pci_domains_supported = 0 };
1268static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1269static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1270#endif
1271
1272
1273typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1274 unsigned int command_bits, u32 flags);
1275void pci_register_set_vga_state(arch_set_vga_state_t func);
1276
1277#else
1278
1279
1280
1281
1282
1283
1284#define _PCI_NOP(o, s, t) \
1285 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1286 int where, t val) \
1287 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1288
1289#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1290 _PCI_NOP(o, word, u16 x) \
1291 _PCI_NOP(o, dword, u32 x)
1292_PCI_NOP_ALL(read, *)
1293_PCI_NOP_ALL(write,)
1294
1295static inline struct pci_dev *pci_get_device(unsigned int vendor,
1296 unsigned int device,
1297 struct pci_dev *from)
1298{ return NULL; }
1299
1300static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1301 unsigned int device,
1302 unsigned int ss_vendor,
1303 unsigned int ss_device,
1304 struct pci_dev *from)
1305{ return NULL; }
1306
1307static inline struct pci_dev *pci_get_class(unsigned int class,
1308 struct pci_dev *from)
1309{ return NULL; }
1310
1311#define pci_dev_present(ids) (0)
1312#define no_pci_devices() (1)
1313#define pci_dev_put(dev) do { } while (0)
1314
1315static inline void pci_set_master(struct pci_dev *dev) { }
1316static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1317static inline void pci_disable_device(struct pci_dev *dev) { }
1318static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1319{ return -EIO; }
1320static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1321{ return -EIO; }
1322static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1323 unsigned int size)
1324{ return -EIO; }
1325static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1326 unsigned long mask)
1327{ return -EIO; }
1328static inline int pci_assign_resource(struct pci_dev *dev, int i)
1329{ return -EBUSY; }
1330static inline int __pci_register_driver(struct pci_driver *drv,
1331 struct module *owner)
1332{ return 0; }
1333static inline int pci_register_driver(struct pci_driver *drv)
1334{ return 0; }
1335static inline void pci_unregister_driver(struct pci_driver *drv) { }
1336static inline int pci_find_capability(struct pci_dev *dev, int cap)
1337{ return 0; }
1338static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1339 int cap)
1340{ return 0; }
1341static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1342{ return 0; }
1343
1344
1345static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1346static inline void pci_restore_state(struct pci_dev *dev) { }
1347static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1348{ return 0; }
1349static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1350{ return 0; }
1351static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1352 pm_message_t state)
1353{ return PCI_D0; }
1354static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1355 int enable)
1356{ return 0; }
1357
1358static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1359{ return -EIO; }
1360static inline void pci_release_regions(struct pci_dev *dev) { }
1361
1362#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1363
1364static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1365static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1366{ return 0; }
1367static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1368
1369static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1370{ return NULL; }
1371static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1372 unsigned int devfn)
1373{ return NULL; }
1374static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1375 unsigned int devfn)
1376{ return NULL; }
1377
1378static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1379static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1380
1381#define dev_is_pci(d) (false)
1382#define dev_is_pf(d) (false)
1383#define dev_num_vf(d) (0)
1384#endif
1385
1386
1387
1388#include <asm/pci.h>
1389
1390
1391
1392#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1393#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1394#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1395#define pci_resource_len(dev,bar) \
1396 ((pci_resource_start((dev), (bar)) == 0 && \
1397 pci_resource_end((dev), (bar)) == \
1398 pci_resource_start((dev), (bar))) ? 0 : \
1399 \
1400 (pci_resource_end((dev), (bar)) - \
1401 pci_resource_start((dev), (bar)) + 1))
1402
1403
1404
1405
1406
1407static inline void *pci_get_drvdata(struct pci_dev *pdev)
1408{
1409 return dev_get_drvdata(&pdev->dev);
1410}
1411
1412static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1413{
1414 dev_set_drvdata(&pdev->dev, data);
1415}
1416
1417
1418
1419
1420static inline const char *pci_name(const struct pci_dev *pdev)
1421{
1422 return dev_name(&pdev->dev);
1423}
1424
1425
1426
1427
1428
1429#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1430static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1431 const struct resource *rsrc, resource_size_t *start,
1432 resource_size_t *end)
1433{
1434 *start = rsrc->start;
1435 *end = rsrc->end;
1436}
1437#endif
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447struct pci_fixup {
1448 u16 vendor;
1449 u16 device;
1450 u32 class;
1451 unsigned int class_shift;
1452 void (*hook)(struct pci_dev *dev);
1453};
1454
1455enum pci_fixup_pass {
1456 pci_fixup_early,
1457 pci_fixup_header,
1458 pci_fixup_final,
1459 pci_fixup_enable,
1460 pci_fixup_resume,
1461 pci_fixup_suspend,
1462 pci_fixup_resume_early,
1463};
1464
1465
1466#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1467 class_shift, hook) \
1468 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1469 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1470 = { vendor, device, class, class_shift, hook };
1471
1472#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1473 class_shift, hook) \
1474 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1475 hook, vendor, device, class, class_shift, hook)
1476#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1477 class_shift, hook) \
1478 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1479 hook, vendor, device, class, class_shift, hook)
1480#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1481 class_shift, hook) \
1482 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1483 hook, vendor, device, class, class_shift, hook)
1484#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1485 class_shift, hook) \
1486 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1487 hook, vendor, device, class, class_shift, hook)
1488#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1489 class_shift, hook) \
1490 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1491 resume##hook, vendor, device, class, \
1492 class_shift, hook)
1493#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1494 class_shift, hook) \
1495 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1496 resume_early##hook, vendor, device, \
1497 class, class_shift, hook)
1498#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1499 class_shift, hook) \
1500 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1501 suspend##hook, vendor, device, class, \
1502 class_shift, hook)
1503
1504#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1505 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1506 hook, vendor, device, PCI_ANY_ID, 0, hook)
1507#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1508 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1509 hook, vendor, device, PCI_ANY_ID, 0, hook)
1510#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1511 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1512 hook, vendor, device, PCI_ANY_ID, 0, hook)
1513#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1514 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1515 hook, vendor, device, PCI_ANY_ID, 0, hook)
1516#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1517 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1518 resume##hook, vendor, device, \
1519 PCI_ANY_ID, 0, hook)
1520#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1521 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1522 resume_early##hook, vendor, device, \
1523 PCI_ANY_ID, 0, hook)
1524#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1525 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1526 suspend##hook, vendor, device, \
1527 PCI_ANY_ID, 0, hook)
1528
1529#ifdef CONFIG_PCI_QUIRKS
1530void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1531struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1532int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1533#else
1534static inline void pci_fixup_device(enum pci_fixup_pass pass,
1535 struct pci_dev *dev) { }
1536static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1537{
1538 return pci_dev_get(dev);
1539}
1540static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1541 u16 acs_flags)
1542{
1543 return -ENOTTY;
1544}
1545#endif
1546
1547void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1548void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1549void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1550int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1551int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1552 const char *name);
1553void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1554
1555extern int pci_pci_problems;
1556#define PCIPCI_FAIL 1
1557#define PCIPCI_TRITON 2
1558#define PCIPCI_NATOMA 4
1559#define PCIPCI_VIAETBF 8
1560#define PCIPCI_VSFX 16
1561#define PCIPCI_ALIMAGIK 32
1562#define PCIAGP_FAIL 64
1563
1564extern unsigned long pci_cardbus_io_size;
1565extern unsigned long pci_cardbus_mem_size;
1566extern u8 pci_dfl_cache_line_size;
1567extern u8 pci_cache_line_size;
1568
1569extern unsigned long pci_hotplug_io_size;
1570extern unsigned long pci_hotplug_mem_size;
1571
1572
1573int pcibios_add_platform_entries(struct pci_dev *dev);
1574void pcibios_disable_device(struct pci_dev *dev);
1575void pcibios_set_master(struct pci_dev *dev);
1576int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1577 enum pcie_reset_state state);
1578int pcibios_add_device(struct pci_dev *dev);
1579void pcibios_release_device(struct pci_dev *dev);
1580
1581#ifdef CONFIG_HIBERNATE_CALLBACKS
1582extern struct dev_pm_ops pcibios_pm_ops;
1583#endif
1584
1585#ifdef CONFIG_PCI_MMCONFIG
1586void __init pci_mmcfg_early_init(void);
1587void __init pci_mmcfg_late_init(void);
1588#else
1589static inline void pci_mmcfg_early_init(void) { }
1590static inline void pci_mmcfg_late_init(void) { }
1591#endif
1592
1593int pci_ext_cfg_avail(void);
1594
1595void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1596
1597#ifdef CONFIG_PCI_IOV
1598int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1599void pci_disable_sriov(struct pci_dev *dev);
1600irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1601int pci_num_vf(struct pci_dev *dev);
1602int pci_vfs_assigned(struct pci_dev *dev);
1603int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1604int pci_sriov_get_totalvfs(struct pci_dev *dev);
1605#else
1606static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1607{ return -ENODEV; }
1608static inline void pci_disable_sriov(struct pci_dev *dev) { }
1609static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1610{ return IRQ_NONE; }
1611static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1612static inline int pci_vfs_assigned(struct pci_dev *dev)
1613{ return 0; }
1614static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1615{ return 0; }
1616static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1617{ return 0; }
1618#endif
1619
1620#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1621void pci_hp_create_module_link(struct pci_slot *pci_slot);
1622void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1623#endif
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636static inline int pci_pcie_cap(struct pci_dev *dev)
1637{
1638 return dev->pcie_cap;
1639}
1640
1641
1642
1643
1644
1645
1646
1647static inline bool pci_is_pcie(struct pci_dev *dev)
1648{
1649 return pci_pcie_cap(dev);
1650}
1651
1652
1653
1654
1655
1656static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1657{
1658 return dev->pcie_flags_reg;
1659}
1660
1661
1662
1663
1664
1665static inline int pci_pcie_type(const struct pci_dev *dev)
1666{
1667 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1668}
1669
1670void pci_request_acs(void);
1671bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1672bool pci_acs_path_enabled(struct pci_dev *start,
1673 struct pci_dev *end, u16 acs_flags);
1674
1675#define PCI_VPD_LRDT 0x80
1676#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1677
1678
1679#define PCI_VPD_LTIN_ID_STRING 0x02
1680#define PCI_VPD_LTIN_RO_DATA 0x10
1681#define PCI_VPD_LTIN_RW_DATA 0x11
1682
1683#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1684#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1685#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1686
1687
1688#define PCI_VPD_STIN_END 0x78
1689
1690#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1691
1692#define PCI_VPD_SRDT_TIN_MASK 0x78
1693#define PCI_VPD_SRDT_LEN_MASK 0x07
1694
1695#define PCI_VPD_LRDT_TAG_SIZE 3
1696#define PCI_VPD_SRDT_TAG_SIZE 1
1697
1698#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1699
1700#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1701#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1702#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1703#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1704
1705
1706
1707
1708
1709
1710
1711static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1712{
1713 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1714}
1715
1716
1717
1718
1719
1720
1721
1722static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1723{
1724 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1725}
1726
1727
1728
1729
1730
1731
1732
1733static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1734{
1735 return info_field[2];
1736}
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1761 unsigned int len, const char *kw);
1762
1763
1764#ifdef CONFIG_OF
1765struct device_node;
1766void pci_set_of_node(struct pci_dev *dev);
1767void pci_release_of_node(struct pci_dev *dev);
1768void pci_set_bus_of_node(struct pci_bus *bus);
1769void pci_release_bus_of_node(struct pci_bus *bus);
1770
1771
1772struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1773
1774static inline struct device_node *
1775pci_device_to_OF_node(const struct pci_dev *pdev)
1776{
1777 return pdev ? pdev->dev.of_node : NULL;
1778}
1779
1780static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1781{
1782 return bus ? bus->dev.of_node : NULL;
1783}
1784
1785#else
1786static inline void pci_set_of_node(struct pci_dev *dev) { }
1787static inline void pci_release_of_node(struct pci_dev *dev) { }
1788static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1789static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1790#endif
1791
1792#ifdef CONFIG_EEH
1793static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1794{
1795 return pdev->dev.archdata.edev;
1796}
1797#endif
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1809
1810#endif
1811